DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed on July 6, 2026. Claims 1, 5, 8, and 16 have been amended. No claims have been added or canceled. Therefore, claims 1-16 are pending.
Applicant’s amendment to claims 1 and 16 renders moot the objection to the Drawings and the Specification.
Applicant’s amendments to claims 1, 5, and 8 successfully overcomes the 112(b) rejection of claims 1, 5, and 8 and dependent claims set forth in the previous Office Action.
Response to Arguments
Applicant’s arguments filed July 6, 2026, have been fully considered but they are not persuasive.
The Applicants argue:
Napetschnig fails to disclose the claimed “chemical solution”. As explained below, ordinarily skilled artisans understand that a “solution” requires more than one substance, including at least a solvent and one or more solutes. Napetschnig, however, discloses only water, which misidentified as “aqueous solution”:
….
Water alone does not constitute a solution under the ordinary technical meaning of that term, as it lacks any dissolved solute component. Applicant directs attention to IUPAC Gold Book definition of “solution”:
….
While Napetschnig makes a passing reference to an “aqueous solution that may comprise or consist of water” at paragraph [0036], as shown above, Napetschnig only describes water alone. See paragraphs [0038], [0072]. To the extent Napetschnig describes an “aqueous solution” that “consist[s] of water”, Napetschnig is not actually describing a solution at all, but instead employs a loose idiosyncratic lexicography that is limited to its own specification. As evidenced above, and ordinarily skilled artisan would not regard Napetschnig’s disclosure of only water as “a chemical solution, wherein the chemical solution is an organic or inorganic cleaning agent” as recited in claim 1.
The Examiner responds:
The Examiner respectfully disagrees. While Examiner agrees with Applicant’s provided definition of “solution,” Napteschnig does not disclose only water. The Examiner disagrees that Napetschnig mistakenly misidentified water as “aqueous solution.” An ordinary artisan would have understood the “aqueous solution” in paras. [0036]-[0038] to include aqueous solutions outside of just water for the following reasons:
The Examiner disagrees with Applicant’s argument that an “aqueous solution that may comprise or consist of water” at paragraph [0036] only describes water alone. The Examiner would have agreed with Applicant if para. [0036] instead stated “aqueous solution that consists of water.” However, because the aqueous solution may comprise water, the disclosure is allowing the aqueous solution to include substances outside of water.
An ordinary artisan would have considered “aqueous solution” to be a broader term, and that Napetschnig used water as the main example. An ordinary artisan would not have understood Napetschnig to only apply to water and then refer to water as “an aqueous solution” for no other reason. For example, in para. [0038], Napetschnig states that in an embodiment, water is provided as the aqueous solution. If Napetschnig’s “aqueous solution” only meant water, this would be a redundant statement. It would be more likely for an ordinary artisan to assume that Napetschnig meant to refer to water as a main example of an aqueous solution, rather than only disclosing water and renaming it “aqueous solution.”
An ordinary artisan would know that the term “aqueous solution” could refer to a water solvent with one or more solutes. As stated in the previous Office Action, because water is inorganic, the claim limitation “the chemical solution is an organic or inorganic cleaning agent” is met. In the alternative, even though the solutes in the aqueous solution are not explicitly stated to be organic or inorganic, the claim language accounts for both possibilities.
All other arguments have been fully addressed in prior Office Actions or in the rejections set forth below. As a result, the rejection of claims 1-16 is maintained.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3, 10-11, 13, and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Napetschnig et al. (US 20200043876).
Regarding claim 1, Napetschnig teaches a method for manufacturing a semiconductor package assembly ([0008]), the method comprising the steps of i) forming at least one semiconductor package (100, Fig. 8, [0069]-[0072], [0084]) by:
i1) providing a lead frame (110, Fig. 8, [0070]-[0072], [0084], [0086]) having a first frame side (top side) and a second frame side (bottom side) opposite to the first frame side;
i2) adhering at least one semiconductor die structure (102, [0070]-[0072], [0086]) having a first die side (top side) and a second die side (bottom side) opposite to the first die side with the second die side (bottom side) on the first frame side (top side) of the lead frame (110) (see Fig. 8), resulting in a first conductive connection (136, [0086]) between the lead frame and the at least one semiconductor die structure (see Fig. 8, [0086]);
i3) adhering at least one bond element (114, [0086]) on the first die side (top side) of the at least one semiconductor die structure (102) and/or on the first frame side of the lead frame (note that the limitation “on the first frame side of the lead frame” is optional because “and/or” can be interpreted as “or”), resulting in at least one further conductive connection (104, [0086]) between the at least one bond element (114) and the at least one semiconductor die structure (102) ([0070]-[0072]); and
ii) encapsulating the at least one semiconductor package with a molding resin (108, [0087]), thereby forming at least one encapsulated semiconductor package assembly (100, [0069]-[0072], [0086]);
wherein, prior to step ii but after step i3, the method further comprises the step of:
iii) subjecting exposed surfaces (see details 180, 182, and 184 in Fig. 8, [0090]-[0091]) of the first frame side (top side) of the lead frame (110), adhering connections (first conductive connection 136 and one further conductive connection 104) and the at least one bond element (114) of the at least one semiconductor package to a surface roughening treatment using a chemical solution ([0070]-[0072]), wherein the chemical solution is an organic or inorganic cleaning agent. ([0036]-[0038], [0071]-[0072], aqueous solution that may comprise or consist of water, so the chemical solution is an inorganic cleaning agent).
Regarding claim 3, Napetschnig further teaches that the surface roughening treatment of step iii) consists of submerging the at least one semiconductor package in the chemical solution for a period of at least 10 minutes ([0039], “between 10 minutes and 3 hours”).
Regarding claim 10, Napetschnig further teaches that the submerging period is 20-40 minutes ([0093], 30 minutes).
Regarding claim 11, Napetschnig further teaches that the submerging period is about 30 minutes ([0093], 30 minutes).
Regarding claim 13, Napetschnig further teaches that the submerging period is about 30 minutes ([0093], 30 minutes).
Regarding claim 16, Napetschnig further teaches a semiconductor package assembly ([0008]) comprising: a semiconductor package (100, [0084]) composed of a lead frame (110, Fig. 8, [0084]) having a first frame side (top side) and a second frame side (bottom side) opposite to the first frame side;
at least one semiconductor die structure (102, [0086]) having a first die side (top side) and a second die side (bottom side) opposite to the first die side being adhered with the second die side (bottom side) on the first frame side (top side) of the lead frame (110), resulting in a first conductive connection (136, [0086]) between the lead frame and the at least one semiconductor die structure (see Fig. 8, [0086]);
at least one bond element (114, [0086]) adhered on the first die side (top side) of the at least one semiconductor die structure (102) and/or on the first frame side of the lead frame, resulting in at least one further conductive connection (104, [0086]) between the at least one bond element (114) and the at least one semiconductor die structure (102); and
a molding resin (108, [0087]) encapsulating the at least one semiconductor package (100, [0086]);
wherein prior to encapsulating the at least one semiconductor package with the molding resin, the exposed surfaces (see detail 182; [0090]) of the first frame side (top side) of the lead frame (110), the adhering connections (first conductive connection 136 and one further conductive connection 104) and the at least one bond element (114) of the at least one semiconductor package are surface roughened using a chemical solution ([0071]-[0072], aqueous solution) using the method steps of claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 2, 4, 6-7, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Napetschnig et al. (US 20200043876) in view of Ma et al. (CN 113594049 A, citations made hereinafter to the attached English Machine translation).
Regarding claim 2, Napetschnig teaches the limitations of claim 1. Napetschnig does not teach that the organic or inorganic cleaning agent is a photoresist layer stripping agent.
In a similar field of endeavor, Ma teaches that the organic or inorganic cleaning agent ([0019], the “pickling and roughening solution” is a cleaning agent because it has ingredients that are commonly used in or as cleaning agents, such as ethylenediamine (EDA), formic acid, ammonium chloride, and citrate; ethylenediamine (EDA), formic acid, and citrate are organic, and ammonium chloride is inorganic) is a photoresist layer stripping agent ([0019], ethylenediamine (EDA) is commonly used as a main ingredient in a photoresist layer stripping agent), in order to maintain the stability of the etching solution during the roughening process and “to control the etching rate and improve etching efficiency” ([0020]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the chemical solution in the method for manufacturing a semiconductor package assembly of Napetschnig with the photoresist layer stripping agent of Ma, in order to maintain the stability of the etching solution during the roughening process and to control the etching rate and improve etching efficiency ([0020]).
Regarding claim 4, Napetschnig teaches the limitations of claim 1. Napetschnig further teaches that prior to the encapsulating of step ii) ([0073]) but after the surface roughening treatment of step iii) ([0071]-[0072]) the method further comprises the step of: iv) rinsing the semiconductor package with deionized water ([0072], the packaged will be rinsed after the hydrothermal process is over).
Napetschnig does not explicitly teach that prior to the encapsulating of step ii) but after the surface roughening treatment of step iii) the method further comprises the step of: v) drying the semiconductor package.
In a similar field of endeavor, Ma teaches that prior to the encapsulating of step ii) ([0002]) but after the surface roughening treatment of step iii) ([0017], step 12) the method further comprises the step of v) drying the semiconductor package ([0017], step 21), in order to increase the bond strength between the lead frame and the encapsulation resin ([0002]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the in the method for manufacturing a semiconductor package assembly of Napetschnig with the drying of Ma, in order to increase the bond strength between the lead frame and the encapsulation resin ([0002]).
Regarding claim 6, Napetschnig in view of Ma teaches the limitations of claim 2. Ma further teaches that the surface roughening treatment of step iii) consists of submerging the at least one semiconductor package in the chemical solution for a period of at least 10 minutes ([0020], 35 minutes).
Regarding claim 7, Napetschnig in view of Ma teaches the limitations of claim 2. Ma further teaches that prior to the encapsulating of step ii) ([0002]) but after the surface roughening treatment of step iii) ([0017], step 12) the method further comprises the steps of: iv) rinsing the semiconductor package with water ([0017], step 19); and v) drying the semiconductor package ([0017], step 21).
Napetschnig further teaches that the water for rinsing the semiconductor package is deionized ([0072]).
Regarding claim 9, Napetschnig in view of Ma teaches the limitations of claim 2. Ma further teaches that the photoresist layer stripping agent can be an aqueous, a solvent or a semi-aqueous agent ([0019], ethylenediamine is a solvent).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Napetschnig et al. (US 20200043876) in view of Dadvand (US 20230298982).
Regarding claim 5, Napetschnig teaches the limitations of claim 1. Napetschnig does not explicitly teach after the encapsulating of step ii), the steps of: vi) plating the lead frame that is exposed; and vii) singulating the at least one encapsulated semiconductor package assembly.
In a similar field of endeavor, Dadvand teaches, in Fig. 2, after the encapsulating of step ii) (Figs. 2 and 5, [0022], step 206, molding to form 108), the steps of: vi) plating the exposed lead frame (Figs. 2 and 6-7, [0023]-[0024], steps 208 and 210; plating lead frame 110 with plates 111 and 112); and
vii) singulating the at least one encapsulated semiconductor package assembly (Figs. 2 and 8, [0025], step 212),
in order to “mitigate deterioration of the material properties and enhance shelf life prior to soldering to a printed circuit board while improving [board level reliability (BLR)] of an electronic system once the electronic device is soldered to a host printed circuit board ([0002], [0024]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the method for manufacturing a semiconductor package assembly of Napetschnig with the plating and singulating of Dadvand, in order to mitigate deterioration of the material properties and enhance shelf life prior to soldering to a printed circuit board while improving board level reliability of an electronic system once the electronic device is soldered to a host printed circuit board ([0002], [0024]).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Napetschnig et al. (US 20200043876) and Ma et al. (CN 113594049 A, citations made hereinafter to the attached English Machine translation) and further in view of Dadvand (US 20230298982).
Regarding claim 8, Napetschnig in view of Ma teaches the limitations of claim 2. Napetschnig in view of Ma does not explicitly teach after the encapsulating of step ii), the steps of: vi) plating the exposed lead frame; and vii) singulating the at least one encapsulated semiconductor package assembly.
In a similar field of endeavor, Dadvand teaches, in Fig. 2, after the encapsulating of step ii) (Figs. 2 and 5, [0022], step 206, molding to form 108), the steps of: vi) plating the lead frame that is exposed (Figs. 2 and 6-7, [0023]-[0024], steps 208 and 210; plating lead frame 110 with plates 111 and 112); and
vii) singulating the at least one encapsulated semiconductor package assembly (Figs. 2 and 8, [0025], step 212),
in order to “mitigate deterioration of the material properties and enhance shelf life prior to soldering to a printed circuit board while improving [board level reliability (BLR)] of an electronic system once the electronic device is soldered to a host printed circuit board ([0002], [0024]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the method for manufacturing a semiconductor package assembly of Napetschnig in view of Ma with the plating and singulating of Dadvand, in order to mitigate deterioration of the material properties and enhance shelf life prior to soldering to a printed circuit board while improving board level reliability of an electronic system once the electronic device is soldered to a host printed circuit board ([0002], [0024]).
Claims 12 and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Napetschnig et al. (US 20200043876) in view of Quillen et al. (US 20130273479 A9).
Regarding claim 12, Napetschnig teaches the limitations of claim 3. Napetschnig does not explicitly teach that the submerging of step iii) is performed at an elevated temperature of at least 10°C below the flashpoint temperature of the chemical solution used.
In a similar field of endeavor, Quillen teaches that the submerging of step iii) is performed at an elevated temperature of at least 10°C below the flashpoint temperature of the chemical solution used ([0018]), in order to meet “a fundamental safety limit as communicated by industry guidelines” ([0018]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the submerging of Napetschnig with the temperature requirements of Quillen, in order to meet a fundamental safety limit as communicated by industry guidelines ([0018]).
Regarding claim 14, Napetschnig teaches the limitations of claim 11. Napetschnig does not explicitly teach that the submerging of step iii) is performed at an elevated temperature of at least 10°C below the flashpoint temperature of the chemical solution used.
In a similar field of endeavor, Quillen teaches that the submerging of step iii) is performed at an elevated temperature of at least 10°C below the flashpoint temperature of the chemical solution used ([0018]), in order to meet “a fundamental safety limit as communicated by industry guidelines” ([0018]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the submerging of Napetschnig with the temperature requirements of Quillen, in order to meet a fundamental safety limit as communicated by industry guidelines ([0018]).
Regarding claim 15, Napetschnig in view of Quillen teaches the limitations of claim 12. Ma further teaches that prior to the encapsulating of step ii) ([0002]) but after the surface roughening treatment of step iii) ([0017], step 12) the method further comprises the steps of: iv) rinsing the semiconductor package with water ([0017], step 19); and v) drying the semiconductor package ([0017], step 21).
Napetschnig further teaches that the water for rinsing the semiconductor package is deionized ([0072]).
Conclusion
THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIKA HEERA SON whose telephone number is (703)756-4644. The examiner can normally be reached Monday - Friday 12:30-9 PM ET.
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/ERIKA H SON/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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