DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, “a further bond element” in the last two lines of step i3) of Claim 1 (also see [0023] of the Specification) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Specification The disclosure is objected to because of the following informalities: “a further bond element” (Specification [0023]) does not have a reference character. Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b ) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claims 1 -16 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. Claim 1 recites the limitation “the exposed surfaces” in the first line of step iii). There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination with regard to the prior art, this term will be treated as --exposed surfaces--. Claim 1 recites the limitation “the adhering connections” in the first 2 lines of step iii). There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination with regard to the prior art, this term will be treated as –the first conductive connection, the at least one further conductive connection,-- (see Specification [0022]-[0023], [0035]-[0036]). Claims 2-16, because they are dependent on claim 1, inherit the deficienc ies of claim 1. Claim 5 recites the limitation “the exposed lead frame” in line 3 of the claim. There is insufficient antecedent basis for this limitation in the claim. Claim 8 recites the limitation “the exposed lead frame” in line 3 of the claim. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination with regard to the prior art, the term “the exposed lead frame” will be treated as –the lead frame--, which does have antecedent basis from claim 1. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim s 1, 3, 10-11, 13, and 16 are rejected under 35 U.S.C. 102 (a)(1) as being FILLIN "Insert either—clearly anticipated—or—anticipated—with an explanation at the end of the paragraph." \d "[ 3 ]" anticipated b y Napetschnig et al. (US 20200043876) . Regarding claim 1 , Napetschnig teaches a method for manufacturing a semiconductor package assembly ([0008]) , the method comprising the steps of i ) forming at least one semiconductor package (100, Fig. 8 , [0069]-[0072], [0084]) by: i1) providing a lead frame (110 , Fig. 8, [00 70 ]-[0072], [0084], [0086] ) having a first frame side (top side) and a second frame side (bottom side) opposite to the first frame side; i2) adhering at least one semiconductor die structure (102 , [0070]-[0072], [0086] ) having a first die side (top side) and a second die side (bottom side) opposite to the first die side with the second die side (bottom side) on the first frame side (top side) of the lead frame (110) (see Fig. 8) , resulting in a first conductive connection (136 , [0086] ) between the lead frame and the at least one semiconductor die structure (see Fig. 8, [0086]) ; i3) adhering at least one bond element (1 1 4 , [0086] ) on the first die side (top side) of the at least one semiconductor die structure (102) and/or on the first frame side of the lead frame (note that the limitation “on the first frame side of the lead frame” is optional because “and/or” can be interpreted as “or” ) , resulting in at least one further conductive connection (104 , [0086] ) between the at least one bond element (114) and the at least one semiconductor die structure (102) ([00 70 ]-[0072]) (note that the limitation “ and between at least a further bond element and the lead frame ” is optional because it relies on the optional limitation “on the first frame side of the lead frame”) ; and ii) encapsulating the at least one semiconductor package with a molding resin (108 , [0087] ), thereby forming at least one encapsulated semiconductor package assembly (100, [0069]-[0072], [0086]) ; wherein, prior to step ii but after step i3, the method further comprises the step of: iii) subjecting the exposed surfaces (see details 180, 182, and 184 in Fig. 8, [0090]-[0091]) of the first frame side (top side) of the lead frame (110), the adhering connection s ( first conductive connection 136 and one further conductive connection 104) and the at least one bond element (114) of the at least one semiconductor package to a surface roughening treatment using a chemical solution ([0070]-[0072]) , wherein the chemical solution is an organic or inorganic cleaning agent. ( [0036]-[0038], [007 1 ]-[0072], aqueous solution that may comprise or consist of water, so the chemical solution is an inorganic cleaning agent ). Regarding claim 3 , Napetschnig further teaches that the surface roughening treatment of step iii) consists of submerging the at least one semiconductor package in the chemical solution for a period of at least 10 minutes ([0039], “ between 10 minutes and 3 hours ”). Regarding claim 10 , Napetschnig further teaches that the submerging period is 20-40 minutes ([0093], 30 minutes). Regarding claim 11 , Napetschnig further teaches that t he submerging period is about 30 minutes ([0093], 30 minutes). Regarding claim 13 , Napetschnig further teaches that t he submerging period is about 30 minutes ([0093], 30 minutes). Regarding claim 16 , Napetschnig further teaches a semiconductor package assembly ([0008]) comprising: a semiconductor package (100, [0084]) composed of a lead frame (110 , Fig. 8, [0084] ) having a first frame side (top side) and a second frame side (bottom side) opposite to the first frame side; at least one semiconductor die structure (102 , [0086] ) having a first die side (top side) and a second die side (bottom side) opposite to the first die side being adhered with the second die side (bottom side) on the first frame side (top side) of the lead frame (110) , resulting in a first conductive connection (136 , [0086] ) between the lead frame and the at least one semiconductor die structure (see Fig. 8, [0086]) ; at least one bond element (1 1 4 , [0086] ) adhered on the first die side (top side) of the at least one semiconductor die structure (102) and/or on the first frame side of the lead frame, resulting in at least one further conductive connection (104 , [0086] ) between the at least one bond element (114) and the at least one semiconductor die structure (102); and a molding resin (108 , [0087] ) encapsulating the at least one semiconductor package (100, [0086]) ; wherein prior to encapsulating the at least one semiconductor package with the molding resin, the exposed surfaces (see detail 182; [0090]) of the first frame side (top side) of the lead frame (110), the adhering connection s ( first conductive connection 136 and one further conductive connection 104) and the at least one bond element (114) of the at least one semiconductor package are surface roughened using a chemical solution ([0071]-[0072], aqueous solution) using the method steps of claim 1. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 2 , 4, 6-7, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Napetschnig et al. (US 20200043876) in view of Ma et al. (CN 113594049 A, citations made hereinafter to the attached English Machine translation). Regarding claim 2 , Napetschnig teaches the limitations of claim 1. Napetschnig does not teach that the organic or inorganic cleaning agent is a photoresist layer stripping agent. In a similar field of endeavor, Ma teaches that the organic or inorganic cleaning agent ([0019], the “pickling and roughening solution” is a cleaning agent because it has ingredients that are commonly used in or as cleaning agents, such as e thylenediamine (EDA), formic acid, ammonium chloride, and citrate; e thylenediamine (EDA), formic acid, and citrate are organic, and ammonium chloride is inorganic) is a photoresist layer stripping agent ([0019], ethylenediamine (EDA) is commonly used as a main ingredient in a photoresist layer stripping agent), in order to maintain the stability of the etching solution during the roughening process and “to control the etching rate and improve etching efficiency” ([0020]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the chemical solution in the method for manufacturing a semiconductor package assembly of Napetschnig with the photoresist layer stripping agent of Ma, in order to maintain the stability of the etching solution during the roughening process and to control the etching rate and improve etching efficiency ([0020]). Regarding claim 4 , Napetschnig teaches the limitations of claim 1. Napetschnig further teaches that prior to the encapsulating of step ii) ([0073]) but after the surface roughening treatment of step iii) ([0071]-[0072]) the method further comprises the step of: iv) rinsing the semiconductor package with deionized water ([0072] , the packaged will be rinsed after the hydrothermal process is over ) . Napetschnig does not explicitly teach that prior to the encapsulating of step ii) but after the surface roughening treatment of step iii) the method further comprises the step of: v) drying the semiconductor package. In a similar field of endeavor, Ma teaches that prior to the encapsulating of step ii) ([0002]) but after the surface roughening treatment of step iii) ([0017], step 12) the method further comprises the step of v) drying the semiconductor package ([0017], step 21) , in order to increase the bond strength between the lead frame and the encapsulation resin ([0002]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the in the method for manufacturing a semiconductor package assembly of Napetschnig with the drying of Ma, in order to increase the bond strength between the lead frame and the encapsulation resin ([0002]). Regarding claim 6 , Napetschnig in view of Ma teaches the limitations of claim 2. Ma further teaches that the surface roughening treatment of step iii) consists of submerging the at least one semiconductor package in the chemical solution for a period of at least 10 minutes ([0020], 35 minutes) . Regarding claim 7 , Napetschnig in view of Ma teaches the limitations of claim 2. Ma further teaches that prior to the encapsulating of step ii) ([0002]) but after the surface roughening treatment of step iii) ([0017], step 12) the method further comprises the steps of: iv) rinsing the semiconductor package with water ([0017], step 19) ; and v) drying the semiconductor package ([0017], step 21) . Napetschnig further teaches that the water for rinsing the semiconductor package is deionized ([0072]). Regarding claim 9 , Napetschnig in view of Ma teaches the limitations of claim 2. Ma further teaches that the photoresist layer stripping agent can be an aqueous, a solvent or a semi-aqueous agent ([0019], ethylenediamine is a solvent). Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Napetschnig et al. (US 20200043876) in view of Dadvand (US 20230298982) . Regarding claim 5 , Napetschnig teaches the limitations of claim 1. Napetschnig does not explicitly teach after the encapsulating of step ii), the steps of: vi) plating the exposed lead frame; and vii) singulating the at least one encapsulated semiconductor package assembly. In a similar field of endeavor, Dadvand teaches, in Fig. 2, after the encapsulating of step ii) (Fig s . 2 and 5 , [0022], step 206, molding to form 108 ) , the steps of: vi) plating the exposed lead fram e (Figs. 2 and 6-7, [0023]-[0024], steps 208 and 210; plating lead frame 110 with plates 111 and 112 ) ; and vii) singulating the at least one encapsulated semiconductor package assembly (Figs. 2 and 8, [0025] , step 212 ), in order to “ mitigate deterioration of the material properties and enhance shelf life prior to soldering to a printed circuit board while improvin g [board level reliability (BLR)] of an electronic system once the electronic device is soldered to a host printed circuit board ([0002], [0024]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the method for manufacturing a semiconductor package assembly of Napetschnig with the plating and singulating of Dadvand , in order to mitigate deterioration of the material properties and enhance shelf life prior to soldering to a printed circuit board while improvin g board level reliability of an electronic system once the electronic device is soldered to a host printed circuit board ([0002], [0024]). Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Napetschnig et al. (US 20200043876) and Ma et al. (CN 113594049 A, citations made hereinafter to the attached English Machine translation) and further in view of Dadvand (US 20230298982) . Regarding claim 8 , Napetschnig in view of Ma teaches the limitations of claim 2. Napetschnig in view of Ma does not explicitly teach after the encapsulating of step ii), the steps of: vi) plating the exposed lead frame; and vii) singulating the at least one encapsulated semiconductor package assembly. In a similar field of endeavor, Dadvand teaches, in Fig. 2, after the encapsulating of step ii) (Figs. 2 and 5, [0022], step 206, molding to form 108) , the steps of: vi) plating the exposed lead fram e (Figs. 2 and 6-7, [0023]-[0024], steps 208 and 210; plating lead frame 110 with plates 111 and 112) ; and vii) singulating the at least one encapsulated semiconductor package assembly (Figs. 2 and 8, [0025], step 212), in order to “ mitigate deterioration of the material properties and enhance shelf life prior to soldering to a printed circuit board while improvin g [board level reliability (BLR)] of an electronic system once the electronic device is soldered to a host printed circuit board ([0002], [0024]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the method for manufacturing a semiconductor package assembly of Napetschnig in view of Ma with the plating and singulating of Dadvand , in order to mitigate deterioration of the material properties and enhance shelf life prior to soldering to a printed circuit board while improvin g board level reliability of an electronic system once the electronic device is soldered to a host printed circuit board ([0002], [0024]). Claims 12 and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Napetschnig et al. (US 20200043876) in view of Quillen et al. ( US 20130273479 A9 ). Regarding claim 12 , Napetschnig teaches the limitations of claim 3. Napetschnig does not explicitly teach that the submerging of step iii) is performed at an elevated temperature of at least 10°C below the flashpoint temperature of the chemical solution used. In a similar field of endeavor, Quillen teaches that the submerging of step iii) is performed at an elevated temperature of at least 10°C below the flashpoint temperature of the chemical solution used ([0018]), in order to meet “a fundamental safety limit as commu nicated by industry guidelines” ([0018]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the submerging of Napetschnig with the temperature requirements of Quillen, in order to meet a fundamental safety limit as communicated by industry guidelines ([0018]). Regarding claim 14 , Napetschnig teaches the limitations of claim 11. Napetschnig does not explicitly teach that the submerging of step iii) is performed at an elevated temperature of at least 10°C below the flashpoint temperature of the chemical solution used. In a similar field of endeavor, Quillen teaches that the submerging of step iii) is performed at an elevated temperature of at least 10°C below the flashpoint temperature of the chemical solution used ([0018]), in order to meet “a fundamental safety limit as communicated by industry guidelines” ([0018]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the submerging of Napetschnig with the temperature requirements of Quillen, in order to meet a fundamental safety limit as communicated by industry guidelines ([0018]). Regarding claim 15 , Napetschnig in view of Quillen teaches the limitations of claim 12. Ma further teaches that prior to the encapsulating of step ii) ([0002]) but after the surface roughening treatment of step iii) ([0017], step 12) the method further comprises the steps of: iv) rinsing the semiconductor package with water ([0017], step 19) ; and v) drying the semiconductor package ([0017], step 21) . Napetschnig further teaches that the water for rinsing the semiconductor package is deionized ([0072]). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT ERIKA HEERA SON whose telephone number is FILLIN "Phone number" \* MERGEFORMAT 703-756-4644 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Monday - Friday 12:30-9:30 PM ET . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Yara Green can be reached on FILLIN "SPE Phone?" \* MERGEFORMAT 571-270-3035 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ERIKA H SON/ Examiner, Art Unit 2893 /YARA B GREEN/ Supervisor Patent Examiner, Art Unit 2893