DETAILED ACTION
This action is responsive to communications: RCE filed on 06/17/2026.
Applicant amended claims 1, 3, 6, 8, 10, 15, and 18; cancelled none; added no new claims. Claims 1-20 are pending. Claims 1, 8, and 15 are independent.
Continued Examination under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/17/2026 has been entered.
Examiner Notes
A) Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. B) MPEP 2163 guidelines teach that drawing and specification must be examined to assess whether an originally-filed claim has adequate support in the written disclosure and/or the drawings. Possession may be shown by a clear depiction of the invention in detailed drawings. C) Per MPEP 2173.04 “If the claim is too broad because it reads on the prior art, a rejection under either 35 U.S.C. 102 or 103 would be appropriate”. D) Examiner cites particular paragraphs or columns and lines in the references as applied to Applicant's claims for the convenience of the Applicant. Other passages and figures may apply as well. Per MPEP 2141.02 VI prior art must be considered in its entirety. E) Per MPEP 2112 and 2112 V, express, implicit, and inherent disclosures of a prior art reference may be relied upon in the rejection of claims under 35 U.S.C. 102 or 103.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
No Priority
3. See ADS, no priority claimed.
Information Disclosure Statement
4. Acknowledgment is made of applicant's Information Disclosure Statement (IDS) filed on 06/17/2026. All IDS has been considered.
Applicant is requested to check other claim informality, language issues (e.g., antecedent issues, redundant limitation issues, grammar issues) for all claims to expedite prosecution since informality scrutiny in this office action is not exhaustive and applicant’s co-operation is sought in this regard.
Claim Rejections - 35 USC § 112
5. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. —The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
6. Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1, line 4 recites: “…optimizing endurance, power, or performance…” (1)
Claim 1, line 13 recites: “…optimize memory settings…” (2)
Claim 6, line 16 recites: “…optimize parameters…” (3)
Claim 8, line 4 recites: “…optimizing endurance, power, or performance…” (4)
Claim10, lines 3-6 recite: “…optimization…”, “…optimized…” (5)
Highlighted language (1)-(5) above conveys a language with a relative term and thus vague and indefinite. See MPEP 2173.05 (a) II, 2173.05 (b). Relative terms are considered indefinite if they don't clearly define the scope of the claimed invention. Relative terms lead to rejection for indefiniteness under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph if the claims fail to define the metes and bounds of the invention with sufficient clarity. Claim must be clear enough for a skilled artisan to understand its boundaries and scope. This includes the recitation "optimizing", “optimize”, “optimized” and all these recitations are indefinite. These recitations are present without providing an objective standard for determining its meaning. Claim's scope is unclear to a skilled artisan without needing to make subjective judgments to determine its meaning. Even if the specification uses the same term of degree as in the claim, a rejection is proper if the scope of the term is not understood when read in light of the specification. While, as a general proposition, broadening modifiers are standard tools in claim drafting in order to avoid reliance on the doctrine of equivalents in infringement actions, when the scope of the claim is unclear a rejection under 35 U.S.C. 112(b), or pre-AIA 35 U.S.C. 112, second paragraph, is proper. See In re Wiggins, 488 F. 2d 538, 541, 179 USPQ 421, 423 (CCPA 1973).
To avoid such indefiniteness when using "optimizing", “optimize”, “optimized” recitations, applicant can provide an objective standard, e.g., define these with terms that can be objectively measured or determined by a skilled artisan. This can be done by: providing a range or numerical value or, by relating the term to a quantifiable parameter, for example, describing sufficiently achieved power reduction that satisfies the optimization.
Similarly,
Claim 1, line 4 recites: “…improve endurance…” (6)
Claim 1, line 15 recites: “…improve parameters…” (7)
Claim 8, line 11 recites: “…improve parameters…” (8)
Claim 8, line 14 recites: “…improve endurance…” (9)
Claim 15, line 9 recites: “…improve endurance…” (10)
Claim 15, line 13 recites: “…improve endurance…” (11)
Highlighted language (6)-(11) above “improve” conveys a language with a relative term and thus vague and indefinite.
For purposes of compact prosecution, the clause (s) are broadly interpreted as adjusting or maintaining associated parameters for reducing any phenomena that impacts memory device negatively. Limitation associated with optimize or, improve are also not given patentable weight.
All dependent claims inclusive of claims 1-20 are rejected under this category.
Claim Rejections - 35 USC § 103
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
8. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
9. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
10. Claims 1-2, 4-5, 7-17, and 19-20 is/are rejected under 35 U.S.C. 103 as being obvious over Hall et al. (US 2022/0013169 A1), in view of CHANDRAMANI et al. (US 2022/0413756 A1) and BRENNAN (US 2020/0174697 A1).
Regarding independent claim 1, Hall teaches a memory subsystem (Fig. 6: 600 “memory subsystem” with smart compute memory and adaptive memory management and control. See para [0079]) comprising:
a resistive memory array (Fig. 6: 680, para [0080]: ReRAM, RRAM, FeRAM);
an adaptive aggregation memory buffer (para [0043]: “buffer”) for aggregating memory requests having configurable settings (para [0043]: 25% size threshold, 50% size threshold, 75% size threshold) for optimizing (optimize suggests a relative term, is too broad and associated limitations are not given patentable weight) endurance, power, or performance of the memory subsystem (para [0041]);
wherein the adaptive aggregation memory buffer has selective power down modes for unused buffer sections to reduce power consumption and improve endurance (see e.g. para [0043]-para [0044], para [0065]: FSM tracks threshold amount full in buffer and send signal to power management circuitry to change power state);
an endurance management and control logic (EMCL) (Fig. 6: 672, 670, 682 combined. Para [0081]: AMMC and associated circuitry manages and controls “endurance”) coupled to the adaptive aggregation memory buffer (see Fig. 6);
an integrated processor (Fig. 1: 160) coupled to the EMCL (Fig. 6: 672, 670, 682 combined).
Hall is silent with respect to the details of functions of adaptive aggregation memory buffer and functions of endurance management control logic and functions of EMCL buffer.
CHANDRAMANI teaches adaptive aggregation memory buffer (Fig. 17: 1730 and 1742) for aggregating memory requests having configurable settings (setting for write command aggregation) for optimizing (optimize suggests a relative term, is too broad and associated limitations are not given patentable weight) endurance, power, or performance of the memory subsystem (see e.g. para [0135]-para [0138]).
BRENNAN teaches -
at least one of the integrated processor (para [0016]: CPU and processing circuitry) and the EMCL (Fig. 2: 210) is configured to determine whether two or more memory requests including two or more write or read operations to a particular localized memory region (Fig. 7: 710, 715) during a time window can be aggregated into a single aggregate memory request for a write or read operation (Fig. 7 in context of para [0068]-para [0074]. See also abstract) and to optimize memory settings (optimize suggests a relative term, is too broad and associated limitations are not given patentable weight), and
to cause the single aggregate memory request and memory settings to be sent to the resistive memory array (“…operation combiner compares the first read addresses and the first write address to one or more second read addresses and a second write address of a second command stored in a buffer. The operation combiner selectively combines the first and second commands to form an aggregate command based on the comparison…”. See Fig. 7 in context of para [0068]-para [0074]. See also abstract, para [0011], para [0030]) to improve parameters including memory performance and memory endurance by reducing a number of write or read cycles (para [0021], para [0074]).
Hall, CHANDRAMANI, and BRENNAN are in the same field of endeavor of read/ write operation improvement of resistive memory and system; and they are in analogous art. An ordinary skill in the art would understand the use of CHANDRAMANI’s and BRENNAN’s circuitry components into the apparatus of Hall.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine CHANDRAMANI and BRENNAN’s circuitry components and functionality into the memory subsystem of Hall such that claimed apparatus can be implemented in order to have benefits e.g., “…improves…unaligned write performance and increases the die utilization…” (CHANDRAMANI para [0044], para [0139]) and improve command execution speed (BRENNAN Abstract)
Regarding claim 2, Hall, CHANDRAMANI, and BRENNAN teach the memory subsystem of claim 1. CHANDRAMANI teaches wherein the EMCL (Fig. 10: 1034) is configured to receive input from the integrated processor (Fig. 10: controller) and to determine a configurable memory setting (Fig. 17: command aggregation function) of the adaptive aggregation memory buffer (Fig. 17: 1730, 1742) based on a memory request type, a usage pattern of an application, or an operating condition (para [0042], para [0161]: e.g., unaligned write commands. See also Fig. 24: 2404-2404).
Regarding claim 4, Hall, CHANDRAMANI, and BRENNAN teach the memory subsystem of claim 1. Hall teaches wherein the adaptive aggregation memory buffer, EMCL, and integrated processor are directly adjacent to the resistive memory array (See Hall Fig. 6 and Fig. 1 components and arrangement in context SOC teachings of para [0038]).
Regarding claim 5, Hall, CHANDRAMANI, and BRENNAN teach the memory subsystem of claim 1. Hall teaches wherein the memory subsystem comprises a system on chip (SoC) compute-in-memory (Hall para [0036], para [0038], para [0081] in context of Fig. 6 memory subsystem).
Regarding claim 7, Hall, CHANDRAMANI, and BRENNAN teach the memory subsystem of claim 1. Hall wherein the resistive memory array comprises non-volatile random-access memory (RAM) including one or more of magnetic RAM (MRAM), resistor random access memory, phase change RAM (PCRAM), voltage-controlled magnetic anisotropy (VCMA)-MRAM, or carbon nanotube memory cells (Hall para [0080]. See also CHANDRAMANI para [0074]).
Regarding independent claim 8, Hall teaches a memory subsystem (Fig. 6: 600 “memory subsystem” with smart compute memory and adaptive memory management and control, para [0079]) comprising:
an endurance management and control logic (EMCL) (Fig. 6: 672, 670, 682 combined. See Para [0081]: AMMC and associated circuitry manages and controls “endurance”);
a ferro-electric RAM (FeRAM) memory array or embedded flash memory (Fig. 6: 680, para [0080]: ReRAM, RRAM, FeRAM) coupled to the adaptive aggregation memory buffer (supported by Fig. 6 670 circuitry and buffer),
an adaptive aggregation memory buffer ((Fig. 6: 672 AMMC) coupled to apparatus;
the adaptive aggregation memory buffer has selective power down modes for unused buffer sections to reduce power and endurance (para [0077]: low power modes; see also para [0038]. see e.g. para [0043]-para [0044], para [0065]: FSM tracks threshold amount full in buffer and send signal to power management circuitry to change power state).
Hall is silent with respect to the details of functions of adaptive aggregation memory buffer and functions of endurance management control logic, and functions of EMCL buffer.
CHANDRAMANI teaches a memory system of (Fig. 10: 1000) with resistive memory array (para [0074]) with circuitry components: an adaptive aggregation memory buffer (Fig. 17: 1730 and 1742) coupled to the EMCL (para [0134], Fig. 10: 1034 firmware and associated circuitry. Para [0044], para [0107])
CHANDRAMANI teaches adaptive aggregation memory buffer (Fig. 17: 1730 and 1742) for aggregating memory requests having configurable settings (setting for write command aggregation) for optimizing (optimize suggests a relative term, is too broad and associated limitations are not given patentable weight) endurance, power, or performance of the memory subsystem (see e.g. para [0134]-para [0138]).
BRENNAN teaches -
the EMCL (Fig. 2: 210) is configured to determine (Fig. 7: 710, 715) whether two or more memory requests to one or more memory regions during a time window (e.g. read-write cycle) can be aggregated into an aggregate memory request (Fig. 7 in context of para [0068]-para [0074]. See also abstract), and
to cause the aggregate memory request to be sent to the FeRAM memory array or the embedded flash memory (“…operation combiner compares the first read addresses and the first write address to one or more second read addresses and a second write address of a second command stored in a buffer. The operation combiner selectively combines the first and second commands to form an aggregate command based on the comparison…”. See Fig. 7 in context of para [0068]-para [0074]. See also abstract, para [0011], para [0030]) to improve parameters including memory performance and memory endurance by reducing a number of write or read cycles (See Fig. 7 in context of para [0068]-para [0074]. See also abstract, para [0011], para [0030]).
Hall, CHANDRAMANI, and BRENNAN are in the same field of endeavor of read/ write operation improvement of resistive memory and system; and they are in analogous art. An ordinary skill in the art would understand the use of CHANDRAMANI’s and BRENNAN’s circuitry components into the apparatus of Hall.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine CHANDRAMANI and BRENNAN’s circuitry components and functionality into the memory subsystem of Hall such that claimed apparatus can be implemented in order to have benefits e.g., “…improves…unaligned write performance and increases the die utilization…” (CHANDRAMANI para [0044], para [0139]) and improve command execution speed (BRENNAN Abstract)
Regarding claim 9, Hall, CHANDRAMANI, and BRENNAN teach the memory subsystem of claim 8, wherein the EMCL is configured to determine a configurable setting of the adaptive aggregation memory buffer based on a memory request type, a usage pattern of an application, or an operating condition. (This claim is drafted as in subsystem format, substantially identical to the limitations recited in claim 2, and is therefore rejected for the same reasons as claim 2. See Claim 2 rejection analysis)
Regarding claim 10, Hall, CHANDRAMANI, and BRENNAN teach the memory subsystem of claim 9. Hall teaches wherein the adaptive aggregation memory buffer has variable clock rates being adjusted for power versus performance optimization and configurable settings including a first mode optimized for writing large amount of data, a second mode optimized for writing small amount of data, a third mode optimized for high-speed writing, and a fourth mode optimized for low-speed writing (para [0041], para [0074], para [0076]).
Regarding claim 11, Hall, CHANDRAMANI, and BRENNAN teach the memory subsystem of claim 8, wherein the adaptive aggregation memory buffer and EMCL are integrated with the FeRAM memory array or embedded flash memory. (This claim is drafted as in subsystem format, substantially identical to the limitations recited in claim 3, and is therefore rejected for the same reasons as claim 3. See Claim 3 rejection analysis)
Regarding claim 12, Hall, CHANDRAMANI, and BRENNAN teach the memory subsystem of claim 9, wherein the adaptive aggregation memory buffer and EMCL are directly adjacent to the FeRAM memory array or embedded flash memory. (This claim is drafted as in subsystem format, substantially identical to the limitations recited in claim 4, and is therefore rejected for the same reasons as claim 4. See Claim 4 rejection analysis)
Regarding claim 13, Hall, CHANDRAMANI, and BRENNAN teach the memory subsystem of claim 8, wherein the memory subsystem comprises a system on chip (SoC) compute-in-memory. (This claim is drafted as in subsystem format, substantially identical to the limitations recited in claim 5, and is therefore rejected for the same reasons as claim 5. See Claim 5 rejection analysis)
Regarding claim 14, Hall, CHANDRAMANI, and BRENNAN teach the memory subsystem of claim 8, wherein the EMCL is configured to cause a pre-read of cells of the FeRAM memory array or embedded flash memory that will be written by the aggregate memory request and to selectively write to the cells that will have a change in logic state based on the aggregate memory request without writing to cells having no change in logic state. (This claim is drafted as in subsystem format, substantially identical to the limitations recited in claim 6, and is therefore rejected for the same reasons as claim 6. See Claim 6 rejection analysis)
Regarding independent claim 15, Hall, CHANDRAMANI, and BRENNAN teach a computer-implemented method for operating a memory subsystem, the computer-implementing method comprises (computer-implemented method is conventional item used conventionally to store and implement computer programs to perform generic computer functions that are well-understood, routine, and conventional activities previously known to the pertinent industry, and several court cases demonstrate that the mere recitation of a computer-implemented method cannot transform a patent-ineligible abstract idea into a patent-eligible invention):
receiving memory requests, with an endurance management and control logic (EMCL), for a non-volatile memory array of the memory subsystem including a non-volatile resistive memory, embedded flash memory, or Ferroelectric RAM (FeRAM);
storing the two or more memory requests including two or more write or read operations in an adaptive aggregation memory buffer of the memory subsystem, wherein the adaptive aggregation memory buffer has selective power down modes for unused buffer sections to reduce power consumption and improve endurance;
determining whether the two or more memory requests including two or more write or read operations to one or more memory regions during a time window can be aggregated into a single aggregated memory request for a write or read operation to improve endurance by reducing a number of write or read cycles, performance, and/or power consumption before sending the single aggregated memory request to the non-volatile memory array.
(This claim is drafted as in subsystem format, substantially identical to the limitations recited in claim 1 and claim 8, and is therefore rejected for the same reasons as claim 1 and claim 8. See Claim 1, 8 rejection analysis)
Regarding claim 16, Hall, CHANDRAMANI, and BRENNAN teach the computer-implemented method of claim 15, further comprising: aggregating with the EMCL the two or more memory requests including write operations aggregated based on time and memory space localization for the single aggregated memory request having the write operation or read operations aggregated based on time and memory space localization into the single aggregate memory request or a reduced number of memory requests.
(Hall and CHANDRAMANI teach the computer-implemented method of claim 15. CHANDRAMANI teaches further comprising: aggregating with the EMCL memory requests (Fig. 17-Fig. 19: aggregated write commands) including write operations aggregated based on time and memory space localization (See Fig. 17-Fig. 19) or read operations aggregated based on time and memory space localization into the aggregate memory request or a reduced number of memory requests (see para [0007], para [0146] in context of Fig. 17-Fig. 19).
Regarding claim 17, Hall, CHANDRAMANI, and BRENNAN teach the computer-implemented method of claim 15. CHANDRAMANI teaches wherein write operations are aggregated into a single write operation (para [0135], Fig. 17) for a temporal and spatial locality within a range of memory addresses of the non-volatile memory array (see para [0007], para [0146], para [0143] in context of Fig. 17-Fig. 19).
Regarding claim 19, Hall, CHANDRAMANI, and BRENNAN teach the computer-implemented method of claim 18. CHANDRAMANI teaches further comprising: processing the aggregate memory request selectively for each cell of the non-volatile memory array that will have a change in logic state. (Para [0141] and para [0042] in context of Fig. 24: 2420)
Regarding claim 20, Hall, CHANDRAMANI, and BRENNAN teach the computer-implemented method of claim 19. CHANDRAMANI teaches wherein the change in logic state (writing process) comprises a change in resistance state when the non-volatile memory includes a resistive memory array. (Fig. 1, para [0061])
Response to Arguments
Applicant’s arguments with respect to independent claim(s) 1, 8, 15 have been considered but are partly moot because the new ground of rejection added using existing references. New analysis does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
1. Applicant argues that obviousness rejection of independent claims under 35 U.S.C. 103 over Hall et al. (US 2022/0013169 A1), and CHANDRAMANI et al. (US 2022/0413756 A1) is not proper because Hall fails to teach “…an adaptive aggregation memory buffer for aggregating memory requests having configurable settings for optimizing endurance, power, or performance of the memory subsystem, wherein the adaptive aggregation memory buffer has selective power down modes for unused buffer sections to reduce power consumption and improve endurance…” (Remarks page 10)
Applicant’s argument is not persuasive because applicant has not provided sufficient reasons and has not considered prior art in its entirety. See new formulated rejection. Applicant’s argument is also not persuasive because Hall teaches the limitation in combination with CHANDRAMANI. See rejection analysis. Hall para [0041]-para [0044] reads on the limitation which is then combined with CHANDRAMANI’s para [0135]-para [0138] and Fig. 17 teachings.
2. Applicant argues that obviousness rejection of independent claims under 35 U.S.C. 103 over Hall et al. (US 2022/0013169 A1), and CHANDRAMANI et al. (US 2022/0413756 A1) is not proper because Hall fails to teach “…wherein at least one of the integrated processor and the EMCL is configured to determine whether two or more memory requests including two or more write or read operations to a particular localized memory region during a time window can be aggregated into a single aggregate memory request for a write or read operation and to optimize memory settings, and to cause the single aggregate memory request and memory settings to be sent to the resistive memory array to optimize improve parameters including memory performance and memory endurance by reducing a number of write or read cycles" of amended claim 1.” (Remarks page 10)
Applicant’s argument is persuasive because BRENNAN’s teachings are relied upon for the rejections of these limitations.
3. Applicant argues that obviousness rejection of independent claims under 35 U.S.C. 103 over Hall et al. (US 2022/0013169 A1), and CHANDRAMANI et al. (US 2022/0413756 A1) is not proper because Chandramani fails to disclose the limitations "an adaptive aggregation memory buffer for aggregating memory requests having configurable settings for optimizing endurance, power, or performance of the memory subsystem, wherein the adaptive aggregation memory buffer has selective power down modes for unused buffer sections to reduce power consumption and improve endurance;" (Remarks page 10)
Applicant’s argument is persuasive because Hall teaches the limitation in combination with CHANDRAMANI. See rejection analysis. Hall para [0041]-para [0044] reads on the limitation which is then combined with CHANDRAMANI’s para [0135]-para [0138] and Fig. 17 teachings.
4. Applicant argues that obviousness rejection of independent claims under 35 U.S.C. 103 over Hall et al. (US 2022/0013169 A1), and CHANDRAMANI et al. (US 2022/0413756 A1) is not proper because Chandramani fails to disclose “…wherein at least one of the integrated processor and the EMCL is configured to determine whether two or more memory requests including two or more write or read operations to a particular localized memory region during a time window can be aggregated into a single aggregate memory request for a write or read operation and to optimize memory settings, and to cause the single aggregate memory request and memory settings to be sent to the resistive memory array to optimize improve parameters including memory performance and memory endurance by reducing a number of write or read cycles" of amended claim 1” (Remarks page 10-11)
Applicant’s argument is persuasive because BRENNAN’s teachings are relied upon for the rejections of these limitations.
5. Applicant argues that obviousness rejection of independent claims under 35 U.S.C. 103 over Hall et al. (US 2022/0013169 A1), and CHANDRAMANI et al. (US 2022/0413756 A1) is not proper because the rejection impermissibly equates address-equality command merging with the claim's higher- level, endurance-driven aggregation and settings optimization. (Remarks page 11)
In response to applicant's argument that the references fail to show certain features of applicant’s invention, it is noted that the features upon which applicant relies (i.e., claim’s higher- level, endurance-driven aggregation and settings optimization) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
6. Applicant argues that obviousness rejection of independent claims under 35 U.S.C. 103 over Hall et al. (US 2022/0013169 A1), and CHANDRAMANI et al. (US 2022/0413756 A1) is not proper because Hall's AMMC/processor subsystem cannot be modified with Chandramani's unaligned-write aggregation and Brennan's operation-combiner to yield the claimed "localized memory region during a time window" aggregation into a "single aggregate memory request" with "memory settings" sent to a resistive/FeRAM/embedded-flash array. Further Brennan's "aggregate command" is a decoder/decompression pipeline micro-optimization tied to cache-line address matching and mask merging, not an endurance-management EMCL that aggregates memory requests and co-sends configurable memory settings to optimize endurance/power/performance for a non-volatile memory array. (Remarks page 11)
In response to applicant's arguments above, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981). Also, mentioned prior arts are NOT non-analogous art: it has been held that a prior art reference must either be in the field of applicant’s endeavor or, if not, then be reasonably pertinent to the particular problem with which the applicant was concerned, in order to be relied upon as a basis for rejection of the claimed invention. See In re Oetiker, 977 F.2d 1443, 24 USPQ2d 1443 (Fed. Cir. 1992).
7. Applicant argues that obviousness rejection of independent claims under 35 U.S.C. 103 over Hall et al. (US 2022/0013169 A1), and CHANDRAMANI et al. (US 2022/0413756 A1) is not proper because Brennan is NOT analogous art to Applicant's endurance/power/performance "EMCL + adaptive aggregation memory buffer with configurable settings" architecture, nor provided an articulated rationale that a person of ordinary skill in the art (POSIT A) would transplant Brennan's decompression-specific command-collapsing into Hall's endurance-management subsystem and further combine it with Chandramani's SSD unaligned-write padding/aggregation to arrive at the claimed invention without hindsight. (Remarks page 11)
In response to applicant's argument that the references fail to show certain features of applicant’s invention, it is noted that the features upon which applicant relies (i.e., claim’s higher- level, endurance-driven aggregation and settings optimization) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Also note, in response to applicant’s argument that the examiner’s conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant’s disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971).
8. Applicant argues that obviousness rejection of independent claims under 35 U.S.C. 103 over Hall et al. (US 2022/0013169 A1), and CHANDRAMANI et al. (US 2022/0413756 A1) is not proper because even if Hall, Chandramani, and Brennan were combined, such a combination would lack the limitations "an adaptive aggregation memory buffer for aggregating memory requests having configurable settings for optimizing endurance, power, or performance of the memory subsystem, wherein the adaptive aggregation memory buffer has selective power down modes for unused buffer sections to reduce power consumption and improve endurance; an endurance management and control logic (EMCL) coupled to the adaptive aggregation memory buffer; and an integrated processor coupled to the EMCL, wherein at least one of the integrated processor and the EMCL is configured to determine whether two or more memory requests including two or more write or read operations to a particular localized memory region during a time window can be aggregated into a single aggregate memory request for a write or read operation and to optimize memory settings, and to cause the single aggregate memory request and memory settings to be sent to the resistive memory array to optimize improve parameters including memory performance and memory endurance by reducing a number of write or read cycles" of amended claim 1.” (page 12)
Applicant’s argument is not persuasive because applicant has not provided sufficient reasons and has not considered prior art in its entirety. See new formulated rejection. One cannot show non-obviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Prior Art Not Relied Upon
The prior art made of record and not relied upon (MPEP § 707.05) is considered pertinent to applicant's disclosure: Benistry (US 20180018101 A1): Fig. 1-Fig. 6B applicable for all claims. Shin et al (US 2020/0151054): Fig. 1-Fig. 16 disclosure applicable for all claims. Prior art teaches a memory system including a memory module including a plurality of memory chips mounted on a module board; and a memory controller configured to control a memory operation for the plurality of memory chips of the memory module, set at least one memory chip from among the plurality of memory chips as an indicator chip, and, when it is determined based on a result of an error detection for a codeword read from the memory module that an error has occurred in the indicator chip, output reliability deterioration information indicating that reliability of the memory module is deteriorated. It is suggested that applicant consider all prior arts made of record.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUSHFIQUE SIDDIQUE whose telephone number is (571)270-0424. The examiner can normally be reached 7:00 am-4:00 pm.
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/MUSHFIQUE SIDDIQUE/Primary Examiner, Art Unit 2825
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