DETAILED ACTION
This Final action is responsive to communications: 09/19/2025.
Applicant amended claims 1, 8, 10, 15 and 16; cancelled none; added no new claims. Claims 1-20 are pending. Claims 1, 8, and 15 are independent.
Examiner Notes
A) Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. B) MPEP 2163 guidelines teach that drawing and specification must be examined to assess whether an originally-filed claim has adequate support in the written disclosure and/or the drawings. Possession may be shown by a clear depiction of the invention in detailed drawings. C) Per MPEP 2173.04 “If the claim is too broad because it reads on the prior art, a rejection under either 35 U.S.C. 102 or 103 would be appropriate”. D) Examiner cites particular paragraphs or columns and lines in the references as applied to Applicant's claims for the convenience of the Applicant. Other passages and figures may apply as well. Per MPEP 2141.02 VI prior art must be considered in its entirety. E) Per MPEP 2112 and 2112 V, express, implicit, and inherent disclosures of a prior art reference may be relied upon in the rejection of claims under 35 U.S.C. 102 or 103.
Notice of Pre-AIA or AIA Status
3. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
No Priority
4. See ADS, no priority claimed.
Information Disclosure Statement
5. Acknowledgment is made of applicant's Information Disclosure Statement (IDS) filed on 09/19/2025. All IDS has been considered.
Applicant is requested to check other claim informality, language issues (e.g., antecedent issues, redundant limitation issues, grammar issues) for all claims to expedite prosecution since informality scrutiny in this office action is not exhaustive and applicant’s co-operation is sought in this regard.
Claim Rejections - 35 USC § 103
6. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
7. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
8. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
9. Claims 1-20 is/are rejected under 35 U.S.C. 103 as being obvious over Hall et al. (US 2022/0013169 A1), in view of CHANDRAMANI et al. (US 2022/0413756 A1) and BRENNAN (US 2020/0174697 A1).
Regarding independent claim 1, Hall teaches a memory subsystem (Fig. 6: 600 “memory subsystem” with smart compute memory and adaptive memory management and control. See para [0079]) comprising:
a resistive memory array (Fig. 6: 680, para [0080]: ReRAM, RRAM, FeRAM);
an endurance management and control logic (EMCL) (Fig. 6: 672, 670, 682 combined. Para [0081]: AMMC and associated circuitry manages and controls “endurance”) coupled to the adaptive aggregation memory buffer (supported by Fig. 6 670 circuitry and buffer);
an integrated processor (Fig. 6: 660 integrated processor) coupled to the EMCL (Fig. 6: 672, 670, 682).
Hall is silent with respect to the details of functions of adaptive aggregation memory buffer and functions of endurance management control logic and functions of EMCL buffer.
CHANDRAMANI teaches a memory system of (Fig. 10: 1000) with resistive memory array (para [0074]) with circuitry components:
an adaptive aggregation memory buffer (Fig. 17: 1730 and 1742) having configurable settings (setting for write command aggregation) for optimizing (optimize suggests a relative term, is too broad and associated limitations are not given patentable weight) endurance, power, or performance of the memory subsystem (see e.g. para [0135]-para [0138]);
an endurance management and control logic (EMCL) (para [0134], Fig. 10: 1034 firmware and associated circuitry. Para [0044], para [0107]) coupled to the adaptive aggregation memory buffer (see Fig. 17: 1730 and 1742); and
an integrated processor (Fig. 10 controller) coupled to the EMCL (para [0134], Fig. 10: 1034 firmware and associated circuitry).
BRENNAN teaches -
at least one of the integrated processor and the EMCL (Fig. 2: 210) is configured to determine whether two or more memory requests including two or more write or read operations to a particular localized memory region (Fig. 7: 710, 715) during a time window can be aggregated into a single aggregate memory request for a write or read operation (Fig. 7 in context of para [0068]-para [0074]. See also abstract) and to optimize memory settings (optimize suggests a relative term, is too broad and associated limitations are not given patentable weight), and
to cause the single aggregate memory request and memory settings to be sent to the resistive memory array (“…operation combiner compares the first read addresses and the first write address to one or more second read addresses and a second write address of a second command stored in a buffer. The operation combiner selectively combines the first and second commands to form an aggregate command based on the comparison…”. See Fig. 7 in context of para [0068]-para [0074]. See also abstract, para [0011], para [0030]) to optimize parameters including memory performance and memory endurance (optimize suggests a relative term, is too broad and associated limitations are not given patentable weight).
Hall, CHANDRAMANI, and BRENNAN are in the same field of endeavor of read/ write operation improvement of resistive memory and system; and they are in analogous art. An ordinary skill in the art would understand the use of CHANDRAMANI’s and BRENNAN’s circuitry components into the apparatus of Hall.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine CHANDRAMANI and BRENNAN’s circuitry components and functionality into the memory subsystem of Hall such that claimed apparatus can be implemented in order to have benefits e.g., “…improves…unaligned write performance and increases the die utilization…” (CHANDRAMANI para [0044], para [0139]) and improve command execution speed (BRENNAN Abstract)
Regarding claim 2, Hall, CHANDRAMANI, and BRENNAN teach the memory subsystem of claim 1. CHANDRAMANI teaches wherein the EMCL (Fig. 10: 1034) is configured to receive input from the integrated processor (Fig. 10: controller) and to determine a configurable memory setting (Fig. 17: command aggregation function) of the adaptive aggregation memory buffer (Fig. 17: 1730, 1742) based on a memory request type, a usage pattern of an application, or an operating condition (para [0042], para [0161]: e.g., unaligned write commands. See also Fig. 24: 2404-2404).
Regarding claim 3, Hall, CHANDRAMANI, and BRENNAN teach the memory subsystem of claim 1. Hall teaches wherein the adaptive aggregation memory buffer, EMCL, and integrated processor are integrated with the resistive memory array (Hall’s Fig. 6 modified components with CHANDRAMANI’s teachings in context of para [0081], para [0038]: circuitry “part of a larger SOC”).
Regarding claim 4, Hall, CHANDRAMANI, and BRENNAN teach the memory subsystem of claim 1. Hall teaches wherein the adaptive aggregation memory buffer, EMCL, and integrated processor are directly adjacent to the resistive memory array (See Hall Fig. 6 and Fig. 1 components and arrangement in context SOC teachings of para [0038]).
Regarding claim 5, Hall, CHANDRAMANI, and BRENNAN teach the memory subsystem of claim 1. Hall teaches wherein the memory subsystem comprises a system on chip (SoC) compute-in-memory (Hall para [0036], para [0038], para [0081] in context of Fig. 6 memory subsystem).
Regarding claim 6, Hall, CHANDRAMANI, and BRENNAN teach the memory subsystem of claim 1. CHANDRAMANI teaches wherein the integrated processor is configured to pre-read cells of the resistive memory array that will be written by the aggregate memory request (para [0141] and para [0042]) and to selectively write to the cells that will have a change in logic state based on the aggregate memory request without writing to cells having no change in logic state (para [0141] and para [0042] disclosure encompasses the limitation. See also para [0135], para [0146]).
Regarding claim 7, Hall, CHANDRAMANI, and BRENNAN teach the memory subsystem of claim 1. Hall wherein the resistive memory array comprises non-volatile random-access memory (RAM) including one or more of magnetic RAM (MRAM), resistor random access memory, phase change RAM (PCRAM), voltage-controlled magnetic anisotropy (VCMA)-MRAM, or carbon nanotube memory cells (Hall para [0080]. See also CHANDRAMANI para [0074]).
Regarding independent claim 8, Hall teaches a memory subsystem (Fig. 6: 600 “memory subsystem” with smart compute memory and adaptive memory management and control, para [0079]) comprising:
an endurance management and control logic (EMCL) (Fig. 6: 672, 670, 682 combined. See Para [0081]: AMMC and associated circuitry manages and controls “endurance”);
a ferro-electric RAM (FeRAM) memory array or embedded flash memory (Fig. 6: 680, para [0080]: ReRAM, RRAM, FeRAM) coupled to the adaptive aggregation memory buffer (supported by Fig. 6 670 circuitry and buffer),
an adaptive aggregation memory buffer ((Fig. 6: 672 AMMC) coupled to apparatus;
the adaptive aggregation memory buffer has selective power down modes for power and endurance optimizations (para [0077]: low power modes; see also para [0038], para [0043]-para [0044]).
Hall is silent with respect to the details of functions of adaptive aggregation memory buffer and functions of endurance management control logic, and functions of EMCL buffer.
CHANDRAMANI teaches a memory system of (Fig. 10: 1000) with resistive memory array (para [0074]) with circuitry components:
an adaptive aggregation memory buffer (Fig. 17: 1730 and 1742) coupled to the EMCL (para [0134], Fig. 10: 1034 firmware and associated circuitry. Para [0044], para [0107]),
wherein the adaptive aggregation memory buffer (Fig. 17: 1730 and 1742) has configurable settings for optimizing endurance, power, or performance of the memory subsystem (para [0135]-para [0138]).
BRENNAN teaches -
the EMCL (Fig. 2: 210) is configured to determine (Fig. 7: 710, 715) whether two or more memory requests to one or more memory regions during a time window (e.g. read-write cycle) can be aggregated into an aggregate memory request (Fig. 7 in context of para [0068]-para [0074]. See also abstract), and
to cause the aggregate memory request to be sent to the FeRAM memory array or the embedded flash memory (“…operation combiner compares the first read addresses and the first write address to one or more second read addresses and a second write address of a second command stored in a buffer. The operation combiner selectively combines the first and second commands to form an aggregate command based on the comparison…”. See Fig. 7 in context of para [0068]-para [0074]. See also abstract, para [0011], para [0030]) to optimize parameters including memory performance and memory endurance (optimize suggests a relative term, is too broad and associated limitations are not given patentable weight).
Hall, CHANDRAMANI, and BRENNAN are in the same field of endeavor of read/ write operation improvement of resistive memory and system; and they are in analogous art. An ordinary skill in the art would understand the use of CHANDRAMANI’s and BRENNAN’s circuitry components into the apparatus of Hall.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine CHANDRAMANI and BRENNAN’s circuitry components and functionality into the memory subsystem of Hall such that claimed apparatus can be implemented in order to have benefits e.g., “…improves…unaligned write performance and increases the die utilization…” (CHANDRAMANI para [0044], para [0139]) and improve command execution speed (BRENNAN Abstract)
Regarding claim 9, Hall, CHANDRAMANI, and BRENNAN teach the memory subsystem of claim 8, wherein the EMCL is configured to determine a configurable setting of the adaptive aggregation memory buffer based on a memory request type, a usage pattern of an application, or an operating condition. (This claim is drafted as in subsystem format, substantially identical to the limitations recited in claim 2, and is therefore rejected for the same reasons as claim 2. See Claim 2 rejection analysis)
Regarding claim 10, Hall, CHANDRAMANI, and BRENNAN teach the memory subsystem of claim 9. Hall teaches wherein the adaptive aggregation memory buffer has variable clock rates being adjusted for power versus performance optimization or configurable settings including a first mode optimized for writing large amount of data, a second mode optimized for writing small amount of data, a third mode optimized for high-speed writing, and a fourth mode optimized for low-speed writing (para [0041], para [0074], para [0076]).
Regarding claim 11, Hall, CHANDRAMANI, and BRENNAN teach the memory subsystem of claim 8, wherein the adaptive aggregation memory buffer and EMCL are integrated with the FeRAM memory array or embedded flash memory. (This claim is drafted as in subsystem format, substantially identical to the limitations recited in claim 3, and is therefore rejected for the same reasons as claim 3. See Claim 3 rejection analysis)
Regarding claim 12, Hall, CHANDRAMANI, and BRENNAN teach the memory subsystem of claim 9, wherein the adaptive aggregation memory buffer and EMCL are directly adjacent to the FeRAM memory array or embedded flash memory. (This claim is drafted as in subsystem format, substantially identical to the limitations recited in claim 4, and is therefore rejected for the same reasons as claim 4. See Claim 4 rejection analysis)
Regarding claim 13, Hall, CHANDRAMANI, and BRENNAN teach the memory subsystem of claim 8, wherein the memory subsystem comprises a system on chip (SoC) compute-in-memory. (This claim is drafted as in subsystem format, substantially identical to the limitations recited in claim 5, and is therefore rejected for the same reasons as claim 5. See Claim 5 rejection analysis)
Regarding claim 14, Hall, CHANDRAMANI, and BRENNAN teach the memory subsystem of claim 8, wherein the EMCL is configured to cause a pre-read of cells of the FeRAM memory array or embedded flash memory that will be written by the aggregate memory request and to selectively write to the cells that will have a change in logic state based on the aggregate memory request without writing to cells having no change in logic state. (This claim is drafted as in subsystem format, substantially identical to the limitations recited in claim 6, and is therefore rejected for the same reasons as claim 6. See Claim 6 rejection analysis)
Regarding independent claim 15, Hall, CHANDRAMANI, and BRENNAN teach a computer-implemented method for operating a memory subsystem, the computer-implementing method comprises (computer-implemented method is conventional item used conventionally to store and implement computer programs to perform generic computer functions that are well-understood, routine, and conventional activities previously known to the pertinent industry, and several court cases demonstrate that the mere recitation of a computer-implemented method cannot transform a patent-ineligible abstract idea into a patent-eligible invention):
receiving memory requests, with an endurance management and control logic (EMCL), for a non-volatile memory array of the memory subsystem including a non-volatile resistive memory, embedded flash memory, or Ferroelectric RAM (FeRAM);
storing the two or more memory requests including two or more write or read operations in an adaptive aggregation memory buffer of the memory subsystem; and determining whether the two or more memory requests including two or more write or read operations to one or more memory regions during a time window can be aggregated into a single aggregated memory request for a write or read operation to improve endurance, performance, and/or power consumption before sending the single aggregated memory request to the non-volatile memory array.
(This claim is drafted as in subsystem format, substantially identical to the limitations recited in claim 1 and claim 8, and is therefore rejected for the same reasons as claim 1 and claim 8. See Claim 1, 8 rejection analysis)
Regarding claim 16, Hall, CHANDRAMANI, and BRENNAN teach the computer-implemented method of claim 15, further comprising: aggregating with the EMCL the two or more memory requests including write operations aggregated based on time and memory space localization for the single aggregated memory request having the write operation or read operations aggregated based on time and memory space localization into the single aggregate memory request or a reduced number of memory requests.
(Hall and CHANDRAMANI teach the computer-implemented method of claim 15. CHANDRAMANI teaches further comprising: aggregating with the EMCL memory requests (Fig. 17-Fig. 19: aggregated write commands) including write operations aggregated based on time and memory space localization (See Fig. 17-Fig. 19) or read operations aggregated based on time and memory space localization into the aggregate memory request or a reduced number of memory requests (see para [0007], para [0146] in context of Fig. 17-Fig. 19).
Regarding claim 17, Hall, CHANDRAMANI, and BRENNAN teach the computer-implemented method of claim 15. CHANDRAMANI teaches wherein write operations are aggregated into a single write operation (para [0135], Fig. 17) for a temporal and spatial locality within a range of memory addresses of the non-volatile memory array (see para [0007], para [0146], para [0143] in context of Fig. 17-Fig. 19).
Regarding claim 18, Hall, CHANDRAMANI, and BRENNAN teach the computer-implemented method of claim 16. CHANDRAMANI teaches further comprising: at periodic intervals or whenever the adaptive aggregation memory buffer of the memory subsystem is a threshold amount full, performing a pre-read of cells of the non-volatile memory array that will be written to based on the aggregate memory request (see Fig. 17-Fig. 19 in context of para [0135], [0146]. See also para [0141] and para [0042]).
Regarding claim 19, Hall, CHANDRAMANI, and BRENNAN teach the computer-implemented method of claim 18. CHANDRAMANI teaches further comprising: processing the aggregate memory request selectively for each cell of the non-volatile memory array that will have a change in logic state. (Para [0141] and para [0042] in context of Fig. 24: 2420)
Regarding claim 20, Hall, CHANDRAMANI, and BRENNAN teach the computer-implemented method of claim 19. CHANDRAMANI teaches wherein the change in logic state (writing process) comprises a change in resistance state when the non-volatile memory includes a resistive memory array. (Fig. 1, para [0061])
Response to Arguments
Applicant’s arguments (filed 09/19/2025) with respect to claim(s) 1, 8, 15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant argues that obviousness rejection of independent claims under 35 U.S.C. 103 over Hall et al. (US 2022/0013169 A1), and CHANDRAMANI et al. (US 2022/0413756 A1) is not proper because CHANDRAMANI fails to disclose "wherein at least one of the integrated processor and the EMCL is configured to determine whether two or more memory requests including two or more write or read operations to a particular localized memory region during a time window can be aggregated into a single aggregate memory request for a write or read operation and to optimize memory settings, and to cause the single aggregate memory request and memory settings to be sent to the resistive memory array to optimize parameters including memory performance and memory endurance" Multiple written commands in CHANDRAMANI do not get reduced into a single write command and each die is a different memory region. (pages 8-9)
Applicant’s argument is not persuasive because applicant has not provided sufficient reasons and has not considered prior art in its entirety. See new formulated rejection.
Prior Art Not Relied Upon
The prior art made of record and not relied upon (MPEP § 707.05) is considered pertinent to applicant's disclosure: Shin et al (US 2020/0151054): Fig. 1-Fig. 16 disclosure applicable for all claims. Prior art teaches a memory system including a memory module including a plurality of memory chips mounted on a module board; and a memory controller configured to control a memory operation for the plurality of memory chips of the memory module, set at least one memory chip from among the plurality of memory chips as an indicator chip, and, when it is determined based on a result of an error detection for a codeword read from the memory module that an error has occurred in the indicator chip, output reliability deterioration information indicating that reliability of the memory module is deteriorated. It is suggested that applicant consider all prior arts made of record.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/MUSHFIQUE SIDDIQUE/Primary Examiner, Art Unit 2825
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