DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/13/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of Species I in the reply filed on 3/25/2026 is acknowledged.
Claims 8, 16 and 20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 3/25/2026.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6, 9-10, 12-14 and 17-18 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Verma et al. (US 2021/0175371 A1, hereinafter “Verma”).
Regarding independent claim 1, Figures 2-3 of Verma disclose a semiconductor structure comprising:
a first circuit row (i.e., the bottom structure including the bottom 112 shown in Fig. 3) comprising one or more first circuit cells; and
a second circuit row (i.e., the top structure including the top 112 shown in Fig. 3) comprising one or more second circuit cells;
wherein at a cell boundary (i.e., the middle region between the top and bottom gate structures 112 shown in Fig. 3) between the one or more first circuit cells in the first circuit row and the one or more second circuit cells in the second circuit row, one or more first gate regions 112 (“gate structure”- ¶0039) of the one or more first circuit cells in the first circuit row are staggered with one or more second gate regions 112 (“gate structure”- ¶0039) of the one or more second circuit cells in the second circuit row, since the 112a portions of the top and bottom gate structure 112 are staggered with one another.
Regarding claim 2, Figures 2-3 of Verma disclose wherein at the cell boundary between the one or more first circuit cells in the first circuit row and the one or more second circuit cells in the second circuit row, one or more first source/drain regions 108 (“diffusion region”- ¶0047, which would act as source/drain regions given the semiconductor structures are MOS structures- ¶0036) of the one or more first circuit cells in the first circuit row are staggered with one or more second source/drain regions 108 (“diffusion region”- ¶0047, which would act as source/drain regions given the semiconductor structures are MOS structures- ¶0036) of the one or more second circuit cells in the second circuit row.
Regarding claim 3, Figures 2-3 of Verma disclose at the cell boundary between the one or more first circuit cells in the first circuit row and the one or more second circuit cells in the second circuit row, at least one of the one or more first gate regions 112 of the one or more first circuit cells in the first circuit row is aligned with at least one of the one or more second source/drain regions 108 of the one or more second circuit cells in the second circuit row, since the gate regions 112 are evenly spaced from regions 108.
Regarding claim 4, Figures 2-3 of Verma disclose wherein at the cell boundary between the one or more first circuit cells in the first circuit row and the one or more second circuit cells in the second circuit row, at least one of the one or more second gate regions 112 of the one or more second circuit cells in the second circuit row is aligned with at least one of the one or more first source/drain regions 108 of the one or more first circuit cells in the first circuit row, since the gate regions 112 are evenly spaced from regions 108.
Regarding claim 5, Figures 2-3 of Verma disclose the semiconductor structure further comprising individual gate contacts 118’ (“contact plug”- ¶0060, specifically the contacts 118’ connected to bottom and top gate structures 112 and conductive layer 124) to at least one of the one or more first gate regions 112 of the one or more first circuit cells in the first circuit row and at least one of the one or more second gate regions 112 of the one or more second circuit cells in the second circuit row (¶0060).
Regarding claim 6, Figures 2-3 of Verma disclose the semiconductor structure further comprising:
a first gate contact 118’ (“contact plug”- ¶0060, specifically the contact 118’ connected to bottom gate structure 112) to a first one of the one or more first gate regions 112 of a first one of the one or more first circuit cells in the first circuit row;
a second gate contact 118’ (“contact plug”- ¶0060, specifically the contact 118’ connected to top gate structure 112) to a first one of the one or more second gate regions 112 of a first one of the one or more second circuit cells in the second circuit row; and
a gate connection layer 124 (“input conductive layer”- ¶0046) connecting the first gate contact 118’ and the second gate contact 118’ (¶0060).
Regarding claim 9, Figures 2-3 of Verma disclose the semiconductor structure further comprising one or more gate contacts 118’ (“contact plug”- ¶0060, specifically the contacts 118’ connected to bottom and top gate structures 112 and conductive layer 124) to at least one of the one or more first gate regions 112 and the one or more second gate regions 112 from a frontside (i.e., the side of the semiconductor structure with contacts 118’) of the semiconductor structure.
Regarding claim 10, Figures 2-3 of Verma disclose the semiconductor structure further comprising one or more gate contacts 118’ (“contact plug”- ¶0060, specifically the contacts 118’ connected to bottom and top gate structures 112 and conductive layer 124) to at least one of the one or more first gate regions 112 and the one or more second gate regions 112 from a backside (i.e., the side of the semiconductor structure with contacts 118’) of the semiconductor structure.
Regarding claim 12, Figures 2-3 of Verma disclose wherein at least one of the one or more first circuit cells and the one or more second circuit cells comprise at least one of a planar transistor, a fin-type field-effect transistor (i.e., “MOS” transistor- ¶0036), a nanosheet transistor, a nanowire transistor and a stacked field-effect transistor.
Regarding independent claim 13, Figures 2-3 of Verma disclose a semiconductor structure comprising:
an array of circuit cells arranged in a first row (i.e., the bottom structure including the bottom 112 shown in Fig. 3) and at least a second row (i.e., the top structure including the top 112 shown in Fig. 3);
wherein gate regions 112 (“gate structure”- ¶0039) and source/drain regions (“diffusion region”- ¶0047, which would act as source/drain regions given the semiconductor structures are MOS structures- ¶0036) of the array of circuit cells are staggered at a cell boundary (i.e., the middle region between the top and bottom gate structures 112 shown in Fig. 3) of the first row and the second row, since the 112a portions of the top and bottom gate structure 112 are staggered with one another.
Regarding claim 14, Figures 2-3 of Verma disclose the semiconductor structure further comprising individual gate contacts 118’ (“contact plug”- ¶0060, specifically the contact 118’ connected to top gate structure 112) to at least one of the gate regions 112 in the first row of the array of circuit cells and at least one of the gate regions 112 in the second row of the array of circuit cells.
Regarding independent claim 17, Figures 2-3 of Verma disclose an integrated circuit comprising:
an array of circuit cells arranged in a first row (i.e., the bottom structure including the bottom 112 shown in Fig. 3) and at least a second row (i.e., the top structure including the top 112 shown in Fig. 3);
wherein gate regions 112 (“gate structure”- ¶0039) and source/drain regions (“diffusion region”- ¶0047, which would act as source/drain regions given the semiconductor structures are MOS structures- ¶0036) of the array of circuit cells are staggered at a cell boundary (i.e., the middle region between the top and bottom gate structures 112 shown in Fig. 3) of the first row and the second row, since the 112a portions of the top and bottom gate structure 112 are staggered with one another.
Regarding claim 18, Figures 2-3 of Verma disclose the integrated circuit further comprising individual gate contacts 118’ (“contact plug”- ¶0060, specifically the contact 118’ connected to top gate structure 112) to at least one of the gate regions 112 in the first row of the array of circuit cells and at least one of the gate regions 112 in the second row of the array of circuit cells.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Verma in view of He et al. (US 2018/0145081 A1, hereinafter “He”).
Regarding claim 11, Figures 2-3 of Verma disclose wherein the one or more first circuit cells and the one or more second circuit cells comprise transistors (i.e., MOS transistors- ¶0036) as part of varactors (¶0036).
Verma does not expressly disclose wherein the varactors are used in a static random-access memory cell.
He discloses the use of varactors in a static random-access memory cell (¶¶0007, 0017).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Verma such that the varactors are used in a static random-access memory cell as taught by He for the purpose of utilizing varactors in a suitable and well-known configuration/device with increased write speed (He ¶0007).
Allowable Subject Matter
Claims 7, 15 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 7, the prior art of record including Verma, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “wherein the first gate contact, the second gate contact and the gate connection layer are formed at the cell boundary between the one or more first circuit cells in the first circuit row and the one or more second circuit cells in the second circuit row”.
Regarding claim 15, the prior art of record including Verma, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “[the] semiconductor structure… further comprising a first gate contact to at least one of the gate regions in the first row of the array of circuit cells, a second gate contact to at least one of the gate regions in the second row of the array of circuit cells, and a gate connection layer connecting the first gate contact and the second gate contact, wherein the first gate contact, the second gate contact and the gate connection layer are formed at the cell boundary of the first row and the second row”.
Regarding claim 19, the prior art of record including Verma, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “[the] integrated circuit of claim… further comprising a first gate contact to at least one of the gate regions in the first row of the array of circuit cells, a second gate contact to at least one of the gate regions in the second row of the array of circuit cells, and a gate connection layer connecting the first gate contact and the second gate contact, wherein the first gate contact, the second gate contact and the gate connection layer are formed at the cell boundary of the first row and the second row”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Jong et al. (US 2023/0260994 A1), which discloses a semiconductor structure comprising gate regions which are staggered with one another.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C CHANG whose telephone number is (571)272-6132. The examiner can normally be reached Mon- Fri 12pm-10pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571)-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAY C CHANG/Primary Examiner, Art Unit 2817
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