DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to an Application filed on 06/13/2023.
Currently, claims 1-10 are examined as below.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement filed 06/13/2023 fails to comply with 37 CFR 1.98(a)(2), which requires a legible copy of each cited foreign patent document; each non-patent literature publication or that portion which caused it to be listed; and all other information or that portion which caused it to be listed. It has been placed in the application file, but the information referred to therein has not been considered.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
(Marked-Up Version) Semiconductor Chip Enabling Detection of Bonding Defect of Wires and Semiconductor Device Including the Same
(Clean Version) Semiconductor Chip Enabling Detection of Bonding Defect of Wires and Semiconductor Device Including the Same
Claim Objections
Claim 6 is objected to because of the following informalities:
Regarding claim 6, “same current rating” should read “a same current rating.”
Appropriate correction is required.
Claim Rejections - 35 USC § 102/103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3 are rejected under 35 U.S.C. 102(a)(1) as anticipated by US 2010/0045328 A1 to Suto or, in the alternative, under pre-AIA 35 U.S.C. 103 as obvious over Suto.
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Regarding independent claim 1, Suto in Fig. 1 teaches a semiconductor chip 10 (Fig. 1, ¶ 16 & ¶ 26, integrated circuit (IC) or IC chip 10) comprising:
a power transistor 24, 26 (¶ 18, power transistor 24, 26);
a plurality of pads 16, 20 (¶ 17, pads 16, 20);
a plurality of wires 18, 22 (¶ 17, bonding wires 18, 22) arranged to establish continuity between each of the plurality of pads 16, 20 and a first end or a second end of the power transistor 24, 26 (Fig. 1, the connection from the pad 16, 20 to an end of the power transistor 24, 26 continues via the wire 18, 22);
a current detection circuit 30 (¶ 19, detection circuit 30) configured to detect, as a sense voltage, at least one of voltage drops caused in each of the plurality of wires according to a branch current (¶ 28, current flows through the bonding wires 18, 22) flowing through the wire 18, 22 and a wire resistance component 40, 42 (¶ 21, pull-down resistor 40, pull-down resistor 42) of the wire 18, 22 (see Note 1 below); and
a logic 38 (¶ 24, AND gate 38) configured to determine a condition of wire bonding of each of the plurality of pads 16, 20 according to a result of the detection by the current detection circuit 30 (¶ 23-¶ 30) (see Note 2 below).
Note 1: A limitation of “configured to detect, as a sense voltage, at least one of voltage drops caused in each of the plurality of wires according to a branch current flowing through the wire and a wire resistance component of the wire” is attempting to define the claimed current detection circuit by what it does, rather than by what it is, which can be evidenced by its specific structure or specific composition. See MPEP § 2173.05(g). The limitation can be construed as a function and/or a property of the claimed semiconductor chip.
According to Section 2114 of the MPEP, "While features of an apparatus may be recited either structurally or functionally, claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429,1431-32 (Fed. Cir. 1997) (The absence of a disclosure in a prior art reference relating to function did not defeat the Board’s finding of anticipation of claimed apparatus because the limitations at issue were found to be inherent in the prior art reference); see also In re Swinehart, 439 F.2d 210, 212-13, 169 USPQ 226, 228-29 (CCPA 1971); In re Danly, 263 F.2d 844, 847, 120 USPQ 528, 531 (CCPA 1959). “[A]pparatus claims cover what a device is, not what a device does.” Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990) (emphasis in original)".
Here, since Suto teaches all of the claimed structure limitations of the claimed semiconductor chip, the semiconductor chip taught by Suto is capable of performing the claimed function as recited in the limitation above.
Furthermore, according to Section 2112.III of the MPEP, "Where applicant claims a composition in terms of a function, property or characteristic{,} and the composition of the prior art is the same as that of the claim but the function is not explicitly disclosed by the reference, the examiner may make a rejection under both 35 U.S.C. 102 and 103, expressed as a 102/103 rejection. “There is nothing inconsistent in concurrent rejections for obviousness under 35 U.S.C. 103 and for anticipation under 35 U.S.C. 102.” In re Best, 562 F.2d 1252, 1255 n.4, 195 USPQ 430, 433 n.4 (CCPA 1977). This same rationale should also apply to product, apparatus, and process claims claimed in terms of function, property or characteristic. Therefore, a 35 U.S.C. 102/103 rejection is appropriate for these types of claims as well as for composition claims {underlined for emphasis}."
Here, the limitation does not structurally distinguish the claimed current detection circuit over the prior art as is it directed to a function or property of the claimed semiconductor chip. The semiconductor chip including inherently has the property or can function as recited in the limitation above.
Note 2: A limitation of “configured to determine a condition of wire bonding of each of the plurality of pads according to a result of the detection by the current detection circuit” is attempting to define the claimed logic by what it does, rather than by what it is, which can be evidenced by its specific structure or specific composition. See MPEP § 2173.05(g). The limitation can be construed as a function and/or a property of the claimed semiconductor chip.
According to Section 2114 of the MPEP, "While features of an apparatus may be recited either structurally or functionally, claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429,1431-32 (Fed. Cir. 1997) (The absence of a disclosure in a prior art reference relating to function did not defeat the Board’s finding of anticipation of claimed apparatus because the limitations at issue were found to be inherent in the prior art reference); see also In re Swinehart, 439 F.2d 210, 212-13, 169 USPQ 226, 228-29 (CCPA 1971); In re Danly, 263 F.2d 844, 847, 120 USPQ 528, 531 (CCPA 1959). “[A]pparatus claims cover what a device is, not what a device does.” Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990) (emphasis in original)".
Here, since Suto teaches all of the claimed structure limitations of the claimed semiconductor chip, the semiconductor chip taught by Suto is capable of performing the claimed function as recited in the limitation above.
Furthermore, according to Section 2112.III of the MPEP, "Where applicant claims a composition in terms of a function, property or characteristic{,} and the composition of the prior art is the same as that of the claim but the function is not explicitly disclosed by the reference, the examiner may make a rejection under both 35 U.S.C. 102 and 103, expressed as a 102/103 rejection. “There is nothing inconsistent in concurrent rejections for obviousness under 35 U.S.C. 103 and for anticipation under 35 U.S.C. 102.” In re Best, 562 F.2d 1252, 1255 n.4, 195 USPQ 430, 433 n.4 (CCPA 1977). This same rationale should also apply to product, apparatus, and process claims claimed in terms of function, property or characteristic. Therefore, a 35 U.S.C. 102/103 rejection is appropriate for these types of claims as well as for composition claims {underlined for emphasis}."
Here, the limitation does not structurally distinguish the claimed logic over the prior art as is it directed to a function or property of the claimed semiconductor chip. The semiconductor chip including inherently has the property or can function as recited in the limitation above.
Regarding claim 2, Suto in Fig. 1 further teaches the logic 38 determines the condition of wire bonding 18, 22 to be defective, when the sense voltage does not coincide with an expected value.
A limitation of “determines the condition of wire bonding to be defective, when the sense voltage does not coincide with an expected value” is attempting to define the claimed logic by what it does, rather than by what it is, which can be evidenced by its specific structure or specific composition. See MPEP § 2173.05(g). The limitation can be construed as a function and/or a property of the claimed semiconductor chip.
According to Section 2114 of the MPEP, "While features of an apparatus may be recited either structurally or functionally, claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429,1431-32 (Fed. Cir. 1997) (The absence of a disclosure in a prior art reference relating to function did not defeat the Board’s finding of anticipation of claimed apparatus because the limitations at issue were found to be inherent in the prior art reference); see also In re Swinehart, 439 F.2d 210, 212-13, 169 USPQ 226, 228-29 (CCPA 1971); In re Danly, 263 F.2d 844, 847, 120 USPQ 528, 531 (CCPA 1959). “[A]pparatus claims cover what a device is, not what a device does.” Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990) (emphasis in original)".
Here, since Suto teaches all of the claimed structure limitations of the claimed semiconductor chip, the semiconductor chip taught by Suto is capable of performing the claimed function as recited in the limitation above.
Furthermore, according to Section 2112.III of the MPEP, "Where applicant claims a composition in terms of a function, property or characteristic{,} and the composition of the prior art is the same as that of the claim but the function is not explicitly disclosed by the reference, the examiner may make a rejection under both 35 U.S.C. 102 and 103, expressed as a 102/103 rejection. “There is nothing inconsistent in concurrent rejections for obviousness under 35 U.S.C. 103 and for anticipation under 35 U.S.C. 102.” In re Best, 562 F.2d 1252, 1255 n.4, 195 USPQ 430, 433 n.4 (CCPA 1977). This same rationale should also apply to product, apparatus, and process claims claimed in terms of function, property or characteristic. Therefore, a 35 U.S.C. 102/103 rejection is appropriate for these types of claims as well as for composition claims {underlined for emphasis}."
Here, the limitation does not structurally distinguish the claimed logic over the prior art as is it directed to a function or property of the claimed semiconductor chip. The semiconductor chip including inherently has the property or can function as recited in the limitation above.
Regarding claim 3, Suto in Fig. 1 further teaches any of the plurality of wires 18, 22 from which the sense voltage is derived is installed on an element-forming region (Fig. 1, an end of the power transistor 24, 26) of the power transistor 24, 26.
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Claims 4-10 are objected to as being dependent upon a rejected base claim, but would be allowable if (i) rewritten in independent form to include all of the limitations of the base claim and any intervening claims or (ii) the objected claim and any intervening claims are fully incorporated into the base claim, AND if any claim objections as set forth in this Office action are overcome.
Claim 4 would be allowable, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 4, the plurality of pads include a plurality of output pads, a plurality of output wires arranged to establish continuity between each of the plurality of output pads and the second end of the power transistor, and the semiconductor chip further includes a multiplexer configured to alternatively output, as the sense voltage, any one of a first sense voltage caused in at least one of the plurality of input wires and a second sense voltage caused in at least one of the plurality of output wires to the current detection circuit.
Claims 5-6 would be allowable, because they depend from the allowable claim 4.
Claim 7 would be allowable, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 7, wherein the power transistor is divided into a plurality of unit transistors having respective control terminals connected in common to each other.
Claim 8 would be allowable, because they depend from the allowable claim 7.
Claim 9 would be allowable, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 9, an output voltage outputted from the power transistor or a feedback voltage corresponding to the output voltage coincides with a reference voltage.
Claim 10 would be allowable, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 10, a semiconductor device comprising: a plurality of external electrodes; and wires arranged to establish bonding between the plurality of external electrodes and the plurality of pads.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2006/0238944 A1 to Yamamoto
US 2020/0027957 A1 to Umemoto et al.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIKKA LIU whose telephone number is (571)272-2568. The examiner can normally be reached on 9AM-5AM EST M-F.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached on 571-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/M.L./Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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