Prosecution Insights
Last updated: April 19, 2026
Application No. 18/334,010

SEMICONDUCTOR STORAGE DEVICE AND SEMICONDUCTOR STORAGE DEVICE MANUFACTURING METHOD

Non-Final OA §103§112
Filed
Jun 13, 2023
Examiner
BRADFORD, PETER
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Kioxia Corporation
OA Round
1 (Non-Final)
80%
Grant Probability
Favorable
1-2
OA Rounds
2y 8m
To Grant
84%
With Interview

Examiner Intelligence

Grants 80% — above average
80%
Career Allow Rate
586 granted / 733 resolved
+11.9% vs TC avg
Minimal +4% lift
Without
With
+4.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
42 currently pending
Career history
775
Total Applications
across all art units

Statute-Specific Performance

§101
1.2%
-38.8% vs TC avg
§103
41.1%
+1.1% vs TC avg
§102
24.3%
-15.7% vs TC avg
§112
32.5%
-7.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 733 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restriction Pursuant to the election without traverse of invention I on December 1, 2025, claims 15-19 are withdrawn from consideration. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The examiner proposes: 3D MEMORY DEVICE WITH TAPERED DIVIDING PLATE Claim Objection Claims 7 and 13 recite that “the charge storage layer is applied a voltage via a word line functioning as the conductive layer.” This is awkward and should be revised. The examiner understands this to mean that a voltage is applied by the word line to the charge storage layer. Claim interpretation The recitation in claim 1 that “a conductive layer and an insulating layer are stacked multiple number of times from a bottom of the stacked body to a top of the stacked body” is interpreted to mean that a pair of a conductive layer and an insulating layer are repeated multiple times in a stack. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 1-5, 8-11, and 14 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, because the specification, while being enabling for memory pillars, does not reasonably provide enablement for other kinds of pillars. The specification does not enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to practice the invention commensurate in scope with these claims. The application discloses an invention that involves memory pillars and division plates. It does not disclose any application that involves any other kind of pillar, such as a metal pillar or a support pillar. The application would not enable those in the art to practice it with any other kind of pillar. (A) The breadth of the claims – the claims encompass any pillar. (B) The nature of the invention – the invention as disclosed addresses only memory pillars. (C) The state of the prior art would not provide additional insights as to how to apply the invention to other pillars. (D) The level of one of ordinary skill in the art would not provide (E) The level of predictability in the art would not provide a predictable application to other kinds of pillars. (F) The amount of direction provided by the inventor – the inventor has not provided any direction as to how to use other kinds of pillars. (G) The existence of working examples – there are no working examples that apply to other kinds of pillars. (H) The quantity of experimentation needed to make or use the invention based on the content of the disclosure would be undue experimentation due to the lack of guidance in the specification. The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 6 and 12 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. These claims recite “the memory pillar”, which lacks antecedent basis. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1 and 4-8 are rejected under 35 U.S.C. 103 as being unpatentable over Lee, US 2022/0077182 A1, in view of Yang, US 2022/0359561 A1. Claim 1: Lee discloses a stacked body (335) where a conductive layer (13/23) and an insulating layer (21) are stacked multiple number of times from a bottom of the stacked body to a top of the stacked body; a plate-shaped portion (SG) extending along a stacking direction of the stacked body and a first direction intersecting the stacking direction and dividing the stacked body along a second direction intersecting the stacking direction and the first direction (FIG. 3A); and a pillar (CH) penetrating the stacked body and extending along the stacking direction, wherein a width of the plate-shaped portion in the second direction (horizontal) at the same height as a conductive layer located at the top of the stacked body is larger than a width of the plate-shaped portion in the second direction at the same height as a conductive layer located at the bottom of the stacked body (FIG. 3A, inverted). PNG media_image1.png 550 756 media_image1.png Greyscale Lee does not disclose that a width of the pillar (666) in the second direction (horizontal) at the same height as the conductive layer located at the top of the stacked body is smaller than a width of the pillar in the second direction at the same height as the conductive layer located at the bottom of the stacked body. However, this was known in the art. See Yang FIG. 12: PNG media_image2.png 456 320 media_image2.png Greyscale (Note that the drawings of Lee and Yang are inverted with respect to each other, and thus Lee is viewed inverted, and Yang is viewed uninverted.) It would have been obvious to have used the pillar of Yang as a known channel pillar effective for forming a memory stack. Claim 4: the pillar is a memory pillar. Claim 5: Yang discloses a dummy pillar (222, Yang FIG. 2, [0045]). Yang does not illustrate the dummy pillars, but it was common to have the dummy pillars have the same structure as regular pillars, and thus it would have been obvious to have the dummy pillars penetrating the stacked body and extending along the stacking direction, wherein a width of the dummy pillar in the second direction at the same height as the conductive layer located at the top of the stacked body is smaller than a width of the dummy pillar in the second direction at the same height as the conductive layer located at the bottom of the stacked body. Claim 6: the sizes of the memory pillar and the dummy pillar are not disclosed. However, it would have been within ordinary skill in the art to determine the appropriate sizes of each. Changes in dimension are not typically a source of patentable distinction absent unexpected results. MPEP 2144.04(IV). Claim 7: the pillar includes a charge storage layer (337-2), the charge storage layer is applied a voltage via a word line (WL) functioning as the conductive layer. 8. The semiconductor storage device according to claim 1, further comprising: a peripheral circuit including a transistor on the bottom of the stacked body (Lee, SST, FIG. 1). Allowable Subject Matter Claim 13 is objected to as being dependent upon a rejected base claim, and is objected to based on the claim language as noted above, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and if the claim objection is addressed. If the scope of enablement rejection is addressed, claims 2, 3, 9-11, and 14 would distinguish over the prior art. The prior art reviewed by the examiner does not show the various levels of decreasing width of claim 2, or the width relationship of the core of the pillar of claim 9. Lee discloses (FIG. 9C) an etch having an opposite taper to that of the memory pillars, but not going through the stack, and not to form the claimed plate. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER BRADFORD whose telephone number is (571)270-1596. The examiner can normally be reached 10:30-6:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469.295.9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PETER BRADFORD/Primary Examiner, Art Unit 2897
Read full office action

Prosecution Timeline

Jun 13, 2023
Application Filed
Mar 07, 2026
Non-Final Rejection — §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604477
SEMICONDUCTOR DEVICE WITH CONDUCTIVE LAYERS IN ISOLATION STRUCTURES
2y 5m to grant Granted Apr 14, 2026
Patent 12604585
MICROLED CONNECTION WITH CU BUMP ON TI/AL WIRE
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Patent 12593573
DISPLAY DEVICE COMPRISING A DISPLAY PANEL HAVING INSULATING LAYERS OVER A PAD AND METHOD OF PROVIDING THE DISPLAY PANEL
2y 5m to grant Granted Mar 31, 2026
Patent 12581658
FERROELECTRIC MEMORY WITH MULTIPLE FERROELETRIC LAYERS THROUGH A STACK OF GATE LINES
2y 5m to grant Granted Mar 17, 2026
Patent 12575429
SEMICONDUCTOR PACKAGE HAVING A LEAD FRAME AND A CLIP FRAME
2y 5m to grant Granted Mar 10, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
80%
Grant Probability
84%
With Interview (+4.1%)
2y 8m
Median Time to Grant
Low
PTA Risk
Based on 733 resolved cases by this examiner. Grant probability derived from career allow rate.

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