DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group II (claims 10–20, drawn to a semiconductor package) and Species B (Figs. 15, 16a, and 16b) in the reply filed on 19 Feb 2026 is acknowledged.
Claims 1–9 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention (Group I, drawn to a method for manufacturing a semiconductor package), there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 19 Feb 2026.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 13 June 2023 and 16 March 2026 have been considered by the examiner.
Specification
The disclosure is objected to because of the following informalities: the examiner finds the phrase “wrapper paper properties” in ¶[0047] and ¶[0096] to be unclear. Based on the fact that the present specification mentions “wrapper paper properties” as part of the “thermal properties of the package board”, the examiner understands the “stiffener”, as well as other features, of the present application to have the purpose of preventing warpage of a substrate and cracks in underfill material due to differing coefficients of thermal expansion of the various materials included in a semiconductor package (e.g., see paragraphs 0004, 0056–57, 00100, 00106, 00113–114). Thus, the examiner believes that “wrapper paper properties” is a mistranslation and that the intended meaning of this phrase is “warpage properties”, “warping properties”, or similar.
Appropriate correction is required.
Claim Objections
Claim 19 is objected to because of the following informality: it is recommended that “opposite second side” in the second from last paragraph be amended to include a comma as in, “opposite, second side”.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 15 is rejected (and claims 2 and 7 would likewise be rejected if they did not presently stand as withdrawn/non-elected) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 2 (a withdrawn claim), it is unclear which of the two first semiconductor chips is referred to by “the first semiconductor chip” in the last line. If this phrase were rewritten as “the first semiconductor chips” then it would be understood that the phrase refers to both of the two first semiconductor chips.
Regarding claim 7 (a withdrawn claim), since the claim says that the plurality of insulating layers comprise any one of the three options, each option is considered to be independent of the other options, and therefore “the silicon material” in the last line lacks antecedent basis and should properly be “a silicon material”.
Regarding claim 15, since the claim says that the plurality of insulating layers comprise any one of the three options, each option is considered to be independent of the other options, and therefore “the silicon material” in the last line lacks antecedent basis and should properly be “a silicon material”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 10 is rejected under 35 U.S.C. 102 (a)(1) and (a)(2) as being anticipated by patent application publication US 2022/0230969 A1 by Yeh et al. (“Yeh” hereinafter).
Regarding claim 10, Yeh teaches:
A semiconductor package PKS1 (Fig. 3B) comprising:
a package board 300;
an interposer 100′ mounted on the package board 300;
a plurality of semiconductor chips 21 and 22 mounted on the interposer 100′;
a stiffener RS1 and RS2 (“a first ring structure RS1 (first stiffener ring)” and “a second ring structure RS2 (second stiffener ring)” ¶[0038]) on the package board 300 that extends around the interposer 100′ (“The first ring structure RS1 may surround the interposer structure 100′ ” ¶[0038]; see Figs. 3C and 3D);
a first underfill 112 that surrounds a plurality of first bumps 110 between the plurality of semiconductor chips 21 and 22 and the interposer 100′; and
a second underfill 350 that surrounds a plurality of second bumps 118 between the package board 300 and the interposer 100′, and wherein a thickness of the second underfill 350 on a sidewall of the interposer 100′ increases in a direction from a first side (top) of the interposer to an opposite, second side (bottom) of the interposer.
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Claims 10–13 and 15–16 are rejected under 35 U.S.C. 102 (a)(2) as being anticipated by patent application publication US 2024/0063208 A1 by Lee et al. (“Lee” hereinafter).
Regarding claim 10, Lee teaches:
A semiconductor package 100 (Figs. 17A and 17B, “first package component 100” ¶[0059]) comprising:
a package board 82 (“The package component 82 may be or may comprise an interposer, a package, a core substrate, a coreless substrate, a printed circuit board, or the like” ¶[0054]);
an interposer 46 (“redistribution structure 46” ¶[0032]) mounted on the package board 82;
a plurality of semiconductor chips 50A and 50B (“Each package component 50B may be a semiconductor die similar to the package component 50A” ¶[0043]) mounted on the interposer 46;
a stiffener 90 (“stiffener ring 90” ¶[0059]) on the package board 82 that extends around the interposer 46 (as shown in Fig. 17B);
a first underfill 56 (“underfill 56” ¶[0059]) that surrounds a plurality of first bumps 44 (“conductive connectors 44, such as solder” ¶[0044]) between the plurality of semiconductor chips 50A and 50B and the interposer 46; and
a second underfill 86 (“underfill 86” ¶[0059]) that surrounds a plurality of second bumps 70 and 72 (“UBMs 70 and conductive connectors 72” ¶[0051]; “The formation of the conductive connectors 72 may include placing solder balls on the exposed portions of the UBMs 70” ¶[0052]) between the package board 82 and the interposer 46, and wherein a thickness of the second underfill 86 on a sidewall of the interposer 46 increases in a direction (down) from a first side (top) of the interposer 46 to an opposite, second side (bottom) of the interposer 46 (as shown in Fig. 17A).
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Regarding claim 11, Lee teaches:
The semiconductor package 100 of claim 10,
wherein the plurality of semiconductor chips 50A and 50B comprise two1 first semiconductor chips 50A mounted at a center of the first side (top in Fig. 17A) of the interposer 46, a plurality of second semiconductor chips 50B (top row in Fig. 17B) mounted on the first side (top in Fig. 17A) of the interposer 46 adjacent to a first side (positive-Y side in Fig. 17B) of the first semiconductor chips 50A, and a plurality of third semiconductor chips 50B (bottom row in Fig. 17B) mounted on the first side (top in Fig. 17A) of the interposer 46 adjacent to an opposite, second side (negative-Y side) of the first semiconductor chips 50A.
Regarding claim 12, Lee teaches:
The semiconductor package 100 of claim 11,
wherein the first semiconductor chips 50A comprise an ASIC (application specific integrated circuit) (“each package component 50A may comprise an Application Specific Integrated Circuit (ASIC) die” ¶[0015]), and
wherein the second semiconductor chips 50B (top row in Fig. 17B) and the third semiconductor chips 50B (bottom row in Fig. 17B) comprise a HBM (High Bandwidth Memory) semiconductor chip (“each package component 50B may comprise a memory die such as a DRAM die (e.g., a high bandwidth memory (HBM) die)” ¶[0023]).
Regarding claim 13, Lee teaches:
The semiconductor package 100 of claim 11, further comprising:
a molding part 56 between the second semiconductor chips 50B (top row in Fig. 17B) and between the third semiconductor chips 50B (bottom row in Fig. 17B).
Explanation: one part of the underfill 56 is located between the layer of semiconductor chips 50A and 50B and the interposer 46, comprising the first underfill 56 as described above in the rejection of claim 10; and another part of the underfill 56 comprises the molding part 56 of the present claim and is located between the second semiconductor chips 50B and between the third semiconductor chips 50B as shown in Fig. 17A and described in the specification: “The package structures 14 [examiner: as shown in Fig. 17B, each package structure 14 is equivalent to one unit of a first semiconductor chip 50A and its surrounding molding material 52] are physically isolated from each other and from the package components 50B by the underfill 56. In addition, the package components 50B are physically isolated from each other by the underfill 56” ¶[0061].
Regarding claim 15, Lee teaches:
The semiconductor package 100 (Figs. 17A and 17B) of claim 10,
wherein the interposer 46 comprises a plurality of insulating layers 24 (“a plurality of insulating layers 24” ¶[0033]), a plurality of redistribution layers 26 (“a plurality of RDLs 26” ¶[0033]) inside the plurality of insulating layers 24, and a plurality of vias that connect some of the plurality of redistribution layers 26 (e.g., “the RDL 26-2 is formed on the insulating layer 24-2, wherein the RDL 26-2 is electrically connected to the RDL 26-1. The RDL 26-2 includes via portions extending into the openings in the insulating layer 24-2” ¶[0036]), and wherein the plurality of insulating layers 24 comprise an organic compound (“the insulating layer 24-1 is formed of or comprises an organic material, which may be a polymer. The organic material may also be a photo-sensitive material. For example, the insulating layer 24-1 may be formed of or comprise polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), or the like” ¶[0033]; “the insulating layer 24-2 may comprise a photo-sensitive material such as PBO, polyimide, BCB, or the like” ¶[0035]; “insulating layers 24-3, 24-4 and 24-5 may be formed of an organic material, which may be a polymer such as polyimide, PBO, BCB, or the like” ¶[0037]).
Regarding claim 16, Lee teaches:
The semiconductor package 100 of claim 11,
wherein the first underfill 56 is between the first semiconductor chips 50A, between the first semiconductor chips 50A and the second semiconductor chips 50B (top row in Fig. 17B), and between the first semiconductor chips 50A and the third semiconductor chips 50B (top row in Fig. 17B).
The specification states: “The package structures 14 [examiner: as shown in Fig. 17B, each package structure 14 is equivalent to one unit of a first semiconductor chip 50A and its surrounding molding material 52] are physically isolated from each other and from the package components 50B by the underfill 56” ¶[0061]. Since the package components 50B include both the present application’s “second semiconductor chips” 50B (top row in Fig. 17B) and “third semiconductor chips” 50B (bottom row in Fig. 17B), in order for the package structures 14 to be “physically isolated from each other and from the package components 50B by the underfill 56” as described in ¶[0061], the underfill 56 is located between the package structures 14 (i.e., between the first semiconductor chips 50A), between the first semiconductor chips 50A and the second semiconductor chips 50B (top row in Fig. 17B), and between the first semiconductor chips 50A and the third semiconductor chips 50B (bottom row in Fig. 17B). This “between” arrangement of the underfill 56 is shown in Fig. 17B by the continuity of the underfill 56 between the package structures 14, and between the package structures 14 and the second/third semiconductor chips 50B.
Claims 10 and 17 are rejected under 35 U.S.C. 102 (a)(2) as being anticipated by patent application publication US 2023/0395563 A1 by Hsu et al. (“Hsu” hereinafter).
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Regarding claim 10, Hsu teaches:
A semiconductor package 400 (Figs. 4A and 4B, “device package 400” ¶[0068]) comprising:
a package board 402 (“device package substrate 402” ¶[0070]);
an interposer 216 (unlabeled in Fig. 4B, but part of the multi-die package 200 of Fig. 2B that is part of the device package 400 of Fig. 4B) mounted on the package board 402;
a plurality of semiconductor chips 204, 206, 208, 210a, and 210b (Fig. 4A, “active IC dies 204-208” ¶[0044] and “non-active dies 210a and 210b” ¶[0045]) mounted on the interposer 216;
a stiffener 404 (“stiffener structure 404” ¶[0070]) on the package board 402 that extends around the interposer 216 (as shown in Fig. 4A);
a first underfill 214a (“underfill material 214a” ¶[0056]) that surrounds a plurality of first bumps 218 (“The connection structures 218 may include a stud, a pillar, a bump, a solderball, …” ¶[0056]) between the plurality of semiconductor chips 204–208 and 210a–b and the interposer 216; and
a second underfill 410 (“underfill material 410” ¶[0071]) that surrounds a plurality of second bumps 224 (“connection structures 224” ¶[0059]; in the example implementation of Fig. 10B, “the connection structures 224 may include controlled collapse chip connection (C4) bumps, micro bumps, electroless nickel-electroless palladium-immersion gold technique (ENEPIG) formed bumps, and/or another type of conductive structures that are connected to the pad column portions of the connection structures 224” ¶[0103]) between the package board 402 and the interposer 216, and wherein a thickness of the second underfill 410 on a sidewall of the interposer 216 increases in a direction (down) from a first side (top) of the interposer 216 to an opposite, second side (bottom) of the interposer 216.
Regarding claim 17, Hsu teaches:
The semiconductor package 400 of claim 10,
wherein a region defined by an edge of the interposer 216 and side walls of the plurality of semiconductor chips 204–208 and 210a–b has a width (any of D5–D12 in Fig. 3) that is greater than 50 µm (“one or more of the distances D5–D12 may be included in a range of approximately 60 microns to approximately 150 microns” ¶[0066]).
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Claims 10 and 18 are rejected under 35 U.S.C. 102 (a)(2) as being anticipated by patent application publication US 2023/0420314 A1 by Wang et al. (“Wang” hereinafter).
Regarding claim 10, Wang teaches:
A semiconductor package (Fig. 17) comprising:
a package board 200;
an interposer 900 mounted on the package board 200;
a plurality of semiconductor chips 701 and 703 mounted on the interposer 900;
a stiffener 294 (“The stabilization structure 294 may comprise a stiffener structure” ¶[0116]) on the package board 200 that extends around the interposer 900;
a first underfill 950 that surrounds a plurality of first bumps 940 between the plurality of semiconductor chips 701 and 703 and the interposer 900; and
a second underfill 292 that surrounds a plurality of second bumps 290 between the package board 200 and the interposer 900, and wherein a thickness of the second underfill 292 on a sidewall of the interposer 900 increases in a direction (down) from a first side (top) of the interposer 900 to an opposite, second side (bottom) of the interposer 900.
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Regarding claim 18, Wang teaches:
The semiconductor package (Fig. 17) of claim 10,
wherein the second underfill 292 covers an outer portion of a first side (top) of the package board 200 and an inner portion of the stiffener 294.
Explanation: as shown in Fig. 17, the bottom-left and bottom-right corners of the second underfill 292 appear to be in contact with the bottom of the inner sidewalls of the stiffener 294. Also in Fig. 17, the leftmost and rightmost portions of the second underfill 292 cover an outer portion of the top side of the package board 200.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of patent application publication US 2021/0358866 A1 by Choi (“Choi” hereinafter, corresponding to KR 10-2021-0138223 A from the IDS received on 16 Mar 2026).
Regarding claim 19, Lee teaches:
A semiconductor package 100 (Figs. 17A and 17B) comprising:
a package board 82;
an interposer 46 mounted on the package board 82;
a plurality of semiconductor chips 50A and 50B comprising two2 first semiconductor chips 50A mounted at a center of a first side (top in Fig. 17A) of the interposer 46, a plurality of second semiconductor chips 50B (top row in Fig. 17B) mounted on the first side (top in Fig. 17A) of the interposer 46 adjacent to a first side (positive-Y side in Fig. 17B) of the first semiconductor chips 50A, and a plurality of third semiconductor chips 50B (bottom row in Fig. 17B) mounted on the first side (top in Fig. 17A) of the interposer 46 adjacent to an opposite, second side (negative-Y side) of the first semiconductor chips 50A;
a stiffener 90 on the package board 82 that extends around the interposer 46;
a first underfill 56 that surrounds a plurality of first bumps 44 between the plurality of semiconductor chips 50A and 50B and the interposer 46, and wherein the first underfill 56 is between3 the first semiconductor chips 50A, between the first semiconductor chips 50A and the second semiconductor chips 50B (top row in Fig. 17B), and between the first semiconductor chips 50A and the third semiconductor chips 50B (bottom row in Fig. 17B); and
a second underfill 86 that surrounds a plurality of second bumps 70 and 72 between the package board 82 and the interposer 46, and wherein a thickness of the second underfill 86 on a sidewall of the interposer 46 increases in a direction (down) from the first side (top) of the interposer 46 to an opposite[,] second side (bottom) of the interposer 46,
wherein the interposer 46 has a rectangular configuration (as shown in the top view of Fig. 17B).
However, Lee fails to teach:
“a molding part between the second semiconductor chips and between the third semiconductor chips”; and
“the interposer has a rectangular configuration with rounded corners and at least one rounded side surface”.
In an analogous semiconductor package, Choi discloses a semiconductor package (Figs. 8–10) comprising:
a package board 100 (Figs. 9–10);
an interposer 110 mounted on the package board 100;
a plurality of semiconductor chips 120 and 130 comprising one first semiconductor chip 130 mounted at a center of a first side (top in Fig. 10) of the interposer 110, a plurality of second semiconductor chips 120 (left column in Fig. 9) mounted on the first side (top in Fig. 10) of the interposer 110 adjacent to a first side (negative-DR1 side in Fig. 9) of the first semiconductor chip 130, and a plurality of third semiconductor chips 120 (right column in Fig. 9) mounted on the first side (top in Fig. 10) of the interposer 110 adjacent to an opposite, second side (positive-DR1 side in Fig. 9) of the first semiconductor chip 130;
a stiffener 160 (Fig. 10, “heat sink 160” ¶[0032]) on the package board 100 that extends around the interposer 110;
a first underfill 152 that surrounds a plurality of first bumps 143 between the plurality of semiconductor chips 120 and 130 and the interposer 110;
a molding part 270 (“first mold layer 270” ¶[0081]) between (as shown in Figs. 8–9) the second semiconductor chips 120 (left column in Fig. 9) and between (as shown in Figs. 8–9) the third semiconductor chips 120 (right column in Fig. 9); and
a second underfill 151 that surrounds a plurality of second bumps 142 between the package board 100 and the interposer 110,
wherein the interposer 110 has a rectangular configuration (as shown in the isometric view of Fig. 8 and the top view of Fig. 9) with rounded corners (“the interposer 110 is shown in FIG. 2 as having a rectangular shape with curved corners” ¶[0043]) and at least one rounded side surface4 110s3 (see ¶[0041–0043], ¶[0082–0083], and compare Figs. 1–2 with Figs. 8–9; “the interposer 110 may comprise four third sidewalls 110s3 having a curved surface shape which each connects a first sidewall 110s1 to a second sidewall 110s2” ¶[0043]).
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As described above, Choi’s semiconductor package of Figs. 8–10 shares many features in common with Lee’s semiconductor package 100 of Figs. 17A–17B, demonstrating that these two semiconductor packages are closely analogous to one another. Additionally, the features from Choi marked in bold text above are the specific features of the present claim that are missing from Lee.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee’s semiconductor package 100 of Figs. 17A–17B to include a molding part between the second semiconductor chips 50B (top row in Fig. 17B) and between the third semiconductor chips 50B (bottom row in Fig. 17B) similar to Choi’s molding part 270 in Figs. 8–10, which is located between the second semiconductor chips 120 (left column in Fig. 9) and between the third semiconductor chips 120 (right column in Fig. 9). The reasons for obviousness are twofold:
First, moldings or encapsulations surrounding semiconductor chips and located between semiconductor chips within a semiconductor package are well-known features of semiconductor packages for purposes such as mechanical support, protection against mechanical damage, thermal management, and/or protection from moisture or oxidation. When added to Lee’s semiconductor package 100 of Figs. 17A–17B, Choi’s “first mold layer 270” would merely perform the same function as it presently does in Choi’s Figs. 8–10 to “wrap each sidewall of the second semiconductor chip 120 and the third semiconductor chip 130” Choi ¶[0081].
Second, Lee’s semiconductor package 100 of Figs. 17A–17B already has a molding part located between the second and third semiconductor chips 50B; that is, the feature labeled as 56, in addition to being an underfill 56 surrounding the first bumps 44 between the layer of semiconductor chips 50A–50B and the interposer 46 (as shown in the cross-sectional view of Fig. 17A), also extends upward to be located between (as shown in the top view of Fig. 17B) adjacent semiconductor chips 50B, which includes both the second semiconductor chips (top row of chips 50B in Fig. 17B) and the third semiconductor chips (bottom row of chips 50B in Fig. 17B). Thus, a lower part of the feature labeled 56 in Figs. 17A–17B acts as the first underfill 56, and an upper part of the feature labeled 56 acts as the molding part 56. Incorporating Choi’s molding part 270 from Figs. 8–10 into Lee’s semiconductor package 100 of Figs. 17A–17B is equivalent to replacing the upper part of the feature labeled 56 in Figs. 17A–17B with Choi’s molding part 270. A person of ordinary skill in the art could have substituted the upper part of the feature labeled 56 in Lee’s Figs. 17A–17B with a separate molding part, and the results of the substitution would have been predictable. That is, it would have been obvious to use two separate encapsulations (an underfill under the chips and a molding layer between the chips) instead of a single encapsulation acting as both underfill material under the chips and molding material between the chips.
Furthermore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee’s semiconductor package 100 of Figs. 17A–17B by rounding the four corners of the rectangular interposer 46 in the top view of Fig. 17B in order to prevent the formation of cracks in the interposer 46, as suggested by Choi: “Aspects of the present inventive concepts provide a semiconductor package with increased reliability, by forming at least a partial portion of a sidewall of an interposer into a curved surface that prevents a crack from being generated in a lower portion of the interposer” ¶[0005] (see also ¶[0071]). In modifying the four sharp, right-angled corners of the rectangular interposer 46 in the top view of Lee’s Fig. 17B to instead be rounded corners similar to Choi’s rounded corners in Figs. 8–9, the sidewalls that extend from the rounded corners in the thickness direction of the interposer would necessarily become curved sidewalls that connect adjacent planar sidewalls of the interposer.
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Claim 14 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The closest prior art of Yeh, Lee, Hsu, Wang, and Choi, either singularly or in combination, fails to anticipate or render obvious that
“the molding part comprises a filler having a size greater than 1.5 times a filler in the first underfill and second underfill”
in combination with all other limitations in the claim as claimed and defined by applicant.
Claim 20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The closest prior art of Lee and Choi, as applied in combination in the rejection of claim 19, upon which claim 20 depends, fails to anticipate or render obvious that
“the second underfill covers an outer portion of a first side of the package board and an inner portion of the stiffener”
in combination with all other limitations in the claim as claimed and defined by applicant.
Although the prior art of Wang cited above in the rejection of claim 18 shows in Fig. 17 an arrangement in which the second underfill 292 covers an outer portion of a first side (top) of the package board 200 and an inner portion of the stiffener 294, Wang provides no particular reason or motivation for this arrangement.
In the examiner’s view, in light of the prior art thus far found from searching or provided by the applicant in the IDS, it would not be obvious to further modify Lee’s semiconductor package 100 (Figs. 17A and 17B), after the modification described in the rejection of claim 19 above, to include the feature of the second underfill 86 extending outward to cover an inner portion of the stiffener 90.
Prior Art Made of Record and Not Relied Upon
Relevant to the rounded corners of claim 19:
US 2022/0189861 A1—see Fig. 5B and ¶[0048]
Relevant to “the second underfill covers an outer portion of a first side of the package board and an inner portion of the stiffener” in claim 18:
US 2024/0030076 A1—see Fig. 10
US 2024/0071949 A1—see Fig. 21
Relevant to the interposer having insulating layers comprising “a silicon material” or “a low dielectric constant (low-k) material having a dielectric constant lower than that of the silicon material” in claim 15:
US 2022/0068756 A1 (corresponding to KR 10-2022-0030551 A from the IDS)—see Fig. 2 and ¶[0037]: “The interlayer insulating film 220 may include, for example, but is not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride and a low-k material having a lower dielectric constant than silicon oxide” ¶[0037]
Relevant to “the first semiconductor chips comprise an ASIC (claim 12) and are “mounted at a center of the first side of the interposer” (claim 11):
US 2022/0319944 A1—see Fig. 1 and ¶[0090]
US 2022/0068881 A1—see Fig. 20 and ¶[0022, 0079]
US 2022/0068756 A1 (corresponding to KR 10-2022-0030551 A from the IDS)—see Fig. 13 and ¶[0040, 0042]
US 2022/0013474 A1 (from the IDS)—see Fig. 1 and ¶[0023]
US 2021/0384143 A1—see Fig. 1 and ¶[0044]
US 2022/0392844 A1—see Fig. 1 and ¶[0042]
The following references appear to teach all the features of claim 10:
US 2023/0386946 A1—see Fig. 12
US 2022/0367312 A1—see Fig. 1H
US 2023/0378036 A1—see Fig. 1B
US 2022/0367311 A1—see Fig. 1F
US 2024/0071847 A1—see Fig. 17
US 2024/0071890 A1—see Fig. 1A
US 2024/0063087 A1—see Fig. 1A
US 2024/0014115 A1—see Fig. 12
US 2024/0014147 A1—see Fig. 1A
US 2023/0386945 A1—see Fig. 15A
US 2023/0378092 A1—see Fig. 16A
US 2023/0378042 A1—see Fig. 2B
US 2023/0066752 A1—see Fig. 2A
US 2022/0310501 A1—see Fig. 21
US 2023/0064277 A1—see Fig. 3
US 2023/0048302 A1—see Fig. 1E
US 2022/0367314 A1—see Fig. 1F
US 2022/0328445 A1—see Fig. 2B
US 2022/0319944 A1—see Fig. 2
US 2022/0199577 A1—see Fig. 3
US 2022/0077039 A1—see Fig. 7
US 2022/0068756 A1 (corresponding to KR 10-2022-0030551 A from the IDS)—see Fig. 2
US 2022/0013496 A1—see Fig. 6
US 2021/0384143 A1—see Fig. 2
US 10,770,369 B2 (from the IDS)—see Fig. 1
US 2020/0006181 A1—Fig. 9B
US 2019/0051621 A1—Figs. 1 and 6
US 9,899,305 B1—see Fig. 1
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Adam J Mott whose telephone number is (571)272-2367. The examiner can normally be reached Mon-Fri 8:30AM-5:00PM EST.
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/A.J.M./ Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
1 In the broadest reasonable interpretation, since the claim does not state that there must be “exactly two first semiconductor chips”, the four chips 50A satisfy the claimed requirement that there must be two first semiconductor chips mounted at a center of the interposer.
2 In the broadest reasonable interpretation, since the claim does not state that there must be “exactly two first semiconductor chips”, the four chips 50A satisfy the claimed requirement that there must be two first semiconductor chips mounted at a center of the interposer.
3 See the rejection of claim 16 above for a detailed explanation of the three underlined “between” statements based on Fig. 17B and ¶[0061].
4 The applicant may wish to amend claim 19 to be more specific about the location of the “at least one rounded side surface”. For instance, to describe a feature of the embodiment of Figs. 16a–16b, it could be stated that “at least one peripheral edge of the second side of the interposer is a rounded edge in a cross-sectional view, wherein the rounded edge provides a curved transition from the second side of the interposer to a sidewall of the interposer”.
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