Prosecution Insights
Last updated: July 17, 2026
Application No. 18/334,188

PLUGGABLE INTERCONNECTS USING GLASS CORES OF INTEGRATED CIRCUIT PACKAGE SUBSTRATES

Non-Final OA §102§103
Filed
Jun 13, 2023
Examiner
PHAM, LONG
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
1 (Non-Final)
92%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allowance Rate
1515 granted / 1655 resolved
+23.5% vs TC avg
Moderate +6% lift
Without
With
+5.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
38 currently pending
Career history
1688
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
56.5%
+16.5% vs TC avg
§102
24.1%
-15.9% vs TC avg
§112
9.4%
-30.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1655 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of claims 1-7, 9-14, and 16-20 in the reply filed on 4/13/26 is acknowledged. With respect to species restriction, examiner agreed with the election of species, 1, 2, and 4 of figs. 1-5 and 8. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 2, 3, 4, 5, 6, and 9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Han et al. (US pub 2023008928). With respect to claim 1, Han et al. teach an apparatus comprising (see figs. 1-18, particularly fig. 1 and fig. 17 stage IV and associated text): a semiconductor die 106, 112, 114; a substrate 108, 400, 600, 800, 1000 including a glass core 1608; and a pluggable interconnect including a portion of the glass core, the pluggable interconnect including a transmission line 1610,1622 extending along the portion of the glass core. With respect to claim 2, Han et al. teach the substrate includes a first build-up region 1620 (upper) on a first side of the glass core and a second build-up region 1620 (lower) on a second side of the glass core, the pluggable interconnect protruding beyond a lateral edge of at least one of the first build- up region or the second build-up region. See fig. 17 state IV and associated text. With respect to claim 3, Han et al. teach the portion of the glass core associated with the pluggable interconnect is exposed to an environment external to the apparatus. See fig. 17 stage IV and associated text. With respect to claim 4, Han et al. teach the transmission line extends along an exterior surface the glass core. See fig. 17 state IV and associated text. With respect to claim 5, Han et al. teach the transmission line extends through an interior of the glass core in a direction substantially parallel to exterior surfaces of the glass core. See fig. 17 stage IV and associated text. With respect to claim 6, Han et al. teach the glass core includes a first glass layer (left 1608) and a second glass layer (right 1608), the transmission line between the first and second glass layers. See fig. 17 stage IV and associated text. With respect to claim 9, Han et al. teach the transmission line is one of a plurality of transmission lines included in the pluggable interconnect. See fig. 17 stage IV and associated text. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Han et al. (US pub 2023008928) in combination with Crane, Jr. et al. (US pat 7123465). With respect to claim 10, Han et al. fail to teach providing a socket to receive the pluggable interconnect. See claim 20. Crane, Jr. et al. teach proving a socket to receive a pluggable interconnect to allow electrical interconnections of devices or components. See claim 20. However, It would have been obvious to one of ordinary skill in the art of making semiconductor devices to incorporate the teaching of Crane, Jr. et al. Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Han et al. (US pub 2023008928) in combination with Crane, Jr. et al. (US pat 7123465). With respect to claim 18, Han et al. teach an apparatus comprising (see figs. 1-18, particularly fig. 1 and fig. 17 stage IV and associated text): means for supporting 108, 400, 600, 800, 1000 a semiconductor die 106, 112,114; means for strengthening (glass core) the means for supporting, the means for strengthening including means for a plug connector 1610, 1622; and means for transmitting 1610, 1622 a signal within the means for inserting. Han et al. fail to teach providing a socket to receive the pluggable interconnect. See claim 20. Crane, Jr. et al. teach proving a socket to receive a pluggable interconnect to allow electrical interconnections of devices or components. See claim 20. However, It would have been obvious to one of ordinary skill in the art of making semiconductor devices to incorporate the teaching of Crane, Jr. et al. With respect to claim 19, Han et al. in combination with Crane, Jr. et al. teach means for communicatively coupling the means for transmitting with a transmission line in the plug connector. See above rejection. With respect to claim 20, Han et al. in combination with Crane, Jr. et al. teach means for aligning (this is inherent or mentally, plug has to be aligned to be inserted into the socket) the means for inserting with the plug connector. See above rejection. Allowable Subject Matter Claims 7, 11-12, 16-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Examiner’s Cited References The cited references generally show the similar or related structure a substrate having a pluggable interconnect, a glass core, and a connector as presently claimed by applicant. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to LONG PHAM whose telephone number is (571)272-1714. The examiner can normally be reached Mon-Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. LONG . PHAM Examiner Art Unit 2823 /LONG PHAM/Primary Examiner, Art Unit 2897
Read full office action

Prosecution Timeline

Jun 13, 2023
Application Filed
Oct 18, 2023
Response after Non-Final Action
Jun 16, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12685219
PACKAGE COMPRISING A CHIPLET LOCATED BETWEEN AN INTEGRATED DEVICE AND A METALLIZATION PORTION
3y 10m to grant Granted Jul 14, 2026
Patent 12685214
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Patent 12685213
SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR PACKAGE
3y 2m to grant Granted Jul 14, 2026
Patent 12685233
THREE-DIMENSIONAL STACKING SEMICONDUCTOR ASSEMBLIES WITH NEAR ZERO BOND LINE THICKNESS
2y 0m to grant Granted Jul 14, 2026
Patent 12677686
Electronic Package with Components Mounted at Two Sides of a Layer Stack
3y 9m to grant Granted Jul 07, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
92%
Grant Probability
97%
With Interview (+5.5%)
2y 3m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1655 resolved cases by this examiner. Grant probability derived from career allowance rate.

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