Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/04/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 6-19, 21, and 25-29 are rejected under 35 U.S.C. 103 as being unpatentable over Trivedi et al US 20210184001 A1 and further in view of Fukuzaki US 20200303375 A1. Trivedi et al will be referenced to as Trivedi henceforth.
Regarding Claim 1,
Trivedi teaches:
““An apparatus comprising a semiconductor device wherein the semiconductor device comprises ([0015], FIGs. 1A-B, 2A-3D, FIG. 5L: The present invention may be used with some of the described aspects. One of ordinary skill in the art would consider using aspects from different embodiments.): a first gate structure (fin 508A, [0080], FIG. 5L) including a first set of channels disposed along a first direction (first nanoribbons 510A, [0080], FIG. 5L: the first direction is vertical.) through a first gate metal (gate electrode 530 (belonging to 508A), [0087], FIG. 5L), and a first set of gate dielectrics disposed between the first set of channels and the first gate metal (gate dielectric 515-A, FIG. 5L), wherein the first set of gate dielectrics each have a first thickness ([0086], FIG. 5L: 515A and 515B have different thicknesses in FIG. 5L); and
a second gate structure (second fin 508-B, [0080], FIG. 5L) including a second set of channels (second nanoribbons 510B, [0080], FIG. 5L) disposed along the first direction through a second gate metal (gate electrode 530 (belonging to 508B), [0087], FIG. 5L), and a second set of gate dielectrics (gate dielectrics 515B, [0084]) disposed between the second set of channels and the second gate metal (FIG. 5L), wherein the second set of gate dielectrics each have a second thickness ([0086], FIG. 5L: 515A and 515B have different thicknesses in FIG. 5L.), wherein the second set of gate dielectrics each have at least one additional dielectric layer than the first set of gate dielectrics ([0040], [0043], [0086], FIG. 2B-3D, FIG. 5L: The dielectric layer of 515A is formed with a single oxidation process without additional steps unlike 515B. The second dielectric layer of the B device may allow for a higher dielectric constant without significantly increasing the amount of dielectric material. One of ordinary skill in the art would find this beneficial because using less material leads to a more compact device leading to increased computational power.), wherein the at least one additional dielectric layer is a different material than other dielectric layers of the second set of gate dielectrics ([0043], FIG. 2B-3D: The first dielectric layer, 3151, may be SiO2. The second dielectric layer, 3152 may be ZrO2.).wherein the second thickness is greater than the first thickness ([0086], FIG. 5L: 515B is furthermore clearly shown to be thicker than 515A in FIG. 5L.), [[and]] wherein the second set of channels is less in number than the first set of channels (FIG. 5L: 508B has 2 channels. 508A has 4 channels) wherein the second set of gate dielectrics each comprise: an interfacial oxide layer ([0043], FIG. 2B-3D: The first dielectric layer, 3151, may be SiO2 which is in direct contact with the channel.);
a high dielectric constant (high-K) dielectric ([0043], FIG. 2B-3D: The second dielectric layer, 3152 may be ZrO2. ZrO2 has a high dielectric constant.);.”
Trivedi doesn’t substantively teach:
“and a middle dielectric layer disposed between the interfacial oxide layer and the high-K dielectric, and wherein the first set of gate dielectrics each comprise: the interfacial oxide layer; and the high-K dielectric”
However, Fukuzaki teaches:
“and a middle dielectric layer disposed between the interfacial oxide layer and the high-K dielectric (Fukuzaki: insulating film 24, [0160],[0164], FIG. 11B-13), and wherein the first set of gate dielectrics each comprise: the interfacial oxide layer; and
the high-K dielectric (Fukuzaki: [0139], [0174]: transistor 10 contains insulating films 13 and 15. 13 contains SiO2, which interfaces with channel structure unit 11, and 15 HfO2, which is a high k dielectric. Transistor 20 contains 23 and 25. 23 contains SiO2, which interfaces with semiconductor layer 52, and 15 HfO2, which is a high k dielectric.).”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Trivedi is modifiable in view of Fukuzaki.
This is because the invention of Fukuzaki teaches that an insulating layer formed by thermal oxidation may have low interface trap density and improved noise performance (Fukuzaki, [0164]). One of ordinary skill in the art would recognize this as an advantage because noise may cause computational errors in a transistor which one of ordinary skill in the art wants to minimize.
Further, the inclusion of a high-k dielectric may allow for a higher dielectric constant without significantly increasing the amount of dielectric material. One of ordinary skill in the art would find this beneficial because using less material leads to a more compact device leading to increased computational power.
Regarding Claim 2,
Trivedi/Fukuzaki teaches:
“The apparatus of claim 1, wherein the first thickness of the first set of gate dielectrics is in a range of 0.8 to 1.5 nanometers (nm) (Trivedi: [0023], FIG. 1A-B: the first dielectric may have a thickness of less than 3nm. The ranges overlap and no criticality has been demonstrated. See MPEP 2144.05.), and wherein the second thickness of the second set of gate dielectrics is in a range of 2.5 to 3.5 nm (Trivedi: [0023], FIG. 1A-B: the second thickness may be 3nm or greater.).”
Regarding Claim 6,
Trivedi/Fukuzaki teaches:
“The apparatus of claim 1, wherein a second distance between channels of the second set of channels is greater than a first distance between channels of the first set of channels (Trivedi: [0024], Annotated FIG. 5L #1).”
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638
992
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Greyscale
Annotated FIG. 5L #1
Regarding Claim 7,
Trivedi/Fukuzaki teaches:
“The apparatus of claim 6, wherein the first distance is in a range of 8 to 12 nanometers (nm) (Trivedi: [0024], FIG. 5J: the spacing SA may be approximately 8 nm.), and wherein the second distance is in a range of 20 to 28 nm (Trivedi: [0024]: The spacing SB may be an integer multiple of the first spacing SA. For example, SB
≈
3*SA. For SA
≈
8 then SB
≈
24 nm.).”
Regarding Claim 8,
Trivedi/Fukuzaki teaches:
“The apparatus of claim 6, wherein the first distance is in a range of 8 to 12 nanometers (nm) (Trivedi: [0024]: the spacing SA may be approximately 8 nm.), and wherein the second distance is in a range of 12 to 18 nm (Trivedi: [0024]: The spacing SB may be an integer multiple of the first spacing SA. For example, SB
≈
2*SA. For SA
≈
8 then SB
≈
16 nm.).”
Regarding Claim 9,
Trivedi/Fukuzaki teaches:
“The apparatus of claim 1, wherein the first gate structure and the second gate structure are disposed on a substrate (Trivedi: substrate 506, [0070], FIG. 5L).”
Regarding Claim 10,
Trivedi/Fukuzaki teaches:
“The apparatus of claim 1, wherein a first channel of the first set of channels and a second channel of the second set of channels are coplanar along the first direction (Trivedi: [0025]: the bottommost nanosheets of the first and second channel sets may be coplanar in the vertical direction given that the bottom surfaces of these nanoribbons may be coplanar.).”
Regarding Claim 11,
Trivedi/Fukuzaki teaches:
“The apparatus of claim 1, wherein the first set of channels and the second set of channels are nanosheets (Trivedi: [0080]: nanoribbons are the same as nanosheets.). ”
Regarding Claim 12,
Trivedi/Fukuzaki teaches:
“The apparatus of claim 1, wherein the first gate structure is in a first region of the semiconductor device and the second gate structure is in a second region of the semiconductor device (Trivedi: FIG. 5L: 508B is on the left region of the device 500 and 508A is on the right region of device 500.).”
Regarding Claim 13,
Trivedi/Fukuzaki teaches:
“The apparatus of claim 12, further comprising: a first source/drain structure disposed on opposite sides of the first gate structure coupled to the first set of channels (Trivedi: source/drain regions 520 (belonging to 508A), [0082]); and
a second source/drain structure disposed on opposite sides of the second gate structure coupled to the second set of channels (Trivedi: source/drain regions 520 (belonging to 508B), [0082]).”
Regarding Claim 14,
Trivedi/Fukuzaki teaches:
“The apparatus of claim 13, wherein the first gate structure and the first source/drain structure are part of a first gate-all-around (GAA) device in the first region (Trivedi: [0087], FIG. 5L) and the second gate structure and the second source/drain structure are part of a second GAA device in the second region (Trivedi: [0087], FIG. 5L: 530 wraps around each of the nanoribbons 510 to form a GAA device.).”
Regarding Claim 15,
Trivedi/Fukuzaki teaches:
“The apparatus of claim 1, wherein the first set of channels has twice a number of channels as the second set of channels (Trivedi: FIG. 5L: 508B has 2 channels. 508A has 4 channels).”
Regarding Claim 16,
Trivedi/Fukuzaki teaches:
“The apparatus of claim 1, wherein each channel of the second set of channels is coplanar in the first direction with a corresponding channel of the first set of channels (Trivedi: annotated FIG. 5L #2: the portions of the second channels surrounding the illustrated lines are each coplanar with a first channel.).”
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748
1204
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Greyscale
Annotated FIG. 5L #2
Regarding Claim 17,
Trivedi/Fukuzaki teaches:
“The apparatus of claim 1, wherein at least one channel of the second set of channels is not coplanar in the first direction with any channel of the first set of channels (Trivedi: [0025]: One or more of the second nanoribbons may be misaligned with the first nanoribbons.).”
Regarding Claim 18,
Trivedi/Fukuzaki teaches:
“The apparatus of claim 1, wherein the apparatus comprises at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of Things (IoT) device, a laptop computer, a server, an access point, a base station, or a device in an automotive vehicle (Trivedi: FIG. 6: an embodiment of the disclosure may be included in a computing device with a communication chip. A computing device with a communication chip may be considered a communication device.). ”
Regarding Claim 19,
Trivedi/Fukuzaki teaches:
“A method of manufacturing a semiconductor device, comprising(Trivedi: [0015], FIGs. 1A-B, 2A-3D, FIG. 5L: The present invention may be used with some of the described aspects. One of ordinary skill in the art would consider using aspects from different embodiments.): forming a first gate structure (Trivedi: fin 508A, [0080], FIG. 5L) including a first set of channels disposed along a first direction (Trivedi: first nanoribbons 510A, [0080], FIG. 5L: the first direction is vertical.) through a first gate metal (Trivedi: gate electrode 530 (belonging to 508A), [0087], FIGs. 5I-5L ), and a first set of gate dielectrics disposed between the first set of channels and the first gate metal (Trivedi: gate dielectric 515-A, FIG. 5L), wherein the first set of gate dielectrics each have a first thickness (Trivedi: [0086], FIG. 5L: 515A and 515B have different thicknesses in FIG. 5L); and
forming a second gate structure (Trivedi: second fin 508-B, [0080], FIG. 5L) including a second set of channels (Trivedi: second nanoribbons 510B, [0080], FIG. 5L) disposed along the first direction through a second gate metal (Trivedi: gate electrode 530 (belonging to 508A), [0087], FIGs. 5I-5L ), and a second set of gate dielectrics (Trivedi: gate dielectrics 515B, [0084]) disposed between the second set of channels and the second gate metal (Trivedi: FIG. 5L), wherein the second set of gate dielectrics each have a second thickness (Trivedi: [0086], FIG. 5L: 515A and 515B have different thicknesses in FIG. 5L.), wherein the second thickness is greater than the first thickness (Trivedi: [0086], FIG. 5L: 515B is furthermore clearly shown to be thicker than 515A in FIG. 5L.), and wherein the second set of channels is less in number than the first set of channels (Trivedi: FIG. 5L: 508B has 2 channels. 508A has 4 channels) wherein the second set of gate dielectrics each have at least one additional dielectric layer than the first set of gate dielectrics (Trivedi: [0040], [0043], [0086], FIG. 2B-3D, FIG. 5L: The dielectric layer of 515A is formed with a single oxidation process without additional steps unlike 515B. The second dielectric layer of the B device may allow for a higher dielectric constant without significantly increasing the amount of dielectric material. One of ordinary skill in the art would find this beneficial because using less material leads to a more compact device leading to increased computational power.), wherein the at least one additional dielectric layer is a different material than other dielectric layers of the second set of gate dielectrics (Trivedi: [0043], FIG. 2B-3D: The first dielectric layer, 3151, may be SiO2. The second dielectric layer, 3152 may be ZrO2.) wherein forming the second set of gate dielectrics comprises: forming an interfacial oxide layer in a second region (Trivedi: [0043], FIG. 2B-3D, FIG. 5K-5L: The first dielectric layer, 3151, may be SiO2 which is in direct contact with the channel.);
forming a high dielectric constant (high-K) dielectric (Trivedi: [0043], FIG. 2B-3D: The second dielectric layer, 3152 may be ZrO2. ZrO2 has a high dielectric constant.) in the second region (Trivedi: FIG. 5K-5L);
and forming a middle dielectric layer disposed between the interfacial oxide layer and the high-K dielectric in the second region (Fukuzaki: insulating film 24, [0160],[0164], FIG. 11B-13), and wherein forming the first set of gate dielectrics comprises: forming the interfacial oxide layer in a first region; and
forming the high-K dielectric in the first region (Fukuzaki: [0139], [0174]: transistor 10 contains insulating films 13 and 15. 13 contains SiO2, which interfaces with channel structure unit 11, and 15 HfO2, which is a high k dielectric. Transistor 20 contains 23 and 25. 23 contains SiO2, which interfaces with semiconductor layer 52, and 15 HfO2, which is a high k dielectric.).”
Regarding Claim 21,
Trivedi/Fukuzaki teaches:
“The method of claim 19, further comprising processing a wafer for forming at least part of the semiconductor device (Trivedi: wafer, [0020]), wherein processing the wafer comprises: forming a first plurality of nanosheet layers in a first region corresponding to the first set of channels (Trivedi: 510A, [0080], FIG. 5I);
forming a first plurality of sacrificial gate layers disposed in an alternating layer pattern with the first plurality of nanosheet layers (Trivedi: sacrificial layers 537, [0080], FIG. 5I);
forming a second plurality of nanosheet layers in a second region corresponding to the second set of channels (Trivedi: 510B, [0080], FIG. 5I); and
forming a second plurality of sacrificial gate layers disposed in an alternating layer pattern with the second plurality of nanosheet layers (Trivedi: sacrificial layers 537, [0080], FIG. 5I).”
Regarding Claim 25,
Trivedi/Fukuzaki teaches:
“The method of claim 19, wherein a second distance between channels of the second set of channels is greater than a first distance between channels of the first set of channels (Trivedi: [0024], Annotated FIG. 5L #1).”
Regarding Claim 26,
Trivedi/Fukuzaki teaches:
“The method of claim 19, wherein the first set of channels and the second set of channels are nanosheets (Trivedi: [0080]: nanoribbons are the same as nanosheets.).”
Regarding Claim 27,
Trivedi/Fukuzaki teaches:
“The method of claim 19, wherein the first gate structure is in a first region of the semiconductor device and the second gate structure is in a second region of the semiconductor device (Trivedi: FIG. 5L: 508B is on the left region of the device 500 and 508A is on the right portion of device 500.).”
Regarding Claim 28,
Trivedi/Fukuzaki teaches:
“The method of claim 27, further comprising: forming a first source/drain structure disposed on opposite sides of the first gate structure coupled to the first set of channels (Trivedi: source/drain regions 520 (belonging to 508A),[0082]); and
forming a second source/drain structure disposed on opposite sides of the second gate structure coupled to the second set of channels (Trivedi: source/drain regions 520 (belonging to 508B), [0082]).”
Regarding Claim 29,
Trivedi/Fukuzaki teaches:
“The method of claim 28, wherein the first gate structure and the first source/drain structure are part of a first gate-all-around (GAA) device in the first region (Trivedi: [0087], FIG. 5L)and the second gate structure and the second source/drain structure are part of a second GAA device in the second region (Trivedi: [0087], FIG. 5L: 530 wraps around each of the nanoribbons 510 to form a GAA device.).”
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Trivedi as applied to claims 1-2, 6-19, 21, and 25-29 above, and further in view of Cheng et al US 20180197784 A1. Cheng et al will be referenced to as Cheng henceforth.
Regarding Claim 20,
Trivedi/Fukuzaki teaches:
“The method of claim 19, further comprising processing a wafer for forming at least part of the semiconductor device, wherein processing the wafer comprises: forming a first plurality of nanosheet layers (Trivedi: [0080], FIG. 5I);
forming a first plurality of sacrificial gate layers disposed in an alternating layer pattern with the first plurality of nanosheet layers (Trivedi: sacrificial layers 537, [0080], FIG. 5I);”
Trivedi/Fukuzaki doesn’t substantially teach:
“and infusing at least one of the first plurality of nanosheet layers with germanium to form a sacrificial portion disposed between adjacent sacrificial gate layers of the first plurality of sacrificial gate layers (Cheng: doped layer 202, [0039], FIG. 2: 202 is a silicon layer doped with germanium ).”
However, Cheng teaches:
“and infusing at least one of the first plurality of nanosheet layers with germanium to form a sacrificial portion disposed between adjacent sacrificial gate layers of the first plurality of sacrificial gate layers (Cheng: doped layer 202, [0039], FIG. 2: 202 is a silicon layer doped with germanium ).”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Trivedi/Fukuzaki is modifiable in view of Cheng.
This is because by implanting a germanium dopant into a silicon layer in Trivedi, the silicon layer becomes easier to etch and may be etched concurrently with the sacrificial layers (Cheng: [0039]). By using this implantation method in the method of Trivedi, a masking step and etching step of the sacrificial layer along with a deposition step of the nanosheet may be replaced with a step of turning a nanosheet into a sacrificial layer to later be etched to make larger gaps between nanosheets. One of ordinary skill in the art would recognize this as an advantage because concurrently etching the sacrificial layers and a doped silicon layer provides the benefit of removing a process step which in turn reduces cost of making a device and the error rate in forming the device.
Response to Arguments
Applicant first substantively argues:
“However, Fukuzaki also teaches in [0164] that the channel structure units of the first
transistor have a structure different from the channel formation region of the second transistor, and the cross section of the channel formation region of the second transistor can be made larger than the cross section of the channel structure units of the first transistor. Therefore, when the channel structure units and the channel formation region are thermally oxidized to form the gate insulating film, the thick gate insulating film can be formed in the channel formation region of the second transistor while preventing the nanowire structure from becoming thinner. The different structures of the first transistor and the second transistor are also shown in Fig. 11B-13 of Fukuzaki.
The Office Action argued that the teaching in Fukuzaki can be applied to Trivedi by one of ordinary skill in the art. However, Trivedi only discloses transistors of the same structure, i.e., no two transistors of different structures; whereas Fukuzaki clearly indicates that forming the insulating layers require the channel structure units of the first transistor to have a structure different from the channel formation region of the second transistor. Therefore, Fukuzaki clearly teaches away from applying its insulating films to the transistor in Trivedi as Trivedi discloses only one type of transistor (i.e., the transistors in Trivedi are not of different structures). Therefore, one of ordinary skill in the art would not have been motivated to modify Trivedi with Fukuzaki.”
The Examiner doesn’t find this argument to be fully persuasive
This is because, as noted by the Applicant, the transistors of the invention of Trivedi have the same structure. That is, these transistors are both nanoribbon transistors. Because of this, one of ordinary skill in the art would recognize that the problems that arise in the invention of Fukuzaki, namely the thinning of nanowires when heating two transistors of different structures, does not apply to the invention of Trivedi which does not include nanowires and includes transistors of the same structure as cited by the Examiner. Further one of ordinary skill in the art would still recognize that an intermediate dielectric layer provides the benefit of reduced noise and lower interface trap density. One of ordinary skill in the art would also recognize that an annealing process would not damage the invention of Trivedi as the invention of Trivedi uses an annealing process.
Applicant further argues in substance:
“In addition to, or in alternative to, the above reason, claims 1 and 19 as amended is
patentable over Trivedi in view of Fukuzaki for the following reason as well. Fukuzaki teaches forming a middle dielectric layer by thermal oxidation (Fukuzaki [0164]) to improve noise performance and interface trap density, whereas Trivedi's FIG. 5L embodiment (cited for the channel count limitation) already uses thermal oxidation to form the gate dielectric at Trivedi [0086], leaving no motivation to add Fukuzaki's additional thermal oxidation layer. Applicant respectfully submits that the Examiner's rationale that adding a high-k dielectric allows for higher dielectric constant without increasing material is contradicted by the fact that both references already teach high-k dielectrics (Trivedi [0030], Fukuzaki [0139]), and one of ordinary skill would not have combined two thermal oxidation processes that would over- consume the nanoribbons, rendering the transistor in Trivedi to be of lower quality and defeating the purpose of both references.
The Examiner does not find this argument to be fully persuasive.
This is because Fukuzaki shows that a thermal oxidation treatment is used to form both dielectric layers 23 and 24 (Fukuzaki: [0158-0159], [0164]). Therefore, the Examiner does not believe that a second thermal oxidation process is redundant, but is instead a method step that results in the formation of an in-between dielectric layer which provides the benefit of improved noise performance. Further, one of ordinary skill in the art, seeing that dielectrics 515A and 515B of Trivedi are similarly formed by an oxidation process would find it obvious to combine the inventions of Trivedi and Fukuzaki. The Examiner is not convinced that two anneal processes would necessarily overconsume the nanoribbons of Trivedi as the Examiner does not find evidence in either Trivedi and Fukuzaki to support this claim. The Examiner agrees that both references already teach high-k dielectric layers. The Examiner noted the use of a high-k dielectric layer to make it clear that a combination of Trivedi and Fukuzaki is consistent with the use of a high-k dielectric layer.
Because the Examiner did not find Applicant’s arguments to be fully persuasive. The Examiner’s 103 rejections are maintained.
In the interest of compact prosecution, if the Applicant were to amend an independent claim with the following limitation in addition to the limitations of claim 13:
“wherein the first source/drain region does not laterally surround a bottommost channel of the first set of channels and the second source/drain region does not laterally surround a bottommost channel of the second set of channels ”
It would overcome the current rejections for claim 1. The Examiner is available for interview at Applicant’s convenience for discussion of claim amendments.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDRE XAVIER RAMIREZ whose telephone number is (571)272-2715. The examiner can normally be reached Monday - Friday 8:30 AM to 6:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALEXANDRE X RAMIREZ/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
Prosecution Insights