DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action responds to the Amendment filed 2 February 2026. By this amendment, claims 1-24 are amended. Claims 1-25 remain pending.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4 and 10-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bae et al (US Patent Application Publication 2022/0045003).
Regarding claim 1, Bae et al disclose a semiconductor structure comprising:
a plurality of first type of lines 460c in a first metal level with a first line width and a first height, wherein each line of the plurality of first type of lines has a wider top surface than a bottom surface [see Fig. 1A]; and
a second type of line in the first metal level with a second line width that is narrower than the first line width in the first metal level, wherein:
a single line of the second type of line is an only line separating adjacent first type of lines; and
the second type of line has the wider top surface than the bottom surface [see Fig. 1A].
Regarding claim 2, Bae et al disclose the semiconductor structure of claim 1, furthermore comprising:
a plurality of first vias 310, wherein each of the plurality of first vias connects a line selected from the group consisting of: (i) the plurality of first type of lines and (ii) the second type line, to a second backside metal level 160, wherein the first metal level is a first backside metal level [see Fig. 1A].
Regarding claim 3, Bae et al disclose the semiconductor structure of claim 2, furthermore wherein each of the plurality of first type of lines and the second type of line connect by a via of a plurality of second vias to a through-silicon via of a plurality of through-silicon vias [see Fig. 1A].
Regarding claim 4, Bae et al disclose the semiconductor structure of claim 2, furthermore comprising:
a third backside metal level includes a plurality of second backside first type of lines and second backside second type of line, wherein the second backside second type of line is between two adjacent lines of the plurality of second backside first type of lines; and
a plurality of third vias connecting: (i) the plurality of second backside first type of lines and (ii) the second backside second type of line, to the second backside metal level.
Regarding claim 10, Bae et al disclose the semiconductor structure of claim 2, furthermore wherein each of the plurality of first type of lines and the second type of line connect by a via of a plurality of second vias to a metal level that is closer to a backside of a semiconductor substrate than the first backside metal level [see Fig. 1A].
Regarding claim 11, Bae et al disclose a semiconductor structure comprising:
a plurality of first type of lines with a first line width in a first backside metal level, wherein each of the plurality of first type of lines have a wider top surface than a bottom surface; and
a second type of line in the first backside metal level with a second line width that is less than the first line width, wherein:
each of the second type of line is between adjacent first type of lines; and
a single line of the second type of line is an only line separating two adjacent first type of lines [see Fig. 1A].
Regarding claim 12, Bae et al disclose the semiconductor structure of claim 11, furthermore comprising:
a plurality of first vias connecting each of the plurality of first type of lines and the second type line to one of a plurality of through-silicon via, wherein the second type line with the wider top surface than the line bottom surface has a different height than the first type of lines [see Fig. 1A]; and
a plurality of second vias connecting each of the plurality of first type lines and the second type line to second backside metal level [see Fig. 1A].
Regarding claim 13, Bae et al disclose the semiconductor structure of claim 11, furthermore comprising:
a plurality of first vias connecting each of the plurality of first type of lines and the second type line to a second metal level closer a backside of a semiconductor substrate than the first metal level [see Fig. 1A]; and
a plurality of second vias connecting each of the plurality of first type lines and the second type line to a third backside metal level under the first backside metal level, wherein the second type has a top surface that is below a top surface of the plurality of the first type of lines [see Fig. 1A].
Allowable Subject Matter
Claims 5-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: regarding dependent claim 5, the prior art of record fails to teach or make reasonably obvious, in combination with the other claimed elements, wherein the second type line has a top surface that is above the top surface of the plurality of first type lines; regarding dependent claims 6 and 7, the prior art of record fails to teach or make reasonably obvious, in combination with the other claimed elements, wherein the second type line has a top surface that is level with a bottom surface of the plurality of first type of lines; regarding dependent claim 8, the prior art of record fails to teach or make reasonably obvious, in combination with the other claimed elements, wherein the second type line has a top surface below a top surface of the plurality of first type of lines and above a bottom surface of the plurality of first type of lines; and regarding dependent claim 9, the prior art of record fails to teach or make reasonably obvious, in combination with the other claimed elements, wherein each of the more than one second type line has a different height.
Claims 14-25 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding independent claim 14, and claims 15-20 which depend therefrom, and as previously noted in the Non-Final Rejection dated 17 November 2025, the prior art of record fails to teach or make reasonably obvious, in combination with the other claimed elements, wherein the second type line has a second line width that is wider than the first line width, and wherein each of the second type line is between adjacent first type of lines.
Regarding independent claim 21, and claims 22 and 23 which depend therefrom, the prior art of record fails to teach or make reasonably obvious, in combination with the other claimed elements, both wherein a single line of the second type of line is an only line separating two adjacent first type of lines of the plurality of first type of lines, and a backside second type of line in the first backside metal level with a fourth line width that is narrower than the third line width.
Regarding independent claim 24, and claim 25 which depends therefrom, the prior art of record fails to teach or make reasonably obvious, in combination with the other claimed elements, wherein the third trench is etched between the two first type of lines using a damascene process, specifically wherein this etching occurs subsequent to depositing the metal material in the first two trenches.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-4 and 10-13 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLLEEN E SNOW whose telephone number is (571)272-8603. The examiner can normally be reached M-W, 8am-4:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale E Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/C.E.S./Examiner, Art Unit 2899 /VICTOR A MANDALA/Primary Examiner, Art Unit 2899