Prosecution Insights
Last updated: April 19, 2026
Application No. 18/334,578

SEMICONDUCTOR PACKAGE

Non-Final OA §103§112
Filed
Jun 14, 2023
Examiner
PARTHASARATHY, ROHIT
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
91%
Grant Probability
Favorable
1-2
OA Rounds
3y 4m
To Grant
99%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allow Rate
21 granted / 23 resolved
+23.3% vs TC avg
Moderate +13% lift
Without
With
+13.3%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
31 currently pending
Career history
54
Total Applications
across all art units

Statute-Specific Performance

§103
56.6%
+16.6% vs TC avg
§102
24.3%
-15.7% vs TC avg
§112
17.6%
-22.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 23 resolved cases

Office Action

§103 §112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant's election with traverse of Genus B, Species B4 in the reply filed on 12/17/2025 is acknowledged. The traversal is on the ground(s) that Claim 20, which Applicant indicates as corresponding to an elected species, contains features of both Species B3 and B4. Since Applicant contends that Claim 20 should be examined, Applicant argues that Claim 10, which includes the TIM, should also be examined. This is not found persuasive for the following reasons: First, as disclosed in the specification and drawings, and pointed out in the Restriction, Figs. 17 and 18 disclose distinct embodiments. In the embodiment of Fig. 17 (labelled 20c), the package includes a TIM layer, and a plate, but no mention is made of the coefficient of thermal expansion of the plate, or of the relationship between the coefficient of thermal expansion of the plate and the stiffeners. Fig. 18 (labelled 20d) on the other hand, does not include a TIM layer, but does disclose a relationship between the coefficient of thermal expansion and the stiffeners. Presumably, Applicant had a reason for drawing this distinction using two separate embodiments, and Examiner separated these two embodiments on the basis of Applicants disclosure and drawings (without referencing the claims). Regarding Claim 20, in Examiner’s opinion, Applicant is mixing features from two distinct embodiments (Figs. 17 and 18). Leaving aside potential 112(b) issues for now, Examiner is removing this claim from examination, since it contains features drawn to an unelected species (the TIM of B3). Regarding Claim 10, since Examiner is not examining Claim 20, the argument that Claim 10 ought to be examined is moot. Furthermore, Claim 10 (and Claims 1-9) are all drawn to Genus A. Claim 1, for example, references a second hole accommodating the plurality of passive elements, as opposed to Claim 11, which references a first concave portion surrounding the plurality of passive elements. This difference is noted in the specification and in the drawings. In the specification, Para. [0055]0 notes that the first stiffener 500 may include a first hole 510 and a second hole 520. Fig. 4 shows the second hole 520. In contrast, Para. [0097], referencing Figs. 11-13, notes that the first stiffener 500a may include a first hole 510 and a first concave portion 530, where Fig. 13 shows the concave portion 530. Fig. 13 and Fig. 4 differ at least in that Fig. 4 only has the second hole and no concave portion, while Fig. 13 has the concave portion. These differences where referenced in the claims. In view of the above, Claims 1-10, 16-18 and 20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Species. In particular, as noted above, Claims 1-10 are drawn to Genus A, and Claim 20 is drawn to B3. The requirement is still deemed proper and is therefore made FINAL. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 14 recites the limitation "…and are not exposed to the outside…". There is insufficient antecedent basis for this limitation in the claim. Specifically, Examiner can find no mention of outside in Claim 11, or elsewhere in Claim 14. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 11, 12, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over US20150091132A1 (Kim) in view of US20230066053A1 (Gong). Regarding Claim 1, Kim discloses a package substrate (Fig. 2B, el. 202, Para. [0026]); a plurality of semiconductor chips mounted on the package substrate (Fig. 2B, el. 204, Para. [0026]), an interposer arranged between the package substrate and the plurality of semiconductor chips (Para. [0033]); a plurality of passive elements mounted on the package substrate and spaced apart from the interposer (Figs. 2A-3C, el. 206, Para. [0029]), a first stiffener (Figs. 2A-2B, el. 208, Para. [0026]) positioned on the package substrate (Fig. 2B) and including a first hole accommodating the interposer (see annotated Fig. 2B below) and a first concave portion surrounding the plurality of passive elements (Fig. 2A, el. 208b, Para. [0024]), wherein the first stiffener has a first coefficient of thermal expansion (Para. [0003]). PNG media_image1.png 537 647 media_image1.png Greyscale Kim does not disclose a second stiffener positioned on the first stiffener and including a third hole communicating with the first hole, wherein the second stiffener has a second coefficient of thermal expansion different from the first coefficient of thermal expansion. Gong discloses a stiffener (Fig. 3, el. 10, Para. [0052]) with two material layers (Fig. 3, els. 11 and 12, Para. [0052]) where the second layer sits over the first layer, forming a hole (Fig. 3), and where the two layers have different coefficients of thermal expansion (Para. [0052]). It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to add a second stiffener with a different coefficient of thermal expansion, as in Gong, to the stiffener disclosed by Kim. Doing so would have the benefit of controlling the warpage of the stiffener when the stiffener is heated (Gong, Para. [0052]). Regarding Claim 12, Kim in view of Gong discloses the semiconductor package of claim 11, wherein a sidewall defining the first hole is positioned between the interposer and the plurality of passive elements (see Kim, annotated Fig. 3E below), and a sidewall defining the first concave portion is spaced apart from the side surfaces of the plurality of passive elements (see Kim, annotated Fig. 3E below), and an upper wall defining the first concave portion is spaced apart from an upper surface of the plurality of passive elements (see Kim, annotated Fig. 3E below). PNG media_image2.png 432 726 media_image2.png Greyscale Regarding Claim 14, Kim in view of Gong discloses the semiconductor package of claim 11, wherein the plurality of passive elements are positioned between sidewalls of the first concave portion of the first stiffener (Kim, Fig. 3B, Para. [0029]), and are not exposed to the outside by an upper wall of the first concave portion (Kim, Fig. 3B), and the interposer and the plurality of semiconductor chips are exposed to the outside (Kim, Fig. 3E). Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Gong. Regarding Claim 15, Kim in view of Gong discloses the semiconductor package of claim 11. Gong further discloses that the first coefficient of thermal expansion is greater than the second coefficient of thermal expansion (Para. [0052]). Kim in view of Gong do not disclose that the substrate has a coefficient of thermal expansion that is greater than the first coefficient of thermal expansion. However, it would It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to optimize the CTEs of the substrate, first stiffener, and second stiffener such that the CTEs decrease (MPEP, 2144.05 II). As disclosed by Gong, this would have the benefit of allowing warpage control (Para. [0054]). Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Gong and US20160163657A1 (Hung) Regarding Claim 13, Kim in view of Gong discloses the semiconductor package of claim 12. Kim in view of Gong does not disclose a first underfill layer positioned between the package substrate and the interposer wherein the first underfill layer is in contact with the sidewall of the first hole without any contact with the plurality of passive elements. Hung discloses a semiconductor package (Fig. 3, el. 100, Para. [0022]) with an interposer (Fig. 1, el. 112, Para. [0023]), a plurality of semiconductor devices (Fig. 1, el. 110, Para. [0023]), a stiffener (Fig. 5, el. 120, Para. [0026], passive components (Fig. 5, el. 126, Para. [0030]), and an underfill layer (Fig. 4, el. 124, Para. [0030], where the underfill material is disposed between the package substrate and the interposer (Para. [0030]), is in contact with a sidewall of the stiffener (Fig. 4), and does not touch the passive components (Fig. 4). It would It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to include the underfill material as in Hung to the package disclosed by Kim in view of Gong. As disclosed by Hung, adding the underfill in the position shown by Hung can help adhere the stiffener to the substrate (Para. [0030]). Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Gong and US20110037167A1 (Iruvanti). Regarding Claim 19, Kim in view of Gong discloses the semiconductor package of claim 11. Gong further discloses that the first coefficient of thermal expansion is greater than the second coefficient of thermal expansion (Para. [0052]). Kim in view of Gong does not disclose a first plate positioned on the second stiffener to cover an upper surface of the second stiffener and the third hole, where the plate has a coefficient of thermal expansion that is smaller than the second coefficient of thermal expansion, and that the first coefficient of thermal expansion is greater than the coefficient of thermal expansion of the substrate. Iruvanti discloses a semiconductor package (Fig. 1, el. 100, Para. [0019]) that has a lid (Fig. 1, el. 130, Para. [0023]) that has a lower coefficient of thermal expansion than the substrate (Para. [0034]). It would It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to add a lid to the structure disclosed by Kim in view of Gong, the lid having a lower CTE than the second stiffener, and the first stiffener have a lower CTE than the substrate. As suggested by Iruvanti, having CTEs decreasing in order can lead to beneficial warpage effects when the temperature changes (Fig. 2, Para. [0034]). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROHIT PARTHASARATHY whose telephone number is (571)272-2572. The examiner can normally be reached Monday-Friday 8:30a-5p. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 5712707877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ROHIT PARTHASARATHY/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Jun 14, 2023
Application Filed
Jan 06, 2026
Non-Final Rejection — §103, §112
Feb 27, 2026
Examiner Interview Summary
Apr 08, 2026
Response Filed

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
91%
Grant Probability
99%
With Interview (+13.3%)
3y 4m
Median Time to Grant
Low
PTA Risk
Based on 23 resolved cases by this examiner. Grant probability derived from career allow rate.

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