DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to the amendments filed on 01/16/2026.
Applicant’s amendments filed 10/16/2026 have been fully considered and reviewed by the examiner. The examiner notes the amendment of claim 1.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 14 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention
Claim 14 recites “the DTI region” (lines 2 and 4). There is insufficient antecedent basis for this limitation in the claim because it is unclear whether “the DTI region” relates back to “a DTI region” recited in claim 13, “a first DTI region” recited in claim 1, “a second DTI region” recited in claim 1, or to set forth an additional DTI region.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 7-8, and 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0155023 to Edwards et al. (hereinafter Edwards) in view of Okamoto et al. (US 2024/0266351, hereinafter Okamoto) and Morii et al. (US 2015/0041960, hereinafter Morii).
With respect to claim 1, Edwards discloses a semiconductor device (e.g., an integrated circuit including a power transistor and a non-power transistor) (Edwards, Figs. 1, 3-4, ¶0030-¶0046) comprising:
a semiconductor substrate (113) (Edwards, Figs. 3-4, ¶0030, ¶0040) having an upper surface (115) and a back surface opposite to the upper surface;
a substrate region (e.g., a lower portion of the substrate 113) (Edwards, Figs. 3-4, ¶0040) included in the semiconductor substrate (113), the substrate region reaching the back surface;
a first semiconductor region (e.g., an upper portion of the substrate 113 for the power transistor 114) and a second semiconductor region (e.g., an upper portion of the substrate 113 for the non-power transistor 118), the first semiconductor region and the second semiconductor region being disposed at different positions on the substrate region;
a buried layer (e.g., NBL 208) (Edwards, Figs. 3-4, ¶0040) of the first conductivity type (e.g., n-type) formed on the first semiconductor region and the second semiconductor region, the buried layer (e.g., NBL 208) including a first portion (e.g., in the power transistor 114 region), a second portion (e.g., in the non-power transistor 118 region), and a third portion (e.g., under the doped region 111) located between the first portion and the second portion;
a third semiconductor region (e.g., PBL 212 for the power transistor 114) (Edwards, Figs. 3-4, ¶0040) of the second conductivity type (e.g., p-type) formed on the first portion of the buried layer;
a fourth semiconductor region (e.g., PBL 212 for the non-power transistor 118) of the second conductivity type (e.g., p-type) formed on the second portion of the buried layer;
a first transistor (114) (Edwards, Figs. 3-4, ¶0040) of the first conductivity type (e.g., n-type);
a second transistor (118) (Edwards, Figs. 3-4, ¶0041) formed in the fourth semiconductor region (e.g., PBL 212 for the non-power transistor 118);
a DTI region (252) (Edwards, Figs. 1, 3, ¶0042) formed of a first insulator buried in a first trench formed in the semiconductor substrate (113);
an interlayer dielectric film (266/268) (Edwards, Figs. 3-4, ¶0046) formed on the upper surface (115) of the semiconductor substrate (113) so as to cover the first transistor (114) and the second transistor (118); and
contact plugs (e.g., vias) (Edwards, Figs. 3-4, ¶0046) buried in the interlayer dielectric film (266/268),
wherein the semiconductor substrate (113) includes:
a fifth semiconductor region (e.g., n-doped deep trench region 111 and n-doped region 258) (Edwards, Figs. 1, 3-4, ¶0042-¶0043) of the first conductivity type (e.g., n-type) reaching the upper surface (115) from the third portion of the buried layer (208),
wherein a first contact plug (e.g., via connecting the n-type region 258/111 to the conductor 280) (Edwards, Figs. 3-4, ¶0042-¶0043, ¶0046) of the contact plugs is disposed on the fifth semiconductor region (258/111) and electrically connected to the fifth semiconductor region (258/111),
wherein, in plan view, the fifth semiconductor region (e.g., 258/111 of the isolation region 110) (Edwards, Fig. 3, ¶0039-¶0042) is interposed between the third semiconductor region (e.g., PBL 212 for the power transistor 114 on the left side of the isolation region 110 in Fig.3) and the fourth semiconductor region (e.g., PBL 212 for the non-power transistor 114 on the right side of the isolation region 110 in Fig.3).
Further, Edwards does not specifically disclose (1) a substrate region of the first conductivity type; a first semiconductor region of the first conductivity type and a second semiconductor region of the first conductivity type or a second conductivity type opposite to the first conductivity type; (2) a first DTI region formed of a first insulator buried in a first trench formed in the semiconductor substrate, the first DTI region surrounding the first portion of the buried layer, the third semiconductor region and the first transistor in plan view; a second DTI region formed of a second insulator buried in a second trench formed in the semiconductor substrate, the second DTI region surrounding the second portion of the buried layer, the fourth semiconductor region and the second transistor in plan view, wherein a bottom surface of the first DTI region is located in the first semiconductor region, wherein a bottom surface of the second DTI region is located in the second semiconductor region, and (3) wherein the fifth semiconductor region surrounds the third semiconductor region and the first DTI region in plan view.
Regarding (1), Okamoto teaches forming a semiconductor device (Okamoto, Fig. 1, ¶0001-¶0002, ¶0013, ¶0036-¶0046) on the n-type semiconductor substrate (SUB/DL) comprised of a silicon carbide (SiC) material and including a substrate region (SUB) of the first conductivity type (n-type), a first semiconductor region (e.g., n-type epitaxial layer DL for the power transistor in the first region ARU) of the first conductivity type (e.g., n-type), and a second semiconductor region (e.g., n-type epitaxial layer DL for the non-power PMOS/NMOS transistor in the second region ARC) of the first conductivity type (e.g., n-type), to provide a power device controlling a high power and a large current, and having excellent performance characteristics (e.g., low on-resistance, high-speed operation and high temperature characteristics).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Edwards by forming a semiconductor device on the n-type SiC semiconductor substrate as taught by Okamoto to have the semiconductor device, wherein a substrate region of the first conductivity type; a first semiconductor region of the first conductivity type and a second semiconductor region of the first conductivity type or a second conductivity type opposite to the first conductivity type, in order to provide a power device controlling a high power and a large current, and having excellent performance characteristics (e.g., low on-resistance, high-speed operation and high temperature characteristics) (Okamoto, ¶0001-¶0002, ¶0013, ¶0044-¶0046).
Regarding (2), Morii teaches forming a semiconductor device (Morii, Figs. 1-4, ¶0038-¶0050, ¶0053-¶0064) comprising a low-voltage transistor region (e.g., CMOS second transistor region) and a high-voltage transistor region (e.g., high-voltages MOS first transistor region) each surrounded in plan view by a deep trench isolation region (DTR) that includes a first DTR region formed of a first insulator buried in a first trench formed in the semiconductor substrate (PSB), the first DTI region surrounding the first portion (e.g., under the high-voltage transistor region) of the buried layer (NBL), the third semiconductor region and the first transistor in plan view; a second DTI region formed of a second insulator buried in a second trench formed in the semiconductor substrate, the second DTI region surrounding the second portion (e.g., under the low-voltage transistor region) of the buried layer (NBL), the fourth semiconductor region and the second transistor in plan view, wherein a bottom surface of the first DTI region is located in the first semiconductor region (e.g., a top portion of the substrate PSB in the high-voltage region), wherein a bottom surface of the second DTI region is located in the second semiconductor region (e.g., a top portion of the substrate PSB in the low-voltage region) (Morii, Figs. 1-4, ¶0061). In Morii, the first and second isolation regions (DTR) are formed to effectively electrically separate the high-voltage transistor region and the low-voltage transistor region from the outside regions.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Edwards by forming the first and second isolation regions (DTR) surrounding the high-voltage transistor region and the low-voltage transistor region, respectively, as taught by Morii to have the semiconductor device comprising: a first DTI region formed of a first insulator buried in a first trench formed in the semiconductor substrate, the first DTI region surrounding the first portion of the buried layer, the third semiconductor region and the first transistor in plan view; a second DTI region formed of a second insulator buried in a second trench formed in the semiconductor substrate, the second DTI region surrounding the second portion of the buried layer, the fourth semiconductor region and the second transistor in plan view, wherein a bottom surface of the first DTI region is located in the first semiconductor region, wherein a bottom surface of the second DTI region is located in the second semiconductor region, in order to provide effective electrical separation of the high-voltage transistor region and the low-voltage transistor region from the outside regions of the semiconductor substrate (Morii, ¶0038, ¶0040, ¶0061).
Regarding (3), Edwards teaches forming the isolation structure (110) including a fifth semiconductor region (e.g., n-doped deep trench region 111) (Edwards, Figs. 1, 3-4, ¶0030, ¶0042-¶0043) of the first conductivity type (e.g., n-type) on sidewalls of the deep isolation trench (252) and reaching the buried layer (208) of the first conductivity type (e.g., n-type), to enhance the isolation of the power transistor from other low-power components of the semiconductor device.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Edwards/Morii by forming the fifth semiconductor region on sidewalls of the first DTI region surrounding the power transistor, as taught by Edwards to have the semiconductor device, wherein the fifth semiconductor region surrounds the third semiconductor region and the first DTI region in plan view, in order to enhance the isolation of the power transistor from other low-power components of the semiconductor device (Edwards, ¶0030, ¶0042-¶0043).
Regarding claim 7, Edwards in view of Okamoto and Morii discloses the semiconductor device according to claim 1. Further, Edwards does not specifically disclose that the first transistor is a power switching element.
However, Okamoto teaches forming a semiconductor device (Okamoto, Fig. 1, ¶0001-¶0002, ¶0011, ¶0013, ¶0036-¶0046, ¶0073) on the n-type semiconductor substrate (SUB/DL), wherein SiC power transistor is configured as a high-speed switch.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Edwards/Okamoto/Morii by forming a semiconductor device on the n-type SiC semiconductor substrate as taught by Okamoto to have the semiconductor device, wherein the first transistor is a power switching element, in order to provide a power device controlling a high power and a large current, and having excellent performance characteristics (e.g., low on-resistance, high-speed operation and high temperature characteristics) (Okamoto, ¶0001-¶0002, ¶0013, ¶0044-¶0046).
Regarding claim 8, Edwards in view of Okamoto and Morii discloses the semiconductor device according to claim 1. Further, Edwards discloses the semiconductor device, wherein, in plan view, the fifth semiconductor region (e.g., isolation region 110 including the n-doped deep trench region 111) (Edwards, Figs. 1, 3, ¶0030, ¶0042) surrounds the third semiconductor region (e.g., PBL 212 for the power transistor 114).
Regarding claim 11, Edwards in view of Okamoto and Morii discloses the semiconductor device according to claim 1. Further, Edwards discloses the semiconductor device, wherein the semiconductor substrate (113) includes: a source region (122) (Edwards, Figs. 1, 3-4, ¶0040) of the first conductivity type (e.g., n+ -type) of the first transistor (114) and a drain region (138) of the first conductivity type (e.g., n+ -type) of the first transistor (114), the source region (122) and the drain region (138) being formed in the third semiconductor region (e.g., PBL 212 for the power transistor 114) and spaced apart from each other; a first well region (SNW 228) (Edwards, Figs. 1, 3-4, ¶0041) formed in the fourth semiconductor region (e.g., PBL 212 for the non-power transistor 118); and a second source region (232) of the second transistor (118) and a second drain region (236) of the second transistor (118), the second source region (232) and the second drain region (236) being formed in the first well region (SNW 228) and spaced apart from each other, wherein a first gate electrode (126) (Edwards, Figs. 1, 3-4, ¶0040) of the first transistor (114) is formed on the upper surface (115) of the semiconductor substrate (113) between the source region (122) and the drain region (138) via a gate dielectric film (224), and wherein a second gate electrode (240) (Edwards, Figs. 1, 3-4, ¶0041) of the second transistor (118) is formed on the upper surface (115) of the semiconductor substrate (113) between the second source region (232) and the second drain region (236) via a second gate dielectric film (244).
Regarding claim 12, Edwards in view of Okamoto and Morii discloses the semiconductor device according to claim 1. Further, Edwards discloses the semiconductor device, wherein a region (e.g., NBL 208) (Edwards, Figs. 1, 3-4, ¶0040, ¶0042) under the third semiconductor region (e.g., PBL 212 for the power transistor 114) and the fifth semiconductor region (111) in the semiconductor substrate is all the region of the first conductivity type (e.g., n-type region of the NBL 208).
Regarding claim 13, Edwards in view of Okamoto and Morii discloses the semiconductor device according to claim 1. Further, Edwards discloses the semiconductor device, wherein an STI region (220 and 248) (Edwards, Figs. 1, 3-4, ¶0040-¶0041) and a DTI region (252) (Edwards, Figs. 1, 3, ¶0042) deeper than the STI region (220/248) are formed in the semiconductor substrate (113).
Regarding claim 14, Edwards in view of Okamoto and Morii discloses the semiconductor device according to claim 1. Further, Edwards discloses the semiconductor device, wherein the DTI region (252) (Edwards, Figs. 1, 3-4, ¶0042) formed in the third semiconductor region (e.g., PBL 212 for the power transistor 114) penetrates through the third semiconductor region and the buried layer (208) and reaches the first semiconductor region (e.g., an upper portion of the substrate 113 for the power transistor 114), and wherein the DTI region (252) formed in the fourth semiconductor region (e.g., PBL 212 for the non-power transistor 118) penetrates through the fourth semiconductor region and the buried layer (208) and reaches the second semiconductor region (e.g., an upper portion of the substrate 113 for the non-power transistor 118).
Claims 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0155023 to Edwards in view of Okamoto (US 2024/0266351) and Morii (US 2015/0041960) as applied to claim 1, and further in view of Olofsson (US Patent No. 7,022,560).
Regarding claim 2, Edwards in view of Okamoto and Morii discloses the semiconductor device according to claim 1. Further, Edwards discloses the semiconductor device, wherein the first conductivity type is an n-type, wherein the first transistor (114) (Edwards, Fig. 3, ¶0040, ¶0045) is an n-channel type MISFET (e.g., n-channel metal-insulator-semiconductor), but does not specifically disclose that a potential higher than a potential of the third semiconductor region is supplied from the first contact plug to the fifth semiconductor region.
However, Olofsson teaches forming a high-voltage MOS transistor comprising a buried layer of the first conductivity type (11) and an isolation region including a contact region (25) of the first conductivity type for the buried layer (11) that reaches the upper surface of the semiconductor substrate (1) from the buried layer (11), wherein a positive voltage (+Vcc) is applied to the contact region (25) to improve isolation characteristics of the MOS structure.
Thus, Olofsson recognizes that a positive voltage applied to the isolation region including the contact region of the buried layer impacts isolation characteristics of the MOS structure. Thus, a voltage applied to the isolation region is a result-effective variable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, a voltage applied to the fifth semiconductor region that functions as an isolation region as Olofsson has identified a voltage applied to the isolation region as a result-effective variable. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at specific positive voltage applied to the isolation region including the fifth semiconductor region such that that a potential higher than a potential of the third semiconductor region is supplied from the first contact plug to the fifth semiconductor region, in order to improve isolation characteristics of the MOS structure as taught by Olofsson (Col. 5, lines 46-51) (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Edwards/Okamoto/Morii by optimizing voltage/potential applied to the isolation region as taught by Olofsson, wherein the isolation region includes the fifth semiconductor region to have the semiconductor device, wherein a potential higher than a potential of the third semiconductor region is supplied from the first contact plug to the fifth semiconductor region, in order to improve isolation characteristics of the MOS structure (Olofsson, Col. 5, lines 46-51).
Regarding claim 3, Edwards in view of Okamoto, Morii, and Olofsson discloses the semiconductor device according to claim 2. Further, Edwards does not specifically disclose that a positive potential is supplied from the first contact plug to the fifth semiconductor region.
However, Olofsson teaches forming a high-voltage MOS transistor comprising a buried layer of the first conductivity type (11) and an isolation region including a contact region (25) of the first conductivity type for the buried layer (11) that reaches the upper surface of the semiconductor substrate (1) from the buried layer (11), wherein a positive voltage (+Vcc) is applied to the contact region (25) to improve isolation characteristics of the MOS structure.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Edwards/Okamoto/Morii/ Olofsson by applying voltage/potential to the isolation region as taught by Olofsson, wherein the isolation region includes the fifth semiconductor region to have the semiconductor device, wherein a positive potential is supplied from the first contact plug to the fifth semiconductor region, in order to improve isolation characteristics of the MOS structure (Olofsson, Col. 5, lines 46-51).
Regarding claim 4, Edwards in view of Okamoto, Morii, and Olofsson discloses the semiconductor device according to claim 2. Further, Edwards discloses the semiconductor device, wherein the first transistor is an LDMOSFET (Edwards, Figs. 1, 3-4, ¶0040, ¶0045).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0155023 to Edwards in view of Okamoto (US 2024/0266351) and Morii (US 2015/0041960) as applied to claim 1, and further in view of Tanaka (US 2020/0177180).
Regarding claim 5, Edwards in view of Okamoto and Morii discloses the semiconductor device according to claim 1. Further, Edwards does not specifically disclose a power conversion circuit including a high-side transistor and a low-side transistor connected in series, wherein the first transistor is used as the low-side transistor in the power conversion circuit.
However, Tanaka teaches forming a power converter (60) (Tanaka, Fig. 1, ¶0001, ¶0011, ¶0015, ¶0038-¶0040, ¶0101) including a high-side transistor (S1) and a low-side transistor (S2) connected in series, wherein MOSFET transistor is used as the low-side transistor or the high-side transistor in the power conversion circuit (60). The power converter (60) is controlled by the semiconductor integrated circuit (50) which drives the power conversion circuit (60) and comprises silicon semiconductor material or a wide-bandgap semiconductor such as SiC or gallium nitride (GaN), to provide semiconductor integrated circuit with improved performance characteristics.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Edwards/Okamoto/Morii by forming a power converter as taught by Tanaka, wherein the MISFET transistor is used as the low-side transistor in the power conversion circuit to have the semiconductor device comprising: a power conversion circuit including a high-side transistor and a low-side transistor connected in series, wherein the first transistor is used as the low-side transistor in the power conversion circuit, in order to provide semiconductor integrated circuit with improved performance characteristics (Tanaka, ¶0001, ¶0011, ¶0015, ¶0038-¶0040, ¶0101).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0155023 to Edwards in view of Okamoto (US 2024/0266351) and Morii (US 2015/0041960) as applied to claim 1, and further in view of Meiser et al. (US 2018/0175846, hereinafter Meiser).
Regarding claim 6, Edwards in view of Okamoto and Morii discloses the semiconductor device according to claim 1. Further, Edwards does not specifically disclose that a withstand voltage of the first transistor is larger than a withstand voltage of the second transistor.
However, Meiser teaches forming an electronic circuit (Meiser, Fig. 1, ¶0001, ¶0025-¶0033) operating as an electronic switch and including a first transistor (T1) and a second transistor (T2) connected in series, wherein the first transistor (T1) has higher voltage blocking capability to withstand high voltage spikes than the second transistor (T2). A lower voltage blocking capability of the second transistor device (T2) is provided by a lower size of a semiconductor body of the second transistor (T2) as compared with the size of a semiconductor body of the first transistor (T1) having higher blocking capability (Meiser, Fig. 1, ¶0031).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Edwards/Okamoto/Morii by forming an electronic circuit including a first transistor and a second transistor connected in series as taught by Meiser, wherein the first transistor has size of a semiconductor body greater than that of the second transistor to have the semiconductor device, wherein a withstand voltage of the first transistor is larger than a withstand voltage of the second transistor, in order to provide an electronic switch with improved performance characteristics (Tanaka, ¶0001, ¶0025, ¶0031).
Claims 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0155023 to Edwards in view of Okamoto (US 2024/0266351) and Morii (US 2015/0041960) as applied to claim 1, and further in view of Huang et al. (US 2023/0078296, hereinafter Huang) and Matsudai et al. (US 2007/0034985, hereinafter Matsudai).
Regarding claim 9, Edwards in view of Okamoto and Morii discloses the semiconductor device according to claim 1. Further, Edwards does not specifically disclose that an impurity concentration of the buried layer is higher than an impurity concentration of each of the first semiconductor region and the substrate region.
However, Huang teaches forming a high-voltage semiconductor device (Huang, Fig. 2A, ¶0002, ¶0014-¶0015, ¶0018, ¶0020, ¶0036) on a substrate comprising silicon or silicon carbide material and including a lightly-doped n-type substrate region (101) under the n-type buried layer (102) and n-type ring-shaped wells (115) connected to the buried layer (102), to isolate the high-voltage semiconductor device having improved performance.
Further, Matsudai teaches forming a semiconductor device (Matsudai, Figs. 1-2, ¶0003, ¶0049-¶0053, ¶0058) comprising n+-type buried layer (2) serving as a low resistance layer on a substrate (e.g., N-sub) having higher impurity concentration than that of the substrate, to provide a lateral MOSFET device with improved performance characteristics.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Edwards/Okamoto/Morii by forming a high-voltage semiconductor device on a lightly-doped n-type substrate as taught by Huang, wherein the n+-type buried layer has higher impurity concentration than that of the substrate including an upper semiconductor region and the lower semiconductor region under the buried region as taught by Matsudai to have the semiconductor device, wherein an impurity concentration of the buried layer is higher than an impurity concentration of each of the first semiconductor region and the substrate region, in order to isolate the high-voltage semiconductor device including a lateral MOSFET device having improved performance (Huang, ¶0002, ¶0015, ¶0018, ¶0036; Matsudai, ¶0003, ¶0049, ¶0058).
Regarding claim 10, Edwards in view of Okamoto, Morii, Huang, and Matsudai discloses the semiconductor device according to claim 9. Further, Edwards does not specifically disclose that the impurity concentration of the first semiconductor region is higher than the impurity concentration of the substrate region.
However, Okamoto teaches the n-type semiconductor substrate (SUB/DL) comprised of a silicon carbide (SiC) material and including a substrate region (SUB) of the first conductivity type (n-type), a first semiconductor region (e.g., n-type epitaxial layer DL for the power transistor in the first region ARU) of the first conductivity type (e.g., n-type) (Okamoto, Fig. 1, ¶0001-¶0002, ¶0013, ¶0036-¶0046) having the n-type impurity concentration of 1e16 cm-3, to provide a power device controlling a high power and a large current, and having excellent performance characteristics (e.g., low on-resistance, high-speed operation and high temperature characteristics).
Further, Huang teaches forming a high-voltage semiconductor device (Huang, Fig. 2A, ¶0002, ¶0014-¶0015, ¶0018, ¶0020, ¶0036) on a substrate comprising silicon or silicon carbide material and including a lightly-doped n-type substrate region (101) under the n-type buried layer (102).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Edwards/Okamoto/Morii/ Huang /Matsudai by forming a high-voltage semiconductor device on the n-type substrate comprising the n-type epitaxial layer including a first semiconductor region as taught by Okamoto, wherein the n-type substrate is a lightly-doped n-type substrate as taught by Huang to have the semiconductor device, wherein the impurity concentration of the first semiconductor region is higher than the impurity concentration of the substrate region, in order to provide a power device controlling a high power and a large current, and having excellent performance characteristics (e.g., low on-resistance, high-speed operation and high temperature characteristics); and to isolate the high-voltage semiconductor device having improved performance (Okamoto, ¶0001-¶0002, ¶0013, ¶0044-¶0046; Huang, ¶0002, ¶0015, ¶0018, ¶0036).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0155023 to Edwards in view of Okamoto (US 2024/0266351) and Morii (US 2015/0041960) as applied to claim 1, and further in view of Ma et al. (US Patent No. 7,538,396, hereinafter Ma).
Regarding claim 15, Edwards in view of Okamoto and Morii discloses the semiconductor device according to claim 1. Further, Edwards discloses the semiconductor device, wherein the fifth semiconductor region (111) (Edwards, Figs. 3-4, ¶0042) covers a side surface of the third semiconductor region (e.g., PBL 212 for the power transistor 114) (Edwards, Figs. 3-4, ¶0040), but does not specifically disclose that the semiconductor substrate includes: a sixth semiconductor region of the first conductivity type covering a side surface of the fourth semiconductor region; and a seventh semiconductor region of the second conductivity type interposed between the fifth semiconductor region and the sixth semiconductor region, wherein the seventh semiconductor region penetrates through the buried layer and reaches the second semiconductor region, and wherein the second semiconductor region is of the second conductivity type.
However, Ma teaches forming a semiconductor device (Ma, Fig. 3, Col. 2, lines 8-14; Col. 4, lines 12-31; Col. 5, lines 34-65; Col. 6, lines 6-67; Col. 7, lines 1-18) comprising a first high-voltage transistor (A2) (Ma, Fig. 3, Col. 6, lines 10-18) and a second transistor (A1) on the semiconductor substrate (200) including a sixth semiconductor region (204n) of the first conductivity type (e.g., n-type) covering a side surface of the fourth semiconductor region (214p); and a seventh semiconductor region (216p/218p) of the second conductivity type (e.g., p-type) interposed between the fifth semiconductor region (302n) and the sixth semiconductor region (204n), wherein the seventh semiconductor region (216p/218p) penetrates through the buried layer (208n) and reaches the second semiconductor region (e.g., an upper portion of the substrate 200 including PBL 215p), and wherein the second semiconductor region (215p) is of the second conductivity type (e.g., p-type), to provide junction isolation structure to effectively isolate the semiconductor devices, and to meet high integration requirement by using n-type and p-type buried layers.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Edwards/Okamoto/Morii by forming junction isolation structure between the first and second semiconductor devices including the p-type semiconductor region between n-type regions (as a seventh semiconductor between the fifth and sixth n-type semiconductor regions) as taught by Ma, wherein the first semiconductor device includes the n-type buried layer and the second semiconductor device includes the p-type buried layer under the n-type buried layer as taught by Ma, and wherein the first and second semiconductor devices are formed on the n-type semiconductor substrate of Edwards/Okamoto to have the semiconductor device, wherein the semiconductor substrate includes: a sixth semiconductor region of the first conductivity type covering a side surface of the fourth semiconductor region; and a seventh semiconductor region of the second conductivity type interposed between the fifth semiconductor region and the sixth semiconductor region, wherein the seventh semiconductor region penetrates through the buried layer and reaches the second semiconductor region, and wherein the second semiconductor region is of the second conductivity type, in order to provide junction isolation structure to effectively isolate the semiconductor devices, and to meet high integration requirement by using n-type and p-type buried layers; and to provide a power device having excellent performance characteristics (Ma, Col. 2, lines 8-14; Col. 4, lines 12-31; Col. 5, lines 34-65; Col. 7, lines 7-18; Okamoto, ¶0001-¶0002, ¶0013, ¶0044-¶0046).
Response to Arguments
Applicant's arguments filed 01/16/2026 have been fully considered but they are not persuasive.
In response to Applicant’s argument that “[E]dwards along with the references cited in combination with Edwards fail to disclose or suggest the features of "wherein the fifth semiconductor region surrounds the third semiconductor region and the first DTI region in plan view", the examiner submits that newly discovered prior art by Morii teaches forming a first DTI region and a second DTI region surrounding the high-voltage transistor and the low-voltage transistor, the first portion and the second portion of the buried layer, respectively, as recited in the amended claim 1. Further, Edwards teaches the fifth semiconductor region surrounding high-voltage transistor including the third semiconductor region and the DTI region in plan view. Thus, a person of ordinary skill in the art would recognize that the combination Edwards/Morii would result in a semiconductor device comprising the fifth semiconductor region surrounding the third semiconductor region and the first DTI region in plan view, as required by the amended claim 1.
Thus, the above Applicant’s argument is not persuasive, and the rejection of claim 1 under 35 USC 103 over Edwards in view of Morii would be maintained.
Regarding dependent claims 2-15 which depend on the independent claim 1, the examiner respectfully submits that the applicant’s arguments with respect to dependent claims are not persuasive for the above reasons, thus, the rejections of the dependent claims are sustained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATALIA GONDARENKO whose telephone number is (571)272-2284. The examiner can normally be reached 9:30 AM-7:30 PM.
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891