DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 05/11/2026 has been entered.
Claim Objections
Claims 1-13 and 15 are objected to because of the following informalities:
Claim 1 recites “the third portion of he buried layer” (lines 19-20, page 3) which should be replaced with “the third portion of the buried layer”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 15 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 15 recites “a seventh semiconductor region of the p-type interposed between the fifth semiconductor region and the sixth semiconductor region, …wherein the seventh semiconductor region penetrates through the buried layer and reaches the second semiconductor region”. However, claim 1 recites “the fifth semiconductor region and the third portion of he buried layer are interposed between the first DTI region and the second DTI region”. The original specification does not describe an embodiment, wherein “a seventh semiconductor region of the p-type interposed between the fifth semiconductor region and the sixth semiconductor region, …wherein the seventh semiconductor region penetrates through the buried layer and reaches the second semiconductor region” and “the fifth semiconductor region and the third portion of he buried layer are interposed between the first DTI region and the second DTI region”. Specifically, the embodiment of Fig. 8 including the seventh semiconductor region (DP) penetrating through the buried layer (BL) does not include first DTI region and the second DTI. The Specification does not resolve ambiguity of the claim and that renders the claim indefinite.
Claim 8 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Claim 8 recites limitations “in plan view, the fifth semiconductor region surrounds the third semiconductor region” previously recited in claim 1 (lines 22-23, page 3). Thus, claim 8 fails to further limit the subject matter of the claim 1 upon which claim 8 depends.
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 8-9, 11-12, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0059689 to Shin in view of Morii et al. (US 2015/0041960, hereinafter Morii), Moen et al. (US 2018/0323187, hereinafter Moen), and Khemka et al. (US Patent No. 8,338,872, hereinafter Khemka).
With respect to claims 1 and 8, Shin discloses a semiconductor device (e.g., an integrated circuit including CMOS transistor and DMOS transistor) (Shin, Fig. 4, ¶0089-¶0095) comprising:
a semiconductor substrate (e.g., 100, N-type silicon substrate) (Shin, Fig. 4, ¶0092) having an upper surface and a back surface opposite to the upper surface;
a substrate region of an n-type (e.g., a lower portion of the N-type substrate 100 under the deep trenches 500) (Shin, Fig. 4, ¶0091-¶0092) included in the semiconductor substrate (100), the substrate region reaching the back surface;
a first semiconductor region (e.g., in a region 30, a portion of the N-type substrate 100 between the deep trenches 500) (Shin, Fig. 4, ¶0091-¶0093) of the n-type and a second semiconductor region (e.g., in a region 20, a portion of the N-type substrate 100 between the deep trenches 500) of the n-type, the first semiconductor region and the second semiconductor region being disposed at different positions (e.g., regions 30 and 20) on the substrate region;
a buried layer (e.g., N-type buried layer 102) (Shin, Fig. 4, ¶0093) of the n-type formed on the first semiconductor region (e.g., in the region 30) and the second semiconductor region (e.g., in the region 20), the buried layer (e.g., 102) including a first portion (e.g., in the region 30), a second portion (e.g., in the region 20);
a third semiconductor region (e.g., P-type region 104) (Shin, Fig. 4, ¶0094) of the p-type formed on the first portion (e.g., in the region 30) of the buried layer (102);
a fourth semiconductor region (e.g., P-type region 101/130) (Shin, Fig. 4, ¶0093) of the p-type formed on the second portion (e.g., in the region 20) of the buried layer (102);
a first source region (e.g., N+ source region) (Shin, Fig. 4, ¶0094) of the n-type formed in the third semiconductor region (e.g., in the region 30);
a first drain region (e.g., N+ drain region) (Shin, Fig. 4, ¶0094) of the n-type formed in the third semiconductor region (e.g., in the region 30);
a first transistor (e.g., EDMOS) including the first source region and the first drain region;
a second source region (e.g., N-type source region of the CMOS transistor) (Shin, Fig. 4, ¶0093) of the n-type formed in the fourth semiconductor region (101/130);
a second drain region (e.g., N-type drain region of the CMOS transistor) (Shin, Fig. 4, ¶0093) of the n-type formed in the fourth semiconductor region (101/130);
a second transistor (e.g., CMOS transistor in the P-type region/well 101/130) including the second source region and the second drain region;
a first DTI region (e.g., deep trench 500, on the right side and the left side of the region 30) (Shin, Fig. 4, ¶0091, ¶0094, ¶0110-¶0111) formed of a first insulator (400) buried in a first trench (500) formed in the semiconductor substrate (100), the first DTI region surrounding the first portion of the buried layer (102), the third semiconductor region (104) and the first transistor (e.g., EDMOS 30);
a second DTI region (e.g., deep trench 500, on the left side and the right side of the region 20) (Shin, Fig. 4, ¶0091, ¶0093, ¶0110-¶0111) formed of a second insulator (400) buried in a second trench formed in the semiconductor substrate (100), the second DTI region surrounding the second portion of the buried layer (102), the fourth semiconductor region (101/130) and the second transistor (e.g., CMOS transistor 20);
an interlayer dielectric film (400) (Shin, Fig. 4, ¶0111) formed on the upper surface of the semiconductor substrate (100) so as to cover the first transistor (30) and the second transistor (20); and
contact plugs (e.g., 710) (Shin, Fig. 4, ¶0117) buried in the interlayer dielectric film (400),
wherein a bottom surface of the first DTI region (500) is located in the first semiconductor region (e.g., in a region 30, a portion of the N-type substrate 100 between the deep trenches 500) (Shin, Fig. 4, ¶0091-¶0093),
wherein a bottom surface of the second DTI region (500) is located in the second semiconductor region (e.g., in a region 20, a portion of the N-type substrate 100 between the deep trenches 500) (Shin, Fig. 4, ¶0091-¶0093),
wherein the semiconductor substrate (100) includes:
a fifth semiconductor region (e.g., N-type region 103) (Shin, Fig. 4, ¶0094) of the n-type reaching the upper surface from the buried layer (102),
wherein a first contact plug (e.g., 710) (Shin, Fig. 4, ¶0117) of the contact plugs is disposed on the fifth semiconductor region (103) and electrically connected to the fifth semiconductor region (103).
Further, Shin does not specifically disclose (1) the buried layer including a third portion located between the first portion and the second portion; the first DTI region surrounding the first portion of the buried layer, the third semiconductor region and the first transistor in plan view; the second DTI region surrounding the second portion of the buried layer, the fourth semiconductor region and the second transistor in plan view, and (2) a fifth semiconductor region reaching the upper surface from the third portion of the buried layer, wherein, in plan view, the fifth semiconductor region and the third portion of the buried layer are interposed between the first DTI region and the second DTI region, and wherein the fifth semiconductor region surrounds the third semiconductor region and the first DTI region in plan view (as claim in claim 1); wherein in plan view, the fifth semiconductor region surrounds the third semiconductor region (as claim in claim 8).
Regarding (1), Morii teaches forming a semiconductor device (Morii, Figs. 1-4, ¶0038-¶0050, ¶0053-¶0064) comprising a low-voltage transistor region (e.g., CMOS second transistor region) and a high-voltage transistor region (e.g., high-voltages MOS first transistor region) each surrounded in plan view by a deep trench isolation region (DTR) that includes a first DTR region surrounding the first portion (e.g., under the high-voltage transistor region) of the buried layer (NBL), the third semiconductor region and the first transistor in plan view; and a second DTI region surrounding the second portion (e.g., under the low-voltage transistor region) of the buried layer (NBL), the fourth semiconductor region and the second transistor in plan view. In Morii, the buried layer (NBL) includes a third portion between the first DTR region and the second DTR region, and the isolation regions (DTR) are formed to effectively electrically separate the high-voltage transistor region and the low-voltage transistor region from the outside regions.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Shin by forming the first and second isolation regions (DTR) surrounding the high-voltage transistor region and the low-voltage transistor region, respectively, as taught by Morii, wherein the buried layer (NBL) includes a third portion between the first DTR region and the second DTR region to have the semiconductor device comprising: the buried layer including a third portion located between the first portion and the second portion; the first DTI region surrounding the first portion of the buried layer, the third semiconductor region and the first transistor in plan view; the second DTI region surrounding the second portion of the buried layer, the fourth semiconductor region and the second transistor in plan view, in order to provide effective electrical separation of the high-voltage transistor region and the low-voltage transistor region from the outside regions of the semiconductor substrate (Morii, ¶0038, ¶0040, ¶0061).
Regarding (2), Morii teaches a semiconductor region (e.g., a portion of the substrate between the first and second isolation regions (DTR)) (Morii, Figs. 1-4, ¶0053-¶0064) reaching the upper surface of the substrate from the third portion of the buried layer (NBL), wherein, in plan view, the semiconductor region and the third portion of the buried layer are interposed between the first DTI region and the second DTI region.
Further, Moen teaches forming an isolation region (Moen, Figs. 3E-3F, ¶0002, ¶0040-¶0050), including an n-type semiconductor region (e.g., 573B), wherein, in plan view, the n-type semiconductor region (e.g., 573B) is interposed between the first DTI region (362A) and the second DTI region (365A), and wherein the n-type semiconductor region (e.g., 573B) surrounds the third semiconductor region (e.g., p-type region 315) and the first DTI region (362A) in plan view.
Further, Khemka teaches forming the isolation structure (100) (Khemka, Fig. 9, Col. 1, lines 6-26; Col. 7, lines 12-31, lines 61-67; Col. 8, lines 1-14) including a fifth semiconductor region (e.g., n-doped sinker region 88) (Khemka, Fig. 9, Col. 7, lines 17-31) of the n-type adjacent the deep isolation region (100) and reaching the upper surface of the substrate from the third portion (722) of the n-type buried layer (72), wherein the fifth semiconductor region (88) and the third portion (722) of the buried layer are adjacent the first deep isolation region (100), and N+ contact region (89) is provided on the fifth semiconductor region (e.g., n-doped sinker region 88) and is connected to the drain of the LDMOS transistor, and the first portion of the n-type buried layer (72) is isolated from the third portion (722) of the buried layer by the deep isolation wall (100), to increase the transient breakdown voltage, and to improve performance of the LDMOS transistor.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Shin/Morii by forming the buried layer including a third portion between the first DTI region and the second DTI region as taught by Morii, and forming the fifth semiconductor region as the n-type semiconductor region of Moen between the first and second DTI regions, wherein the fifth semiconductor region is formed on the third portion of the buried layer as taught by Khemka to have the semiconductor device comprising, a fifth semiconductor region reaching the upper surface from the third portion of the buried layer, wherein, in plan view, the fifth semiconductor region and the third portion of the buried layer are interposed between the first DTI region and the second DTI region, and wherein the fifth semiconductor region surrounds the third semiconductor region and the first DTI region in plan view (as claim in claim 1); wherein in plan view, the fifth semiconductor region surrounds the third semiconductor region (as claim in claim 8), in order to provide effective electrical separation of the high-voltage transistor region and the low-voltage transistor region from the outside regions of the semiconductor substrate; and increase the transient breakdown voltage, and to improve performance of the LDMOS transistor (Morii, ¶0038, ¶0040, ¶0061; Moen, ¶0002, ¶0040-¶0050; Khemka, Col. 1, lines 6-26; Col. 7, lines 12-31, lines 61-67; Col. 8, lines 1-14).
Regarding claim 9, Shin in view of Morii, Moen, and Khemka discloses the semiconductor device according to claim 1. Further, Shin discloses the semiconductor device, wherein an impurity concentration of the buried layer (102, a high-concentration region in the substrate 100) (Shin, Fig. 4, ¶0093) is higher than an impurity concentration of each of the first semiconductor region and the substrate region (100).
Regarding claim 11, Shin in view of Morii, Moen, and Khemka discloses the semiconductor device according to claim 1. Further, Shin discloses the semiconductor device, wherein the semiconductor substrate (100) includes: a first well region (130) (Shin, Fig. 4, ¶0093) formed in the fourth semiconductor region (e.g., 101), wherein the first source region (e.g., N+ source region) (Shin, Fig. 4, ¶0094) and the first drain region (e.g., N+ drain region) are spaced apart from each other, wherein the second source region (e.g., N-type source region) (Shin, Fig. 4, ¶0093) and the second drain region (e.g., N-type drain region) (Shin, Fig. 4, ¶0093) are formed in the first well region (130) and spaced apart from each other, wherein a first gate electrode (350) (Shin, Fig. 4, ¶0094) of the first transistor (30) is formed on the upper surface of the semiconductor substrate (100) between the source region and the drain region via a gate dielectric film, and wherein a second gate electrode (300) (Shin, Fig. 4, ¶0093) of the second transistor (20) is formed on the upper surface of the semiconductor substrate (100) between the second source region and the second drain region via a second gate dielectric film.
Regarding claim 12, Shin in view of Morii, Moen, and Khemka discloses the semiconductor device according to claim 1. Further, Shin discloses the semiconductor device, wherein a region under the third semiconductor region (104) in the semiconductor substrate (100) is all the region of the n-type, but does not specifically disclose that a region under the fifth semiconductor region in the semiconductor substrate is all the region of the n-type.
Further, Khemka teaches forming a fifth semiconductor region (88) (Khemka, Fig. 9, Col. 7, lines 12-31) in the semiconductor substrate (70), wherein regions under fifth semiconductor region (88) includes n-type buried layer (722) and a portion of the substrate (70) having P-type or other doping type (e.g., N-type).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Shin/Morii/Moen/Khemka by forming the fifth semiconductor region as the n-type semiconductor region on the third portion of the n-type buried layer as taught by Khemka, wherein the n-type buried layer is formed in the n-type substrate to have the semiconductor device, wherein a region under the fifth semiconductor region in the semiconductor substrate is all the region of the n-type, in order to provide improved LDMOS semiconductor device having improved breakdown voltage (Khemka, Col. 1, lines 6-26; Col. 7, lines 61-67; Col. 8, lines 1-14).
Regarding claim 13, Shin in view of Morii, Moen, and Khemka discloses the semiconductor device according to claim 1. Further, Shin discloses the semiconductor device, wherein an STI region (120) (Shin, Fig. 4, ¶0099-¶0100) is formed in the semiconductor substrate (100).
Claims 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0059689 to Shin in view of Morii (US 2015/0041960), Moen (US 2018/0323187), and Khemka (US Patent No. 8,338,872) as applied to claim 1, and further in view of Olofsson (US Patent No. 7,022,560).
Regarding claim 2, Shin in view of Morii, Moen, and Khemka discloses the semiconductor device according to claim 1. Further, Shin discloses the semiconductor device, wherein the first transistor (30) (Shin, Fig. 4, ¶0094) is an n-channel type MISFET (e.g., n-channel metal-insulator-semiconductor), but does not specifically disclose that a potential higher than a potential of the third semiconductor region is supplied from the first contact plug to the fifth semiconductor region.
However, Olofsson teaches forming a high-voltage MOS transistor comprising a buried layer of the first conductivity type (11) and an isolation region including a contact region (25) of the first conductivity type for the buried layer (11) that reaches the upper surface of the semiconductor substrate (1) from the buried layer (11), wherein a positive voltage (+Vcc) is applied to the contact region (25) to improve isolation characteristics of the MOS structure.
Thus, Olofsson recognizes that a positive voltage applied to the isolation region including the contact region of the buried layer impacts isolation characteristics of the MOS structure. Thus, a voltage applied to the isolation region is a result-effective variable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, a voltage applied to the fifth semiconductor region that functions as an isolation region as Olofsson has identified a voltage applied to the isolation region as a result-effective variable. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at specific positive voltage applied to the isolation region including the fifth semiconductor region such that that a potential higher than a potential of the third semiconductor region is supplied from the first contact plug to the fifth semiconductor region, in order to improve isolation characteristics of the MOS structure as taught by Olofsson (Col. 5, lines 46-51) (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Shin/Morii/Moen/Khemka by optimizing voltage/potential applied to the isolation region as taught by Olofsson, wherein the isolation region includes the fifth semiconductor region to have the semiconductor device, wherein a potential higher than a potential of the third semiconductor region is supplied from the first contact plug to the fifth semiconductor region, in order to improve isolation characteristics of the MOS structure (Olofsson, Col. 5, lines 46-51).
Regarding claim 3, Shin in view of Morii, Moen, Khemka, and Olofsson discloses the semiconductor device according to claim 2. Further, Shin does not specifically disclose that a positive potential is supplied from the first contact plug to the fifth semiconductor region.
However, Olofsson teaches forming a high-voltage MOS transistor comprising a buried layer of the first conductivity type (11) and an isolation region including a contact region (25) of the first conductivity type for the buried layer (11) that reaches the upper surface of the semiconductor substrate (1) from the buried layer (11), wherein a positive voltage (+Vcc) is applied to the contact region (25) to improve isolation characteristics of the MOS structure.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Shin/Morii/Moen/Khemka/ Olofsson by applying voltage/potential to the isolation region as taught by Olofsson, wherein the isolation region includes the fifth semiconductor region to have the semiconductor device, wherein a positive potential is supplied from the first contact plug to the fifth semiconductor region, in order to improve isolation characteristics of the MOS structure (Olofsson, Col. 5, lines 46-51).
Regarding claim 4, Shin in view of Morii, Moen, Khemka, and Olofsson discloses the semiconductor device according to claim 2. Further, Shin discloses the semiconductor device, wherein the first transistor is an LDMOSFET (30, EDMOS) (Shin, Fig. 4, ¶0094).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0059689 to Shin in view of Morii (US 2015/0041960), Moen (US 2018/0323187), and Khemka (US Patent No. 8,338,872) as applied to claim 1, and further in view of Tanaka (US 2020/0177180).
Regarding claim 5, Shin in view of Morii, Moen, and Khemka discloses the semiconductor device according to claim 1. Further, Shin does not specifically disclose a power conversion circuit including a high-side transistor and a low-side transistor connected in series, wherein the first transistor is used as the low-side transistor in the power conversion circuit.
However, Tanaka teaches forming a power converter (60) (Tanaka, Fig. 1, ¶0001, ¶0011, ¶0015, ¶0038-¶0040, ¶0101) including a high-side transistor (S1) and a low-side transistor (S2) connected in series, wherein MOSFET transistor is used as the low-side transistor or the high-side transistor in the power conversion circuit (60). The power converter (60) is controlled by the semiconductor integrated circuit (50) which drives the power conversion circuit (60) and comprises silicon semiconductor material or a wide-bandgap semiconductor such as SiC or gallium nitride (GaN), to provide semiconductor integrated circuit with improved performance characteristics.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Shin/Morii/Moen/Khemka by forming a power converter as taught by Tanaka, wherein the MISFET transistor is used as the low-side transistor in the power conversion circuit to have the semiconductor device comprising: a power conversion circuit including a high-side transistor and a low-side transistor connected in series, wherein the first transistor is used as the low-side transistor in the power conversion circuit, in order to provide semiconductor integrated circuit with improved performance characteristics (Tanaka, ¶0001, ¶0011, ¶0015, ¶0038-¶0040, ¶0101).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0059689 to Shin in view of Morii (US 2015/0041960), Moen (US 2018/0323187), and Khemka (US Patent No. 8,338,872) as applied to claim 1, and further in view of Meiser et al. (US 2018/0175846, hereinafter Meiser).
Regarding claim 6, Shin in view of Morii, Moen, and Khemka discloses the semiconductor device according to claim 1. Further, Shin does not specifically disclose that a withstand voltage of the first transistor is larger than a withstand voltage of the second transistor.
However, Meiser teaches forming an electronic circuit (Meiser, Fig. 1, ¶0001, ¶0025-¶0033) operating as an electronic switch and including a first transistor (T1) and a second transistor (T2) connected in series, wherein the first transistor (T1) has higher voltage blocking capability to withstand high voltage spikes than the second transistor (T2). A lower voltage blocking capability of the second transistor device (T2) is provided by a lower size of a semiconductor body of the second transistor (T2) as compared with the size of a semiconductor body of the first transistor (T1) having higher blocking capability (Meiser, Fig. 1, ¶0031).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Shin/Morii/Moen/Khemka by forming an electronic circuit including a first transistor and a second transistor connected in series as taught by Meiser, wherein the first transistor has size of a semiconductor body greater than that of the second transistor to have the semiconductor device, wherein a withstand voltage of the first transistor is larger than a withstand voltage of the second transistor, in order to provide an electronic switch with improved performance characteristics (Tanaka, ¶0001, ¶0025, ¶0031).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0059689 to Shin in view of Morii (US 2015/0041960), Moen (US 2018/0323187), and Khemka (US Patent No. 8,338,872) as applied to claim 1, and further in view of Okamoto et al. (US 2024/0266351, hereinafter Okamoto).
Regarding claim 7, Shin in view of Morii, Moen, and Khemka discloses the semiconductor device according to claim 1. Further, Shin does not specifically disclose that the first transistor is a power switching element.
However, Okamoto teaches forming a semiconductor device (Okamoto, Fig. 1, ¶0001-¶0002, ¶0011, ¶0013, ¶0036-¶0046, ¶0073) on the n-type semiconductor substrate (SUB/DL), wherein SiC power transistor is configured as a high-speed switch.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Shin/Morii/Moen/Khemka by forming a semiconductor device on the n-type SiC semiconductor substrate as taught by Okamoto to have the semiconductor device, wherein the first transistor is a power switching element, in order to provide a power device controlling a high power and a large current, and having excellent performance characteristics (e.g., low on-resistance, high-speed operation and high temperature characteristics) (Okamoto, ¶0001-¶0002, ¶0013, ¶0044-¶0046).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0059689 to Shin in view of Morii (US 2015/0041960), Moen (US 2018/0323187), and Khemka (US Patent No. 8,338,872) as applied to claim 9, and further in view of Okamoto (US 2024/0266351), Huang et al. (US 2023/0078296, hereinafter Huang).
Regarding claim 10, Shin in view of Morii, Moen, and Khemka discloses the semiconductor device according to claim 9. Further, Shin does not specifically disclose that the impurity concentration of the first semiconductor region is higher than the impurity concentration of the substrate region.
However, Okamoto teaches the n-type semiconductor substrate (SUB/DL) comprised of a silicon carbide (SiC) material and including a substrate region (SUB) of the first conductivity type (n-type), a first semiconductor region (e.g., n-type epitaxial layer DL for the power transistor in the first region ARU) of the first conductivity type (e.g., n-type) (Okamoto, Fig. 1, ¶0001-¶0002, ¶0013, ¶0036-¶0046) having the n-type impurity concentration of 1e16 cm-3, to provide a power device controlling a high power and a large current, and having excellent performance characteristics (e.g., low on-resistance, high-speed operation and high temperature characteristics).
Further, Huang teaches forming a high-voltage semiconductor device (Huang, Fig. 2A, ¶0002, ¶0014-¶0015, ¶0018, ¶0020, ¶0036) on a substrate comprising silicon or silicon carbide material and including a lightly-doped n-type substrate region (101) under the n-type buried layer (102).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Shin/Morii/Moen/Khemka by forming a high-voltage semiconductor device on the n-type substrate comprising the n-type epitaxial layer including a first semiconductor region as taught by Okamoto, wherein the n-type substrate is a lightly-doped n-type substrate as taught by Huang to have the semiconductor device, wherein the impurity concentration of the first semiconductor region is higher than the impurity concentration of the substrate region, in order to provide a power device controlling a high power and a large current, and having excellent performance characteristics (e.g., low on-resistance, high-speed operation and high temperature characteristics); and to isolate the high-voltage semiconductor device having improved performance (Okamoto, ¶0001-¶0002, ¶0013, ¶0044-¶0046; Huang, ¶0002, ¶0015, ¶0018, ¶0036).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0059689 to Shin in view of Morii (US 2015/0041960), Moen (US 2018/0323187), and Khemka (US Patent No. 8,338,872) as applied to claim 1, and further in view of Ma et al. (US Patent No. 7,538,396, hereinafter Ma).
Regarding claim 15, Shin in view of Morii, Moen, and Khemka discloses the semiconductor device according to claim 1. Further, Shin does not specifically disclose that the semiconductor substrate includes: a sixth semiconductor region of the n-type covering a side surface of the fourth semiconductor region; and a seventh semiconductor region of the p-type interposed between the fifth semiconductor region and the sixth semiconductor region, wherein the fifth semiconductor region covers a side surface of the third semiconductor region, wherein the seventh semiconductor region penetrates through the buried layer and reaches the second semiconductor region, and wherein the second semiconductor region is of the p-type.
However, Ma teaches forming a semiconductor device (Ma, Fig. 3, Col. 2, lines 8-14; Col. 4, lines 12-31; Col. 5, lines 34-65; Col. 6, lines 6-67; Col. 7, lines 1-18) comprising a first high-voltage transistor (A2) (Ma, Fig. 3, Col. 6, lines 10-18) and a second transistor (A1) on the semiconductor substrate (200) including a sixth semiconductor region (204n) of the first conductivity type (e.g., n-type) covering a side surface of the fourth semiconductor region (214p); and a seventh semiconductor region (216p/218p) of the second conductivity type (e.g., p-type) interposed between the fifth semiconductor region (302n) and the sixth semiconductor region (204n), wherein the seventh semiconductor region (216p/218p) penetrates through the buried layer (208n) and reaches the second semiconductor region (e.g., an upper portion of the substrate 200 including PBL 215p), and wherein the second semiconductor region (215p) is of the second conductivity type (e.g., p-type), to provide junction isolation structure to effectively isolate the semiconductor devices, and to meet high integration requirement by using n-type and p-type buried layers.
Further, Khemka teaches forming the fifth semiconductor region (88) (Khemka, Fig. 9, Col. 7, lines 12-31) in the semiconductor substrate (70), wherein the fifth semiconductor region (88) covers a side surface of the third semiconductor region (74) of the LDMOS device.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Shin/Morii/Moen/Khemka by forming junction isolation structure between the first and second semiconductor devices including the p-type semiconductor region between n-type regions (as a seventh semiconductor between the fifth and sixth n-type semiconductor regions) as taught by Ma, wherein the first semiconductor device includes the n-type buried layer and the second semiconductor device includes the p-type buried layer under the n-type buried layer as taught by Ma to have the semiconductor device, wherein the semiconductor substrate includes: a sixth semiconductor region of the n-type covering a side surface of the fourth semiconductor region; and a seventh semiconductor region of the p-type interposed between the fifth semiconductor region and the sixth semiconductor region, wherein the fifth semiconductor region covers a side surface of the third semiconductor region, wherein the seventh semiconductor region penetrates through the buried layer and reaches the second semiconductor region, and wherein the second semiconductor region is of the p-type, in order to provide junction isolation structure to effectively isolate the semiconductor devices, and to meet high integration requirement by using n-type and p-type buried layers; and to provide semiconductor device having improved performance characteristics (Ma, Col. 2, lines 8-14; Col. 4, lines 12-31; Col. 5, lines 34-65; Col. 7, lines 7-18; Khemka, Col. 1, lines 6-26; Col. 7, lines 61-67; Col. 8, lines 1-14).
Response to Arguments
Applicant’s arguments with respect to claims 1-13 and 15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891
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