DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to the communications dated 06/30/2026.
Claims 1-20 are pending in this application.
Claim Objection
2. The claim is objected to for the following reason:
In claim 10, line 9, the phrase “and further to and a second region in the second level” should be changed to: -- and further to
Correction is required.
Remarks
3. Applicant’s arguments have been fully considered, but are moot in view of the new ground(s) of rejection(s). See details below.
Claim Rejections - 35 USC § 102
4. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
5. Claims 1-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim et al. (US 2024/0313000)
Regarding claim 1, Kim discloses a semiconductor structure, comprising:
a first set of transistors TR1 (see Fig. 2B) in a first level TR1, the first set of transistors TR1 having a first gate pitch (between gates G11-G31) and a first cell height (the heights of source/drain regions SD11-SD31); and
a second set of transistors TR2 in a second level TR2, the second set of transistors TR2 having a second gate pitch (between gates G12-G32) and a second cell height (the heights of source/drain regions SD12-SD32);
wherein the second level is vertically stacked over the first level;
wherein the first gate pitch is different than the second gate pitch; and
wherein the first cell height is different than the second cell height; and
a middle-of-line contact 261 & 221 & 231 &281 (or 273 & 222 & 232 & 282) extending (i) from a back-end-of-line interconnect structure B1 (BM11-BM19) at a first side of the first level TR1 through the first level TR1 in a first region in the first level disposed between a first gate structure G11 of a first transistor in the first set of transistors TR1 and a second gate structure G21 of a second transistor in the first set of transistors TR1 to a second side of the first level and further to (ii) a second region in the second level TR2 to contact a portion SD12 of at least one transistor of the second set of transistors TR2.
Regarding claim 2, Kim disclose the semiconductor structure of claim 1, wherein the first gate pitch is greater than the second gate pitch. See fig. 2B. Note that the structure of Kim can be turned upside-down so that TR2 will be the first level, and TR1 be the second level.
Regarding claim 3, Kim discloses the semiconductor structure of claim 1, wherein the first cell height is greater than the second cell height (in case the structure being turned upside-down).
Regarding claim 4, Kim discloses the semiconductor structure of claim 1, wherein the middle- of-line contact 261 & 221 & 231 &281 connects (i) a first source/drain region SD11 of at least one of the first and second transistors in the first set of transistors TR1 in the first level TR1 and (ii) a second source/drain region SD12 of the at least one transistor in the second set of transistors TR2 in the second level TR2, wherein the first source/drain region SD11 at least partially overlaps the second source/drain region SD12. See fig. 2B.
Regarding claim 5, Kim discloses the semiconductor structure of claim 1, wherein the middle-of-line contact 261 & 221 & 231 &281 (structurally) connects (i) a source/drain region SD11 of at least one of the first and second transistors in the first set of transistors TR1 in the first level TR1 and (ii) a gate structure G12 of said at least one transistor in the second set of transistors TR2 in the second level TR1, wherein the source/drain region at least partially overlaps the gate structure of said at least one transistor in the second set of transistors. See fig. 2B.
Regarding claim 6, Kim discloses the semiconductor structure of claim 1, further comprising at least one via connecting a first interconnect on a first side of the semiconductor structure below the first level and a second interconnect on a second side of the semiconductor structure above the second level. See fig. 2B.
Regarding claim 7, Kim discloses the semiconductor structure of claim 1, further comprising at least one interconnect on a first side of the semiconductor structure below the first level which connects to at least one transistor of the first set of transistors of the first level through one or more contacts below the first level. See fig. 2B.
Regarding claim 8, Kim discloses the semiconductor structure of claim 1, further comprising one or more interconnects on a first side of the semiconductor structure below the first level, the one or more interconnects on the first side of the semiconductor structure comprising a power delivery network and signal wirings. See fig. 2B.
Regarding claim 9, Kim discloses the semiconductor structure of claim 1, further comprising one or more interconnects on a second side of the semiconductor structure above the second level, the one or more interconnects on the second side of the semiconductor structure comprising a power delivery network and signal wirings. See fig. 2B.
Regarding claim 10, Kim discloses a semiconductor structure comprising:
a first set of transistors TR1 in a first level TR1 (see fig. 2B), the first set of transistors TR1 having a first gate pitch (between gates G11-G31) and a first cell height (the heights of source/drain regions SD11-SD31);
a second set of transistors TR2 in a second level TR2, the second set of transistors having a second gate pitch (between gates G12-G32) and a second cell height (the heights of source/drain regions SD12-SD32), wherein the second level TR2 is vertically stacked over the first level TR1; and
a middle-of-line contact 261 & 221 & 231 &281 (or 273 & 222 & 232 & 282) extending from a back-end-of-line interconnect structure B1 (BM11-BM19) at a first side of the first level TR1 through between a first region in the first level to a second side of the first level and further to
wherein the first region in the first level TR1 is disposed between a first gate structure G11 of a first transistor in the first set of transistors TR1 and a second gate structure G21 of a second transistor in the first set of transistors TR1.
Regarding claim 11, Kim discloses the semiconductor structure of claim 10, wherein the first gate pitch is different than the second gate pitch. See fig. 2B.
Regarding claim 12, Kim discloses the semiconductor structure of claim 11, wherein the first cell height is different than the second cell height. See fig. 2B.
Regarding claim 13, Kim discloses the semiconductor structure of claim 10, wherein the first region comprises a first source/drain region of at least one of the first and second transistors TR1 in the first set of transistors TR1 and the second region comprises a second source/drain region of one of the transistors in the second set of transistors TR2. See fig. 2B.
Regarding claim 14, Kim discloses the semiconductor structure of claim 10, wherein the first region comprises a source/drain region of at least one of the first and second transistors in the first set of transistors and the second region comprises a gate structure of one of the transistors in the second set of transistors. See fig. 2B.
Regarding claim 15, Kim discloses the semiconductor structure of claim 10, further comprising at least one via connecting a first interconnect on a first side of the semiconductor structure below the first level and a second interconnect on a second side of the semiconductor structure above the second level. See fig. 2B.
Regarding claim 16, Kim discloses an integrated circuit comprising:
a stacked transistor structure comprising:
a first set of transistors TR1 in a first level TR1, the first set of transistors having a first gate pitch (between gates G11-G31) and a first cell height (the heights of source/drain regions SD11-SD31);
a second set of transistors TR2 in a second level TR2, the second set of transistors having a second gate pitch (between gates G12-G32) and a second cell height (the heights of source/drain regions SD12-SD32); and
a middle-of-line contact 261 & 221 & 231 &281 (or 273 & 222 & 232 & 282) extending (i) from a back-end-of-line interconnect structure B1 (BM11-BM19) at a first side of the first level TR1 through the first level in a first region in the first level disposed between a first gate structure G11 of a first transistor in the first set of transistors TR1 and a second gate structure G21 of a second transistor in the first set of transistors TR1 to a second side of the first level and further to (ii) a second region in the second level TR2 to contact a portion of at least one transistor of the second set of transistors TR2;
wherein the second level TR2 is vertically stacked over the first level TR1;
wherein the first gate pitch is different than the second gate pitch; and
wherein the first cell height is different than the second cell height.
Regarding claim 17, Kim discloses the integrated circuit of claim 16, wherein the first gate pitch is greater than the second gate pitch. See fig. 2B (in case the structure being turned upside-down).
Regarding claim 18, Kim discloses the integrated circuit of claim 16, wherein the first cell height is greater than the second cell height (in case the structure being turned upside-down).
Regarding claim 19, Kim discloses the integrated circuit of claim 16, wherein the middle-of- line contact connects (i) a first source/drain region of at least one of the first and second transistors in the first set of transistors in the first level and (ii) a second source/drain region of the at least one transistor in the second set of transistors in the second level, wherein the first source/drain region at least partially overlaps the second source/drain region. See fig. 2B.
Regarding claim 20, Kim discloses the integrated circuit of claim 16, wherein the middle-of- line contact connects (i) a source/drain region of at least one of the first and second transistors in the first set of transistors in the first level and (ii) a gate structure of said at least one transistor in the second set of transistors in the second level, wherein the source/drain region at least partially overlaps the gate structure of said at least one transistor in the second set of transistors. See fig. 2B.
Conclusion
6. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the day of this letter. Failure to respond within the period for response will cause the application to become abandoned (see M.P.E.P 710.02(b)).
A shortened time for reply may be extended up to the maximum six-month period (35 U.S.C. 133). An extension of time fee is normally required to be paid if the reply period is extended. The amount of the fee is dependent upon the length of the extension. Extensions of time are generally not available after an application has been allowed.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Dao H. Nguyen whose telephone number is (571)272-1791. The examiner can normally be reached on Monday-Friday, 9:00 AM – 6:00 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke, can be reached on (571)272-1657. The fax numbers for all communication(s) is 571-273-8300.
Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-1633.
/DAO H NGUYEN/Primary Examiner, Art Unit 2818 July 22, 2026
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