DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
With respect to claim 6, the recitation of “second sheet pattern on the upper surface of the substrate, the second sheet pattern including a third end and a fourth end; a third source/drain pattern between the first source/drain pattern and the substrate, …and a fourth source/drain pattern between the contact blocking pattern and the substrate, the fourth source/drain pattern being connected to the fourth end of the second sheet pattern, wherein the first source/drain contact is connected to the third source/drain pattern” renders the claim as indefinite. It is unclear as to how the fourth source/drain pattern can be simultaneously connected to the fourth end of the second sheet pattern which is on the upper surface of the substrate and be between the substrate and the contact blocking pattern which would require the second sheet pattern to be below the substrate.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 5, 9-12, and 17-20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chang et al. (U.S. Publication No 2024/0030136 A1; hereinafter Chang)
With respect to claim 1, Chang discloses semiconductor device comprising: a substrate [101] including an upper surface and a lower surface that are opposite each other in a first direction; a first sheet pattern [104] on the upper surface of the substrate (see ¶[0011]), the first sheet pattern including a first end and a second end; a gate electrode [182] extending in a second direction on the upper surface of the substrate, the gate electrode surrounding the first sheet pattern (See ¶[0042] and Figure 16); a first source/drain pattern [146] connected to the first end of the first sheet pattern; a second source/drain pattern [146] connected to the second end of the first sheet pattern; a contact blocking pattern [195] on a lower side of the second source/drain pattern, the contact blocking pattern including an upper surface and a lower surface that are opposite each other in the first direction (see Figure 27); a first source/drain contact [196/197] extending in the first direction, the first source/drain contact being connected to the first source/drain pattern; and a second source/drain contact [196] in contact with the upper surface of the contact blocking pattern, the second source/drain contact extending in the first direction, and the second source/drain contact being connected to the second source/drain pattern, wherein a depth from an upper surface of the gate electrode to a lowermost portion of the first source/drain contact is greater than a depth from the upper surface of the gate electrode to the upper surface of the contact blocking pattern (see Figure 27).
With respect to claim 2, Chang discloses a power line [199] (VDD/VSS) on the lower surface of the substrate, wherein the first source/drain contact is connected to the power line, and the second source/drain contact is not connected to the power line (See Figure 27 and ¶[0068]).
With respect to claim 3, Chang discloses wherein the depth from the upper surface of the gate electrode to the lowermost portion of the first source/drain contact is equal to a depth from the upper surface of the gate electrode to the lower surface of the contact blocking pattern (See Figure 27).
With respect to claim 5, Chang discloses wherein a portion of the first source/drain contact and a portion of the second source/drain contact are in the substrate (See Figure 27).
With respect to claim 9, Chang discloses a semiconductor device comprising: a substrate [101] including an upper surface and a lower surface that are opposite each other in a first direction; a first sheet pattern [104] on the upper surface of the substrate (see ¶[0011]), the first sheet pattern including a first end and a second end; a gate electrode [182] extending in a second direction on the upper surface of the substrate, the gate electrode surrounding the first sheet pattern (See ¶[0042] and Figure 16); a first source/drain pattern [146] connected to the first end of the first sheet pattern; a second source/drain pattern [146] connected to the second end of the first sheet pattern; a first source/drain contact [196/197] extending in the first direction, the first source/drain contact being connected to the first source/drain pattern; and a second source/drain contact [196] extending in the first direction, the second source/drain contact being connected to the second source/drain pattern, wherein a depth from an upper surface of the gate electrode to a lowermost portion of the first source/drain contact is greater than a depth from the upper surface of the gate electrode to a lowermost portion of the first source/drain pattern, and a depth from the upper surface of the gate electrode to a lowermost portion of the second source/drain contact is greater than or equal to a depth from the upper surface of the gate electrode to a lowermost portion of the second source/drain pattern (see Figure 27).
With respect to claim 10, Chang discloses wherein a height of the first source/drain contact in the first direction is greater than a height of the second source/drain contact in the first direction (see Figure 27).
With respect to claim 11, Chang discloses a contact blocking pattern [195] in the substrate, wherein the second source/drain contact is in contact with the contact blocking pattern (see Figure 27).
With respect to claim 12, Chang discloses wherein the first source/drain contact penetrates through the substrate and extends to the lower surface of the substrate (see Figure 27).
With respect to claim 17, Chang discloses a semiconductor device comprising: a substrate [101] including an upper surface and a lower surface that are opposite each other in a first direction; a sheet pattern [104] on the upper surface of the substrate (see ¶[0011]), the sheet pattern including a first end and a second end; a gate electrode [182] extending in a second direction on the upper surface of the substrate, the gate electrode surrounding the sheet pattern (See ¶[0042] and Figure 16); a first source/drain pattern [146] connected to the first end of the sheet pattern; a second source/drain pattern [146] connected to the second end of the sheet pattern; a contact blocking pattern [195] in the substrate; a first source/drain contact [196/197] connected to the first source/drain pattern, the first source/drain contact penetrating through the substrate; and a second source/drain contact [196] connected to the second source/drain pattern, the second source/drain contact being in contact with the contact blocking pattern (See Figure 27).
With respect to claim 18, Chang discloses wherein a depth from an upper surface of the gate electrode to a lowermost portion of the second source/drain contact is greater than a depth from the upper surface of the gate electrode to a lowermost portion of the second source/drain pattern (See Figure 27).
With respect to claim 19, Chang discloses a power line [199] (VSS/VDD) on the lower surface of the substrate, wherein the first source/drain contact is connected to the power line, and the second source/drain contact is not connected to the power line (See Figure 27 and ¶[0068]).
With respect to claim 20, Chang discloses wherein a height from an upper surface of the gate electrode to an upper surface of the first source/drain contact is equal to a height from the upper surface of the gate electrode to an upper surface of the second source/drain contact (See Figure 27).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 4 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang in view of Reznicek et al. (U.S. Patent No. 11,315,923 B2; hereinafter Reznicek)
With respect to claim 4, Chang discloses a wiring structure on the upper surface of the substrate, wherein the wiring structure is connected to the second source/drain contact. In the same field of endeavor, Reznicek teaches a wiring structure [13501] on the upper surface of the substrate, wherein the wiring structure is connected to the second source/drain contact [1325] (see Figure 13; wiring structure is connected through source/drain pattern region to second source/drain contacts Column 13, lines 38-48). Implementation of the wiring structure of Reznicek facilitates voltage supplies and ground contacts for the source and drain of the transistor structures (see Column 13, lines 38-48). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 13, Chang discloses a power line [199] (VDD/VSS) on the lower surface of the substrate, the power line being connected to the first source/drain contact; wherein the second source/drain contact is not connected to the power line (See Figure 27 and ¶[0068]).
and a wiring structure on the upper surface of the substrate, the wiring structure being connected to the second source/drain contact,
In the same field of endeavor, Reznicek teaches a wiring structure [13501] on the upper surface of the substrate, the wiring structure being connected to the second source/drain contact [1325] (see Figure 13; wiring structure is connected through source/drain pattern region to second source/drain contacts Column 13, lines 38-48). Implementation of the wiring structure of Reznicek facilitates voltage supplies and ground contacts for the source and drain of the transistor structures (see Column 13, lines 38-48). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
Claim(s) 6-8 and 14-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang in view of Xie et al. (U.S. Publication No. 2023/0345691 A1; hereinafter Xie)
With respect to claim 6, Chang discloses fails to disclose second sheet pattern on the upper surface of the substrate, the second sheet pattern including a third end and a fourth end; a third source/drain pattern between the first source/drain pattern and the substrate, the third source/drain pattern being connected to the third end of the second sheet pattern; and a fourth source/drain pattern between the contact blocking pattern and the substrate, the fourth source/drain pattern being connected to the fourth end of the second sheet pattern, wherein the first source/drain contact is connected to the third source/drain pattern.
In the same field of endeavor, Xie teaches second sheet pattern [210] on the upper surface of the substrate, the second sheet pattern including a third end and a fourth end; a third source/drain pattern [212] between the first source/drain pattern and the substrate, the third source/drain pattern being connected to the third end of the second sheet pattern; and a fourth source/drain pattern [211] between the contact blocking pattern [110] and the substrate [120], the fourth source/drain pattern being connected to the fourth end of the second sheet pattern, wherein the first source/drain contact [711/812/832] is connected to the third source/drain pattern (see Figure 6B). Implementation of a stacked transistor structure as taught by Xie within the device of Chang allows for minimum cell area for the transistor structure (see Xie ¶[0002]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 7, the combination of Chang and Xie discloses wherein the depth from the upper surface of the gate electrode to the lowermost portion of the first source/drain contact is greater than a depth from the upper surface of the gate electrode to the lower surface of the contact blocking pattern (see Xie Figure 6B and Chang Figure 27).
With respect to claim 8. The semiconductor device of claim 6, wherein the first source/drain contact and the second source/drain contact do not include a portion in the substrate (see Xie Figure 6B and Chang Figure 27).
With respect to claim 14, Chang fails to disclose a second sheet pattern on the upper surface of the substrate, the second sheet pattern including a third end and a fourth end; a third source/drain pattern between the first source/drain pattern and the substrate, the third source/drain pattern connected to the third end of the second sheet pattern; and a fourth source/drain pattern between the second source/drain pattern and the substrate, the fourth source/drain pattern connected to the fourth end of the second sheet pattern, wherein the first source/drain contact extends to the third source/drain pattern and is connected to the third source/drain pattern, and the second source/drain contact does not extend to the fourth source/drain pattern. In the same field of endeavor, Xie teaches a second sheet pattern [210] on the upper surface of the substrate, the second sheet pattern including a third end and a fourth end; a third source/drain pattern [212] between the first source/drain pattern and the substrate, the third source/drain pattern connected to the third end of the second sheet pattern; and a fourth source/drain pattern [211] between the second source/drain pattern and the substrate, the fourth source/drain pattern connected to the fourth end of the second sheet pattern, wherein the first source/drain contact [711/812/832] extends to the third source/drain pattern and is connected to the third source/drain pattern, and the second source/drain contact does not extend to the fourth source/drain pattern (see Figure 6B).
With respect to claim 15, the combination of Chang and Xie discloses a contact blocking pattern [120] between the second source/drain pattern and the fourth source/drain pattern, wherein the second source/drain contact is in contact with the contact blocking pattern (see Xie Figure 9B).
With respect to claim 16, the combination of Chang and Xie discloses wherein a depth from the upper surface of the gate electrode to the lowermost portion of the third source/drain pattern is greater than the depth from the upper surface of the gate electrode to the lowermost portion of the first source/drain contact (See Chang Figure 27 and Xie Figure 9B).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. - Shi et al. (U.S. Patent No. 12,051,692 B2) discloses integrated circuit with front side signaling and backside power delivery.
Xie et al. (U.S. Publication No. 2023/0130305 A1) discloses stack devices with shared contacts
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONATHAN HAN whose telephone number is (571)270-7546. The examiner can normally be reached 9.00-5.00PM PST.
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/JONATHAN HAN/Primary Examiner, Art Unit 2818