DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of device embodiment 2 of fig. 3 (claims 1-11, 13 readable thereon, claims 12, 14-20 withdrawn) in the reply filed on 1/18/2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hsieh (US PGPub 2013/0075810).
Re claim 1: Hsieh teaches (e.g. figs. 2A,2B and labeled fig. 2B below) a protection structure (trench clamp diode 200; e.g. paragraph 25) for a power transistor (MOSFET 201; e.g. paragraph 25), the power transistor (201) including a gate terminal (gate metal layer 222; e.g. paragraph 25), a first current terminal (epi layer 202; e.g. paragraph 25; hereinafter “1CT”) and a second current terminal (n+ source region 206; e.g. paragraph 25; hereinafter “2CT”), the protection structure (200) comprising: at least one pair of pn junction diodes (226, 227 of diode 200 as shown in fig 2A, 2B) connected in a back-to-back configuration, the pn junction diodes (200) being provided in a first portion (area labeled “1P”) of a semiconductor substrate (218), the pn junction diodes (200) being formed in a first polysilicon layer (226, 227 within 1P; hereinafter “1PL”) provided in a first trench (trench 225 of 1P; hereinafter “1T”) formed in the semiconductor substrate (218), the first polysilicon layer (1PL) being isolated from the semiconductor substrate (218) by a first dielectric layer (210-1) formed on sidewalls of the first trench (1T), the first polysilicon layer (1PL) having alternating doped regions (226, 227) of first and second conductivity types along a length of the first trench (1T), at least a portion of the first polysilicon layer (1PL) being formed above a first surface (upper surface of 218) of the semiconductor substrate (218), wherein a first doped region (furthest right 226 as shown in fig. 2A; hereinafter “1DR”) of the first conductivity type (n-type) in the first polysilicon layer (1PL) is coupled to the gate terminal (222) of the power transistor (201) and a second doped region (furthest left 226 as shown in fig. 2A; hereinafter “2DR”) of the first conductivity type (n-type) in the first polysilicon layer (1PL) is coupled to the second current terminal (213,206) of the power transistor (201), the first doped region (1DR) is separated from the second doped region (2DR) by at least a third doped region (furthest right 227 as shown in fig. 2A; hereinafter “3DR”) of the second conductivity type (p-type).
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Re claim 2: Hsieh teaches the protection structure of claim 1, wherein the length of the first trench (1T) extends in a first direction (right-left direction of fig. 2B; hereinafter “1D”) in the semiconductor substrate (218) and a width of the first trench (1T) extends in a second direction (up-down direction of fig. 2B; hereinafter “2D”), the second direction (2D) being orthogonal to the first direction (1D) and in the same plane as the first surface (upper surface of 218) of the semiconductor substrate (218), the length of the first trench (1T) being larger than the width.
Re claim 3: Hsieh teaches the protection structure of claim 1, wherein the power transistor (201) is provided in a second portion (area labeled “2P”) of the semiconductor substrate (218), the power transistor (201) comprises: a second polysilicon layer (gate electrode 209 formed of polysilicon; e.g. paragraph 25) formed in a second trench (gate trench 205; e.g. paragraph 25) formed in the semiconductor substrate (218), the second polysilicon layer (209) being isolated from the semiconductor substrate (218) by a second dielectric layer (210); a body region (207) of the second conductivity type (p-type) formed in and at the first surface (upper surface of 218) of the semiconductor substrate (218) adjacent the second trench (205); and a source region (206) of the first conductivity type (n-type) formed in the body region (207) adjacent the second trench (205), wherein a length of the second trench (205) is parallel (as can be seen in fig. 2B, the dashed line ABCD shows that 205 and 1T extends in the same direction) to the length of the first trench (1T).
Re claim 4: Hsieh teaches the protection structure of claim 3, wherein the first trench (1T) has a depth extending into the semiconductor substrate (218) opposite from the first surface (upper surface of 218) greater than a depth (there exists a depth within 205 that is shallower than T1) of the second trench (205).
Re claim 5: Hsieh teaches the protection structure of claim 3, wherein the first dielectric layer (210-1) has a thickness greater than a thickness of the second dielectric layer (210 adjacent gate 209 is thinner than 210-1).
Re claim 6: Hsieh teaches the protection structure of claim 3, wherein a thickness of the first dielectric layer (210-1) is selected to provide a predetermined protection voltage of the protection structure (200).
Re claim 7: Hsieh teaches the protection structure of claim 3, wherein the semiconductor substrate (218) forms the first current terminal (1CT) of the power transistor (201) and the source region (206) forms the second current terminal (2CT) of the power transistor (201), one of the first and second current terminals (1CT, 2CT) being coupled to a first power supply voltage (voltage applied to 213) and the other one of the first and second current terminals being configured to drive a load (voltage applied to 222), and the second polysilicon layer (209) forms the gate terminal which is configured to receive a control signal (gate voltage).
Re claim 8: Hsieh teaches the protection structure of claim 1, further comprising a plurality of pairs of pn junction diodes (226, 227), each pair of pn junction diodes being connected in a back-to-back configuration, the plurality of pairs of pn junction diodes being formed in the first polysilicon layer (1PL) in the first trench (1T) as alternating doped regions (226, 227) of the first and second conductivity types along the length of the first trench (1T).
Re claim 9: Hsieh teaches the protection structure of claim 1, further comprising a plurality of pairs of pn junction diodes (226, 227), each pair of pn junction diodes being connected in a back-to-back configuration, the plurality of pairs of pn junction diodes being formed in a plurality of polysilicon layers (plural polysilicon regions are disposed adjacent to portion 1P to form multiple diode regions) provided in a plurality of trenches (each diode region is provided with a trench) in the semiconductor substrate (218), a subset of the plurality of pn junction diodes being formed in a given polysilicon layer (226, 227) in the respective trench as alternating doped regions (226, 227) of the first and second conductivity types along the length of the first trench (1T), at least a portion of each of the plurality of polysilicon layers being formed above the first surface (upper surface of 218) of the semiconductor substrate (218).
Re claim 10: Hsieh teaches the protection structure of claim 9, wherein the length of the plurality of trenches extends in a first direction (1D) in the semiconductor substrate (218) and a width of each trench extends in a second direction (2D), the second direction (2D) being orthogonal to the first direction (1D) and in the same plane as the first surface (upper surface of 218) of the semiconductor substrate (218), the length of the trenches being larger than the width.
Re claim 11: Hsieh teaches the protection structure of claim 10, wherein the alternating doped regions (226, 227) of the first and second conductivity types in a first one of the plurality of trenches (1T) are aligned in the first direction (1D) as the alternating doped regions (226, 227) of the first and second conductivity types in a second one of the plurality of trenches (trench adjacent 1T).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsieh as applied to claim 9 above, and further in view of Sato (US 10,522,668).
Re claim 13: Hsieh teaches the protection structure of claim 9, wherein the plurality of the polysilicon layers (1PL and adjacent polysilicon layer) of the pn junction diodes are connected together by a polysilicon cap layer (left 226 as shown in fig. 2B are commonly formed to connect to each diode in each trench) formed above the plurality of polysilicon layers (226, 227) above the first surface (upper surface of 218) of the semiconductor substrate (218).
It may be considered that a polysilicon cap layer formed above the plurality of polysilicon layers above the first surface of the semiconductor substrate.
Sato teaches (e.g. figs. 9B and 3) a polysilicon cap layer (14 as shown in fig. 1B and 3; e.g. column 4, lines 35-40 of Sato) formed above the plurality of polysilicon layers (226 of plural diodes of Hsieh) above the first surface (upper surface of 23) of the semiconductor substrate (23).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use a polysilicon cap as taught by Sato in the device of Hsieh in order to have the predictable result of using an alternate method of connecting gate terminals by using gate runners to protection diodes which would allow for variability for the number of diodes connected for the protection circuit of Hsieh.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JESSE Y MIYOSHI whose telephone number is (571)270-1629. The examiner can normally be reached M-F, 8:30AM-5:00PM.
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/JESSE Y MIYOSHI/
Primary Examiner, Art Unit 2898