Prosecution Insights
Last updated: April 19, 2026
Application No. 18/335,138

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

Final Rejection §102§103§112
Filed
Jun 15, 2023
Examiner
REIDA, MOLLY KAY
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
SK Hynix Inc.
OA Round
2 (Final)
84%
Grant Probability
Favorable
3-4
OA Rounds
2y 3m
To Grant
86%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allow Rate
348 granted / 417 resolved
+15.5% vs TC avg
Minimal +2% lift
Without
With
+2.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
31 currently pending
Career history
448
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
46.3%
+6.3% vs TC avg
§102
34.4%
-5.6% vs TC avg
§112
16.0%
-24.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 417 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 22 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 22 is currently written as being dependent upon claim 13, which is a withdrawn claim and would result in a lack of antecedent basis issue for the claim. It appears that claim 22 was intended to be dependent upon claim 21 and the application will be examined as such. Appropriate correction is required. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-5, 6-10, 21, and 22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US Pub. 2006/0040444). Regarding independent claim 1, Lee teaches a semiconductor device (Figs. 4A-4G; para. 0036+) comprising: a data storage element including a first electrode (420, 450) disposed over a semiconductor substrate (para. 0036-0038), wherein the first electrode includes: a pillar body (450) which is oriented perpendicular to a surface of the semiconductor substrate and which includes a tapered sidewall (Fig. 4D); and a sealing layer (420) covering the tapered sidewall of the pillar body (Fig. 4D), wherein the sealing layer includes a tapered inner surface and a vertical outer surface (Fig. 4D). Re claim 2, Lee teaches wherein an outer wall of the first electrode includes a vertical sidewall which is defined by the sealing layer (Fig. 4D). Re claim 3, Lee teaches wherein the tapered sidewall of the pillar body has a negative slope (Fig. 4D). Re claim 4, Lee teaches wherein a diameter of a bottom portion of the pillar body is smaller than a diameter of a top portion of the pillar body (Fig. 4D). Re claim 5, Lee teaches wherein an outer wall of the pillar body is surrounded by the sealing layer (Fig. 4D). Re claim 6, Lee teaches wherein the tapered inner surface of the sealing layer contacts the tapered sidewall of the pillar body (Fig. 4D). Re claim 7, Lee teaches wherein the tapered inner surface of the sealing layer has a positive slope (Fig. 4D). Re claim 8, Lee teaches wherein the pillar body includes at least one of a metal and a noble metal (para. 0038). Re claim 9, Lee teaches wherein the sealing layer includes a conductive metal oxide (para. 0036). Re claim 10, Lee teaches wherein the sealing layer includes niobium oxide (Nb2O5) (para. 0036). Re claim 21, Lee teaches wherein the sealing layer includes an upper-level sealing layer (upper half of sealing layer 420) and a lower-level sealing layer (lower half of sealing layer 420) (Fig. 4D). Re claim 22, Lee teaches wherein an average thickness of the upper-level sealing layer is smaller than an average thickness of the lower-level sealing layer (Fig. 4D). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-12 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Jeong et al. (US Pub. 2013/0256769) in view of Kang et al. (US Pub. 2020/0395438). Regarding independent claim 1, Jeong teaches a semiconductor device (Figs. 1A-1B; para. 0060+) comprising: a data storage element (capacitor CP; para. 0076) including a first electrode (60; para. 0076) disposed over a semiconductor substrate (1; para. 0061), wherein the first electrode includes: a pillar body (60) which is oriented perpendicular to a surface of the semiconductor substrate and which includes a tapered sidewall (Fig. 1B). Jeong is silent with respect to a sealing layer. Kang teaches a semiconductor device including a sealing layer (174A) covering the sidewalls of the pillar body (172A) (Fig. 4; para. 0064-0065). It would have been obvious to one of ordinary skill in the art at the time of filing to include a sealing layer as taught by Kang within the device of Jeong for the purpose of improving the capacitance of the capacitor (Kang para. 0067). When including a sealing layer within the device of Jeong the sealing layer would include a tapered inner surface (inner surface of the portion of the sealing layer on the slanted portion of the pillar body) and a vertical outer surface (outer surface of the portion of the sealing layer in the vertical portion of the pillar body) as claimed. Re claim 2, the combination of Jeong and Kang teaches wherein an outer wall of the first electrode includes a vertical sidewall which is defined by the sealing layer (Jeong Fig. 1B; Kang Fig. 4). Re claim 3, Jeong teaches wherein the tapered sidewall of the pillar body has a negative slope (Fig. 1B). Re claim 4, Jeong teaches wherein a diameter of a bottom portion of the pillar body is smaller than a diameter of a top portion of the pillar body (Fig. 1B). Re claim 5, the combination of Jeong and Kang teaches wherein the pillar body includes a vertically oriented pillar shape, and wherein an outer wall of the pillar body is surrounded by the sealing layer (Jeong Fig. 1B; Kang Fig. 4). Re claim 6, the combination of Jeong and Kang teaches wherein the tapered inner surface of the sealing layer contacts the tapered sidewall of the pillar body (Jeong Fig. 1B; Kang Fig. 4). Re claim 7, the combination of Jeong and Kang teaches wherein the tapered inner surface of the sealing layer has a positive slope (Jeong Fig. 1B; Kang Fig. 4). Re claim 8, Jeong is silent with respect to a material of the pillar body. Kang teaches wherein their pillar body includes at least one of a metal, a metal nitride, a conductive metal oxide, and a noble metal (para. 0063). It would have been obvious to one of ordinary skill in the art at the time of filing to look to Kang to provide that which was missing from Jeong; that is, a material for the pillar body to arrive at the claimed invention with a reasonable expectation of success. Furthermore, the selection of a known material based on its suitability for its intended use is considered prima facie obviousness (MPEP 2144.07). Re claim 9, the combination of Jeong and Kang teaches wherein the sealing layer includes a conductive metal oxide (Kang para. 0065). Re claim 10, Kang teaches wherein the sealing layer includes conductive metal oxides, but is silent with respect to at least one of titanium oxide (TiO2), niobium oxide (Nb2O5), molybdenum oxide (MoO2), and indium oxide (InO2) specifically; however, titanium oxide (TiO2), niobium oxide (Nb2O5), molybdenum oxide (MoO2), and indium oxide (InO2) are known conductive metal oxides and it would have been obvious to one of ordinary skill in the art at the time of filing to choose one of them with a reasonable expectation of success (MPEP 2143, I, E). Furthermore, the selection of a known material based on its suitability for its intended use is considered prima facie obviousness (MPEP 2144.07). Re claim 11, the combination of Jeong and Kang teaches wherein the sealing layer includes at least one of a metal and a metal nitride (Kang para. 0065). Re claim 12, Jeong teaches wherein the data storage element further includes: a supporter (40; para. 0076) supporting an outer wall of the first electrode; a dielectric layer (58; para. 0077) covering the supporter and the first electrode; and a second electrode (56; para. 0077) disposed over the dielectric layer (Fig. 1B). Re claim 21, the combination of Jeong and Kang wherein the sealing layer includes an upper-level sealing layer and a lower-level sealing layer (Jeong Fig. 1B; Kang Fig. 4). Response to Arguments Applicant's arguments filed with respect to the rejection of claim 1 under 35 U.S.C. 103 as being unpatentable over Jeong in view of Kang have been fully considered but they are not persuasive. Specifically, Applicant argues Jeong in view of Kang fails to disclose or suggest a sealing layer having both a tapered inner surface and vertical outer surface. The Examiner disagrees because when including a sealing layer (capping layer) of Kang within the device of Jeong, the sealing layer would include a tapered inner surface (inner surface of the portion of the sealing layer on the slanted portion of the pillar body 60 of Jeong) and a vertical outer surface (outer surface of the portion of the sealing layer in the vertical portion of the pillar body 60 of Jeong) as claimed. Applicant’s remaining arguments have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOLLY KAY REIDA whose telephone number is (571)272-4237. The examiner can normally be reached M-F 8:30-5:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at (571)272-4237. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MOLLY K REIDA/Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Jun 15, 2023
Application Filed
Nov 19, 2025
Non-Final Rejection — §102, §103, §112
Feb 27, 2026
Response Filed
Mar 09, 2026
Final Rejection — §102, §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
84%
Grant Probability
86%
With Interview (+2.4%)
2y 3m
Median Time to Grant
Moderate
PTA Risk
Based on 417 resolved cases by this examiner. Grant probability derived from career allow rate.

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