Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1-20 are objected to because of the following informalities:
Each of independent claims 1, 12 and 19 recites: “a backside-power-distribution-network (BSDPN). . ., wherein the BSPDN. . . .”
It appears that the acronym “BSDPN” as recited in each of claims 1, 12 and 19 is a typographical error and should instead be spelled as “BSPDN.”
All dependent claims are objected to because they depend from an objected parent claim.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3, 9-10 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over “Liebmann” (US 2022/0181258) in view of “Hong” (US 2023/0253324).
Regarding claim 1, Liebmann discloses 1. A microelectronic structure comprising: a backside-power-distribution-network (BSDPN) connected to a backside of a device region (Figs. 3C, 4A, [0039], [0044]; the BSPDN is connected to a backside of a device plane),
wherein the BSPDN is comprised of: a first type power rail and a second type power rail located on a same level (Figs. 3C, 4A, [0039], [0044]; the BSPDN is comprised of the backside power rails 431 and 433 located on a same level);
and a first power plane located on a level above the first type power rail and the second type power rail, wherein the first power plane extends across the first type power rail and the second type power rail (Figs. 3C, 4A, [0039], [0044]; the local interconnect structure 412 on the left of Fig. 4A is a first power plane located above the backside power rail 433, and the local interconnect structure 412 on the right of Fig. 4A is a second power plane located above the backside power rail 431),
wherein the first power plane is connected to the first type power rail, but not connected to the second type power rail (Figs. 3C, 4A, [0039], [0044]; the local interconnect structure 412 on the left of Fig. 4A is connected to the backside power rail 433, but not connected to the backside power rail 431).
Liebmann does not disclose a plurality of first and second type power rails.
Hong discloses a plurality of first and second type power rails ([0009]; the plurality of first and second power rails are configured to distribute power).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Liebmann’s structure with Hong’s embodiment in order to reduce routing congestion and a size of the BSPDN module, as suggested by Hong at [0034].
Regarding claim 2, Liebmann in view of Hong discloses the claimed invention as applied to claim 1, above.
Liebmann discloses 2. The microelectronic structure of claim 1, further comprising: a second power plane located on a second level, wherein the second power plane is located on a different level than the first power plane (Figs. 3C, 4A, [0039], [0044]; the local interconnect structure 412 on the right of Fig. 4A is located on a different level than the local interconnect structure 412 on the left of Fig. 4A).
Regarding claim 3, Liebmann in view of Hong discloses the claimed invention as applied to claim 2, above.
Liebmann discloses 3. The microelectronic structure of claim 2, wherein the second power plane is connected to the second type of power rail but not connected to the first type of power rail (Figs. 3C, 4A, [0039], [0044]; the local interconnect structure 412 on the right of Fig. 4A is connected to the backside power rail 431, but not connected to the backside power rail 433).
Regarding claim 9, Liebmann in view of Hong discloses the claimed invention as applied to claim 1, above.
Liebmann discloses a connection via connecting the first power plane to the first type of power rail (Figs. 3C, 4A, [0039], [0044], [0045]; the bottom power via 413 on the left of Fig. 4A connects the local interconnect structure 412 on the left of Fig. 4A to the backside power rail 433).
Liebmann does not disclose a plurality of connection vias and a plurality of first type of power rails.
Hong discloses a plurality of first type power rails ([0009]; the plurality of first power rails are configured to distribute power).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Liebmann’s structure, as modified by Hong’s embodiment, with a plurality of connection vias since Liebmann teaches a via is used per power rail.
Regarding claim 10, Liebmann in view of Hong discloses the claimed invention as applied to claim 1, above.
Liebmann discloses 10. The microelectronic structure of claim 1, wherein the first power plane is located directly on a top surface of the first type of power rail (Figs. 3C, 4A, [0039], [0044]; the local interconnect structure 412 on the left of Fig. 4A is located directly on a top surface of the backside power rail 433).
Regarding claim 19, Liebmann discloses 19. A microelectronic device comprising: a backside-power-distribution-network (BSDPN) connected to a backside of a device region (Figs. 3C, 4A, [0039], [0044]; the BSPDN is connected to a backside of a device plane),
wherein the BSPDN is comprised of: a first type power rail and a second type power rail located on a same level (Figs. 3C, 4A, [0039], [0044]; the BSPDN is comprised of the backside power rails 431 and 433 located on a same level);
a first power plane located on a level above the first type power rail and the second type power rail, wherein the first power plane extends across the first type power rail and the second type power rail (Figs. 3C, 4A, [0039], [0044]; the local interconnect structure 412 on the left of Fig. 4A is a first power plane located above the backside power rail 433, and the local interconnect structure 412 on the right of Fig. 4A is a second power plane located above the backside power rail 431),
wherein the first power plane is connected to the first type power rail, but not connected to the second type power rail (Figs. 3C, 4A, [0039], [0044]; the local interconnect structure 412 on the left of Fig. 4A is connected to the backside power rail 433, but not connected to the backside power rail 431).
and a plurality of metal lines located on a second level, wherein the plurality of metal lines are located on a different level than the first power plane (Figs. 3C, 4A, [0039], [0044]; the signal tracks 401 are plurality of metal lines located on a second level, wherein the plurality of metal lines are located on a different level than the first power plane).
Liebmann does not disclose a plurality of first and second type power rails.
Hong discloses a plurality of first and second type power rails ([0009]; the plurality of first and second power rails are configured to distribute power).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Liebmann’s structure with Hong’s embodiment in order to reduce routing congestion and a size of the BSPDN module, as suggested by Hong at [0034].
Regarding claim 20, Liebmann in view of Hong discloses the claimed invention as applied to claim 19, above.
Liebmann discloses 20. The microelectronic device of claim 19, wherein each of the plurality of metal lines are connected to one of the plurality of second type of power rails but not connected to the plurality of first type of power rails (Figs. 1, 3C, 4A, [0039], [0044]; each of the signal tracks 401 are connected to one power rail but not connected to the other power rail).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Liebmann in view of Hong and “Yang” (US 10,319,629).
Regarding claim 4, Liebmann in view of Hong discloses the claimed invention as applied to claim 3, above.
Liebmann discloses a via that connects the second power plane to the second type of power rail (Figs. 3C, 4A, [0039], [0044]-[0045]; the bottom power via connects the local interconnect structure 412 on the right of Fig. 4A to the backside power rail 431).
Liebmann does not disclose the vias are skip vias.
Yang discloses skip vias (Fig. 11, col. 12, lines 14-30; the metal vial 254 is a skip via).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Liebmann’s structure, as modified by Hong, with Yang’s skip vias in order to form connections between non-adjacent multilevel metallization layers that overcomes the scaling issues created by forming smaller device components and interconnects in the ever-decreasing device dimensions, as suggested by Yang at col. 1, lines 34-39.
Claims 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over Liebmann in view of Hong, Yang and “Yu” (US 2024/0389230).
Regarding claim 5, Liebmann in view of Hong and Yang discloses the claimed invention as applied to claim 4, above.
Liebmann does not disclose the limitations of claim 5.
Yu discloses each of the plurality of skip vias pass through the first power plane, wherein the first power plane surrounds the sidewalls of each of the plurality of skip vias (Fig. 5D, [0020]; the skip vias can skip or bypass a plane that surrounds the sidewalls of the skip vias).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Liebmann’s structure, as modified by Hong and Yang, with Yu’s skip vias in order to improve signal and power integrity in PCB construction that improves the fabrication efficiency and reduces costs, as suggested by Yu at [0020].
Regarding claim 6, Liebmann in view of Hong, Yang and Yu discloses the claimed invention as applied to claim 5, above.
Liebmann does not disclose the limitations of claim 6.
Yang discloses 6. The microelectronic structure of claim 5, further comprising: a dielectric liner located adjacent to each of the plurality of skip vias (Fig. 11, col 10, line 46; the insulator 138 is a dielectric liner located adjacent to the skip via).
Regarding claim 7, Liebmann in view of Hong, Yang and Yu discloses the claimed invention as applied to claim 6, above.
Liebmann does not disclose the limitations of claim 7.
Yang discloses 7. The microelectronic structure of claim 6, wherein the dielectric liner is located directly adjacent to each of the plurality of skip vias where each of the plurality of skip vias passes through the first power plane (Fig. 11, col 10, line 46; the insulator 138 is a dielectric liner located directly adjacent to the skip via that passes through the plane).
Regarding claim 8, Liebmann in view of Hong, Yang and Yu discloses the claimed invention as applied to claim 7, above.
Liebmann does not disclose the limitations of claim 8.
Yang discloses 8. The microelectronic structure of claim 7, wherein the dielectric liner is located between the sidewalls of each of the plurality of skip vias and the first power plane (Fig. 11, col 10, line 46; the insulator 138 is a dielectric liner located between the sidewall of the skip via and the plane).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Liebmann in view of Hong and “Cheng” (US 2021/0183908).
Regarding claim 11, Liebmann in view of Hong discloses the claimed invention as applied to claim 10, above.
Liebmann discloses the second type of power rail does not contact the first power plane (Figs. 3C, 4A, [0039], [0044]; the backside power rail 431 does not contact the local interconnect structure 412 on the left of Fig. 4A)
Liebmann does not disclose the plurality of first type of power rails and the plurality of second type of power rails have different dimensions.
Cheng discloses the plurality of first type of power rails and the plurality of second type of power rails have different dimensions ([0028]; the power rail layers 14 to 14d may have different shapes).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Liebmann’s structure, as modified by Hong, with Cheng’s embodiment in order to accommodate the design requirements of different chips, as suggested by Cheng at [0028].
Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Liebmann in view of Hong and “Elsherbini” (US 2024/0063202).
Regarding claim 12, Liebmann discloses 12. A microelectronic device comprising: a backside-power-distribution-network (BSDPN) connected to a backside of a device region (Figs. 3C, 4A, [0039], [0044]; the BSPDN is connected to a backside of a device plane),
wherein the BSPDN is comprised of: a first type power rail and a second type power rail is located on a same level (Figs. 3C, 4A, [0039], [0044]; the BSPDN is comprised of the backside power rails 431 and 433 located on a same level);
a first power plane located on a level above the first type power rail and the second type power rail, wherein the first power plane extends across the first type power rail and the second type power rail (Figs. 3C, 4A, [0039], [0044]; the local interconnect structure 412 on the left of Fig. 4A is a first power plane located above the backside power rail 433, and the local interconnect structure 412 on the right of Fig. 4A is a second power plane located above the backside power rail 431),
wherein the first power plane is connected to the first type power rail, but not connected to the second type power rail (Figs. 3C, 4A, [0039], [0044]; the local interconnect structure 412 on the left of Fig. 4A is connected to the backside power rail 433, but not connected to the backside power rail 431);
a second power plane located on a second level, wherein the second power plane is located on a different level than the first power plane (Figs. 3C, 4A, [0039], [0044]; the local interconnect structure 412 on the right of Fig. 4A is located on a different level than the local interconnect structure 412 on the left of Fig. 4A).
Liebmann does not disclose a plurality of first and second type power rails, an insulator layer located between the first power plane and the second power plane, wherein a metal-insulator-metal (MIM) capacitor is formed from the arrangement of the first power plane, the insulator layer, and the second power plane.
Hong discloses a plurality of first and second type power rails ([0009]; the plurality of first and second power rails are configured to distribute power).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Liebmann’s structure with Hong’s embodiment in order to reduce routing congestion and a size of the BSPDN module, as suggested by Hong at [0034].
Elsherbini an insulator layer located between the first power plane and the second power plane, wherein a metal-insulator-metal (MIM) capacitor is formed from the arrangement of the first power plane, the insulator layer, and the second power plane (Fig. 1A, [0083], [0089]; the metal-insulator-metal MIM capacitors 118 is formed from two parallel metal planes separated by a thin dielectric material).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Liebmann’s structure, as modified by Hong, with Elsherbini’s embodiment in order to enable better power conversion in high performance computer systems that require high density capacitors, as suggested by Elsherbini at [0025].
Regarding claim 13, Liebmann in view of Hong and Elsherbini discloses the claimed invention as applied to claim 12, above.
Liebmann discloses 13. The microelectronic device of claim 12, wherein the second power plane is connected to the second type of power rail but not connected to the first type of power rail (Figs. 3C, 4A, [0039], [0044]; the local interconnect structure 412 on the right of Fig. 4A is connected to the backside power rail 431, but not connected to the backside power rail 433).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Liebmann in view of Hong, Elsherbini and Yang.
Regarding claim 14, Liebmann in view of Hong and Elsherbini discloses the claimed invention as applied to claim 13, above.
Liebmann discloses a via that connects the second power plane to the second type of power rail (Figs. 3C, 4A, [0039], [0044]-[0045]; the bottom power via connects the local interconnect structure 412 on the right of Fig. 4A to the backside power rail 431).
Liebmann does not disclose the vias are skip vias.
Yang discloses skip vias (Fig. 11, col. 12, lines 14-30; the metal vial 254 is a skip via).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Liebmann’s structure, as modified by Hong and Elsherbini, with Yang’s skip vias in order to form connections between non-adjacent multilevel metallization layers that overcomes the scaling issues created by forming smaller device components and interconnects in the ever-decreasing device dimensions, as suggested by Yang at col. 1, lines 34-39.
Claims 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Liebmann in view of Hong, Elsherbini, Yang and Yu.
Regarding claim 15, Liebmann in view of Hong, Elsherbini and Yang discloses the claimed invention as applied to claim 14, above.
Liebmann does not disclose the limitations of claim 15.
Yu discloses each of the plurality of skip vias pass through the first power plane, wherein the first power plane surrounds the sidewalls of each of the plurality of skip vias (Fig. 5D, [0020]; the skip vias can skip or bypass a plane that surrounds the sidewalls of the skip vias).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Liebmann’s structure, as modified by Hong, Elsherbini and Yang, with Yu’s skip vias in order to improve signal and power integrity in PCB construction that improves the fabrication efficiency and reduces costs, as suggested by Yu at [0020].
Regarding claim 16, Liebmann in view of Hong, Yang, Elsherbini and Yu discloses the claimed invention as applied to claim 15, above.
Liebmann does not disclose the limitations of claim 16.
Yang discloses 16. The microelectronic structure of claim 15, further comprising: a dielectric liner located adjacent to each of the plurality of skip vias (Fig. 11, col 10, line 46; the insulator 138 is a dielectric liner located adjacent to the skip via).
Regarding claim 17, Liebmann in view of Hong, Yang, Elsherbini and Yu discloses the claimed invention as applied to claim 16, above.
Liebmann does not disclose the limitations of claim 17.
Yang discloses 17. The microelectronic structure of claim 16, wherein the dielectric liner is located directly adjacent to each of the plurality of skip vias where each of the plurality of skip vias passes through the first power plane (Fig. 11, col 10, line 46; the insulator 138 is a dielectric liner located directly adjacent to the skip via that passes through the plane).
Regarding claim 18, Liebmann in view of Hong, Yang, Elsherbini and Yu discloses the claimed invention as applied to claim 17, above.
Liebmann does not disclose the limitations of claim 18.
Yang discloses 18. The microelectronic structure of claim 17, wherein the dielectric liner is located between the sidewalls of each of the plurality of skip vias and the first power plane (Fig. 11, col 10, line 46; the insulator 138 is a dielectric liner located between the sidewall of the skip via and the plane).
Conclusion
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/STANLEY TSO/Primary Examiner, Art Unit 2847
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