CTNF 18/335,184 CTNF 71715 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 112 07-34-01 Claims 5, 10, 16-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph , as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. As per claim 5, the boundaries of claim scope are not clear. The antecedent basis for “routing track” [lines 2 and 4] is not particularly clear. For examination purposes, the feature is interpreted as “the same routing track” recited in claim 1, however, the Examiner requests the claim be so clarified. Thus, the claim is vague and indefinite. Taking claim 10 as exemplary of claims 5, 10 and 16-17, the boundaries of claim scope are not clear. The antecedent basis for “different segments” [lines 2 and 3] and “another buffer” [line 3] are not particularly clear. Claim 1 appears to solely provide limitations for a buffer, any further limitations regarding different segments and another buffer are not apparent. While the preamble of claim 1 recites “in an integrated circuit” [line 1] any limitations or boundaries without respect to a specific or particular integrated circuit are not recited or apparent from the claim language. Thus, the claim is vague and indefinite. The following rejections are based on the Examiner’s best interpretation of the claims in view of the indefiniteness identified above. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-6, 8-13, 15-20 are rejected under 35 U.S.C. 102( a)(1) and (a)(2 ) as being anticipated by Chen et al. [US 11,423,204 B1] 1. A buffer arranged in an integrated circuit [FIGS. 7A and 7B, the buffer comprising: one or more logic circuits [column 14, lines 2-3 buffer (or inverter) may be used as a repeater, line 42 repeater 715 (e.g., buffer), line 56 repeater 745]; and an input signal pin electrically coupled to an input of one of the one or more logic circuits and an output signal pin electrically coupled to an output of one of the one or more logic circuits [column 14, lines 42-44 repeater (e.g. buffer) may be used to route feedthrough wire 700, repeater 715 may include an input pin 720 and an output pin 725, lines 56-58 repeater 745 that is used with feedthrough wire 730 may include an input pin 750 and an output pin 755]; wherein the input signal pin and output signal pin are positioned on a same routing track which specifies a routing in the integrated circuit [column 14, lines 32-34 depending upon the orientation of the routing resources of the feedthrough wires the orientation of the input and output pins on the repeater may vary] and a respective segment of a net routed to the input and output signal pin is on the same routing track [column 14, lines 47-48 allow the routing resources of the feedthrough wire 700 to be routed, 60-62 allow the routing resources of the feedthrough wire 730 to be routed]. 2. The buffer of claim 1, wherein the routing track is oriented in a horizontal or vertical direction in the integrated circuit [column 14, lines 29-30 vertical and horizontal orientations]. 3. The buffer of claim 2, wherein the buffer is formed in a first layer of the integrated circuit column 14, lines 1-5] and signal pins are arranged through one or more layers of the integrated circuit from the first layer to an second layer on which the segments are routed [column 15, lines 10-31]. 4. The buffer of claim 1, wherein a skew of a group of signals which includes a signal output by the output signal pin or input by the input signal pin is less than a threshold amount [skew is inherent, column 7, lines 12-14 clock signals may be considered critical signals, impact chip speed and lines 30-31 for IR drop may be improved are interpreted to include a group of signals, column 12, lines 13-16 design constraints may specify timing constraints with which the integrated circuit needs to comply is interpreted to provide a threshold amount]. 5. The buffer of claim 1, wherein one or more routing tracks in parallel with the routing track are in between the segments of the buffer and segments of another buffer where the segments of the other buffer are routed parallel to the routing track, the buffer and the other buffer arranged offset from each other along a common side [this is interpreted as shielding, column 7, lines 10-31, column 13, lines 45-47, column 15, lines 27-31, 38-47]. 6. The buffer of claim 1, wherein the segments routed to the input signal pin and the output signal pin have identical routing topologies [column 7, lines 3-4 identical routing topologies result with H-trees being inherently symmetric]. 8. The buffer of claim 1, wherein the buffer spans a distance of two or more routing tracks perpendicular to the same routing track [column 10, lines 13-19 orientation, size and shape may vary, column 10, lines 28-56, column 15, lines 10-47]. 9. The buffer of claim 1, wherein a logic circuit of the one or more logic circuits is selected from a group comprising an AND gate, OR gate, and inverter [column 2, lines 52-56 standard cells inherently comprise AND gates, OR gates, etc., column 14, line 2 (or inverter)]. 10. The buffer of claim 1, wherein a track is in between the segments, the segments being electrically coupled to the buffer and different segments electrically coupled to another buffer, the different segments along another track parallel to the routing track [given the indefiniteness identified above, this claim is best interpreted as column 7, lines 10-31 shielding, column 13, lines 45-47 may be leveraged, column 14, lines 29-30 vertical and horizontal orientations]. 11. The buffer of claim 1, wherein the net of the integrated circuit is defined by a Manhattan routing and the same routing track is in an X or Y direction, where the X and Y direction are perpendicular to each other [Manhattan routing is inherent, column 14, lines 29-30 vertical and horizontal orientations]. 12. The buffer of claim 1, wherein a signal is received by the input signal pin from a first segment of the segments formed on the routing track and is output by the output signal pin to a second segment of the segments formed on the routing track [column 14, lines 16-29]. 13. A method for an electronic design automation (EDA) tool to perform routing in an integrated circuit [FIG. 1], the method comprising: defining a net in the integrated circuit associated with a skew critical protocol [column 3, lines 44-58 part of CAD or EDA software suite used by a user to create a layout, standard cell layout of the circuit may show various components and connections, clock signals, column 12, lines 3-16 netlist, design constraints, column 15, lines 51-52 timing critical nets; skew is considered inherent]; identifying a first segment [FIG. 7A feedthrough wire 700] of a net routed in a first direction along a first track in the first direction on a layer of an integrated circuit [column 14, lines 29-48 vertical orientation]; positioning a first buffer [column 14, lines 2-3, FIG. 7A buffer 715] in the net where the first segment is routed to a first input pin [input pin 720] and a first output pin [output pin 725] of the first buffer, the first input pin and first output pin positioned on the first track [column 14, lines 29-48 vertical orientation]; identifying a second segment [FIG. 7B feedthrough wire 730] of the net arranged in a second direction along a second track in the second direction on a layer of an integrated circuit [column 14, lines 49-62horizontal orientation]; and positioning a second buffer [column 14, lines 2-3, FIG. 7B buffer 745] in the net where the second segment is routed a second input pin [input pin 750] and a second output pin [output pin 755] of the second buffer, the second input pin and second output pin positioned on the second track [column 14, lines 49-62horizontal orientation]; wherein the first segment is routed perpendicular to the second segment and the first track is perpendicular to the second track [column 11, lines 8-15 extend in intersecting directions, column 14, lines 16-34]. 15. The method of claim 13, wherein a routing of the first segment to the first pins and second pins does not include a detour to a different track [the reference does not appear to disclose a detour]. 16. The method of claim 13, wherein a track is in between the segments, the segments being electrically coupled to the buffer and segments electrically coupled to another buffer [column 14, lines 16-28, column 15, lines 27-47]. 17. The method of claim 13, wherein positioning the first buffer comprises positioning the first buffer so that one or more routing tracks in parallel with the first track are in between the first segment and segments of another buffer where the segments of the other buffer are routed in the first direction, the first buffer and the other buffer arranged offset from each other along a common side [this is interpreted as shielding, column 7, lines 10-31, column 13, lines 45-47, column 15, lines 27-47]. 18. The method of claim 13, wherein the first segment routed to the first input pin has identical routing topologies to the second segment routed to the second input pin and the first segment routed to the first output pin has identical routing topologies to the second segment routed to the second output pin [column 7, lines 3-4 identical routing topologies result with H-trees being inherently symmetric]. 19. The method of claim 13, wherein the net of the integrated circuit is defined by a Manhattan routing and the same routing track is in an X or Y direction, where the X and Y direction are perpendicular to each other [Manhattan routing is inherent, column 14, lines 29-30 vertical and horizontal orientations]. 20. The method of claim 13, wherein the first buffer spans a distance of two or more tracks in the second direction [column 10, lines 13-19 orientation, size and shape may vary, column 10, lines 28-56, column 15, lines 10-47] . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 7 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. [US 11,423,204 B1] . Chen et al. teach the features from which the claims depend, including clocking signals may be distributed through the integrated circuit design to synchronous components and the clock tree may be synthesized using clock buffers [column 12,lines 28-31]. However, Chen et al. do not explicitly teach wherein the segments comprises a lane of a bus of a source synchronous interface (SSI). SSI is a widely used standard interface. Provided SSI is the designer’s chosen clocking technique, feedthrough wires would be interpreted as a lanes of a bus thereof. Thus, the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains because SSI is a design choice that allows for higher speeds . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See, for example, Brown et al. (entire document); Huang et al. [US 7,487,488 B1] (entire document, particularly column 2, lines 39-45 regarding detours); Wang et al. [US 11,144,703 B1] at column 11, lines 48-58; Kim et al. [US 2021/0384186 A1] at paragraphs [0031, 0052, 0071, 0072, 0076]; Singh et al. [US 11,151,298 B1] at Abstract, column 14, lines 34-column 15, line 5; Li et al. [US 2023/0385504 A1] at FIG. 13 . Any inquiry concerning this communication or earlier communications from the examiner should be directed to LEIGH M GARBOWSKI whose telephone number is (571)272-1893. The examiner can normally be reached M-F 9-5 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /LEIGH M GARBOWSKI/ Primary Examiner, Art Unit 2851 Application/Control Number: 18/335,184 Page 2 Art Unit: 2851 Application/Control Number: 18/335,184 Page 3 Art Unit: 2851 Application/Control Number: 18/335,184 Page 4 Art Unit: 2851 Application/Control Number: 18/335,184 Page 5 Art Unit: 2851 Application/Control Number: 18/335,184 Page 6 Art Unit: 2851 Application/Control Number: 18/335,184 Page 7 Art Unit: 2851 Application/Control Number: 18/335,184 Page 8 Art Unit: 2851 Application/Control Number: 18/335,184 Page 9 Art Unit: 2851