DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of the application
This office Action is in response to Applicant's Application filled on 10/22/2025. Claims 1-20 are pending for this examination.
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). The certified copy has been filed on 07/17/2023.
Oath/Declaration
The oath or declaration filed on 10/09/2023 is acceptable.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/15/2023 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the examiner.
Election/Restrictions
Applicant’s election, without traverse, group I Species I, directed to an embodiment as depicted in FIGS. [1-2], with claims 1-9 and 19-20, in the “Response to Election / Restriction Filed” filed on 10/22/2025 is acknowledged and entered.
This office action considers claims 1-20 are thus pending for prosecution, of which, non-elected claims 10-18 are withdrawn, and elected claims 1-9 and 19-20 are examined on their merits.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4 and 8-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huynh Bao et al (US 2018/0174642 A1; hereafter Huynh).
Regarding claim 1. Huynh discloses a bit cell for a Static Random-Access Memory (SRAM), the bit cell (Fig [1-2]) comprising:
first and second sets of transistors (Fig [1-2], Para [ 0083] discloses “The first stack 110 includes a pull-up transistor PU1, a pull-down transistor PD1 and a pass transistor PG1. The second stack 120 includes a pull-up transistor PU2, a pull-down transistor PD2 and a pass transistor PG2”) arranged on a substrate (Fig [1-2], substrate 102), each set comprising a respective pass-gate transistor and a respective stacked complementary transistor pair of an upper transistor and a lower transistor (Fig [1-2], Para [ 0083] discloses “The first stack 110 includes a pull-up transistor PU1, a pull-down transistor PD1 and a pass transistor PG1. The second stack 120 includes a pull-up transistor PU2, a pull-down transistor PD2 and a pass transistor PG2”);
wherein each transistor of the first set (Fig [1-2], Para [ 0083] discloses “The first stack 110 includes a pull-up transistor PU1, a pull-down transistor PD1 and a pass transistor PG1) comprises a semiconductor channel extending between respective source and drain regions along a horizontal first channel track (Fig [1-2], channels [ 112c, 114c and 116c], Para [ 0086-0087]), and
each transistor of the second set (Fig [1-2], Para [ 0083] discloses “The second stack 120 includes a pull-up transistor PU2, a pull-down transistor PD2 and a pass transistor PG2”) comprises a semiconductor channel extending between respective source and drain regions along a horizontal second channel track (Fig [1-2], channels [ 122c, 124c and 126c], Para [ 0091-0098]);
wherein the semiconductor channels of the lower transistors are arranged at a first level above the substrate (Fig [1-2], pull-up transistors PU1 and PU2, Para [ 0076-0089]) and the semiconductor channels of the upper transistors are arranged at a second level, above the first level (Fig [1-2], pull-down transistors PD1 and PD2, Para [ 0076-0089]);
wherein the semiconductor channels of the pass-gate transistors are arranged at the first level or the second level (Fig [1-2], pass gate PG-1 and PG-2, Para [ 0075-0082]);
wherein a source or drain terminal (112a/ 112b Para [ 0086, 0112]) of the lower transistor of each set of transistors (Fig [1-2], pull-up transistors PU1 and PU2, Para [ 0085-0089]) is connected to a respective first power supply extending in a first power supply track arranged below the lower transistor (Para [ 0107]); and
wherein a source or drain terminal (124a/ 124b and 122a/122b, Para [ 0089, 0112]) of the upper transistor of each set of transistors (Fig [1-2], pull-down transistors PD1 and PD2, Para [ 0076-0089]) is connected to a respective second power supply extending in a second power supply track arranged above the upper transistor (Para [0078, 0107]).
Regarding claim 2. Huynh discloses the bit cell of claim 1, Huynh further discloses wherein a gate of each of the pass-gate transistors (Fig [1-2], pass gate PG-1 and PG-2, Para [ 0075-0082]) is connected to a respective word line (Fig [1-2], word line WL, Para [ 0078]) extending in a word line track arranged at the same vertical level as the second power supply track (Para [ 0078, 0107]).
Regarding claim 4. Huynh discloses the bit cell of claim 1, Huynh further discloses wherein the first power supply is a buried interconnect (Fig [1-2], Para [0078-0079, 0107]).
Regarding claim 8. Huynh discloses the bit cell of claim 1, Huynh further discloses wherein the semiconductor channel of each transistor is formed of a respective fin portion, nanosheet portion, or nanowire portion (Fig [1-2], Para [ 0075-0090, 0107]).
Regarding claim 9. Huynh discloses the bit cell of claim 1, Huynh further discloses wherein the semiconductor channel of each transistor comprises a vertical stack of nanosheet portions or nanowire portions (Fig [1-2], Para [ 0075-0090,0107]).
Allowable Subject Matter
Claims 3 and 5-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is the Examiner's Reasons for Allowance:
The prior art fails to disclose and would not have rendered obvious:
Regarding claim 3. The bit cell of claim 2, wherein: a source or drain terminal of the pass-gate transistor of the first set of transistors is connected to a first bit line;
a source or drain terminal of the pass gate transistor of the second set of transistors is connected to a second bit line; and the first and second bit lines extend in a respective bit line track arranged at a level between the pass-gate transistors and the word line tracks.
Regarding claim 5. The bit cell of claim 1, further comprising: a first inverter gate electrode forming a common gate electrode for the semiconductor channels of the complementary transistor pair of the first set of transistors and a second inverter gate electrode forming a common gate electrode for the semiconductor channels of the complementary transistor pair of the second set of transistors, wherein the first and second inverter gate electrodes extend in a horizontal gate track transverse to the channel tracks: a first pass gate electrode forming a gate of the first pass-gate transistor and being aligned with the first inverter gate electrode; a second pass gate electrode forming a gate of the second pass-gate transistor and being aligned with the second inverter gate electrode; and a dielectric wall disposed in a trench that separates the first pass gate electrode from the first inverter gate electrode and that separates the second pass gate electrode from the second inverter gate electrode.
Claims 6-7 is objected based on the dependency of claim 5.
Claims 19-20 are allowed.
The following is the Examiner's Reasons for Allowance:
The prior art fails to disclose and would not have rendered obvious:
wherein the first and second bit lines extend in a respective bit line track arranged at a level between the pass-gate transistors and the word line tracks; and a first inverter gate electrode forming a common gate electrode for the semiconductor channels of the complementary transistor pair of the first set of transistors and a second inverter gate electrode forming a common gate electrode for the semiconductor channels of the complementary transistor pair of the second set of transistors, wherein the first and second inverter gate electrodes extend in a horizontal gate track transverse to the channel tracks: a first pass gate electrode forming a gate of the first pass-gate transistor and being aligned with the first inverter gate electrode; a second pass gate electrode forming a gate of the second pass-gate transistor and being aligned with the second inverter gate electrode; and a dielectric wall disposed in a trench that separates the first pass gate electrode from the first inverter gate electrode and that separates the second pass gate electrode from the second inverter gate electrode., as recited in claim 19.
Claim 20 are allowed based on the dependency of claim 19.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOIN M RAHMAN whose telephone number is (571)272-5002. The examiner can normally be reached 8:30-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOIN M RAHMAN/Primary Examiner, Art Unit 2898
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