Prosecution Insights
Last updated: May 29, 2026
Application No. 18/335,332

CHIP PACKAGE AND CHIP PACKAGE PREPARATION METHOD

Non-Final OA §103
Filed
Jun 15, 2023
Priority
Dec 16, 2020 — continuation of PCTCN2020136865
Examiner
CAMPBELL, SHAUN M
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Huawei Technologies Co., Ltd.
OA Round
2 (Non-Final)
73%
Grant Probability
Favorable
2-3
OA Rounds
0m
Est. Remaining
81%
With Interview

Examiner Intelligence

Grants 73% — above average
73%
Career Allowance Rate
750 granted / 1033 resolved
+4.6% vs TC avg
Moderate +8% lift
Without
With
+8.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
27 currently pending
Career history
1079
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
88.1%
+48.1% vs TC avg
§102
7.0%
-33.0% vs TC avg
§112
2.3%
-37.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1033 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION RCE, received 4/7/2026, has been entered. Claims 1, 4-8, 11-14, 17-21, 23, 25 and 27-29 are presented for examination. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 1, 4-7, 14, 17-21, 25, 27 and 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US Pub. No. 2018/0294202 A1), hereafter referred to as Cheng, in view of Liu et al. (US Pub. No. 2015/0214074 A1), hereafter referred to as Liu. As to claim 1, Cheng discloses a chip package (title, Fig 1C), comprising: a substrate (120) having at least a first surface (top); a die (130) having at least a first surface (top) and a side surface (side); a first protection structure (structure including materials 150a and 150b in the region shown in annotated figure 1C) having at least a first surface (top) and a second surface (bottom), wherein the first protection structure (see annotated 1st protection structure) wraps the side surface of the die (130); a second protection structure (see annotated figure 1C below that shows 2nd protection structure including 150a in the region between the die and the substrate) disposed between the substrate (120) and the die (130); and a blocking structure (140) having at least a first surface (top), wherein the die (130), the first protection structure (see annotated fig 1C below), and the blocking structure (140) are all disposed on the first surface (top) of the substrate (120), the blocking structure (140) wraps a surface (side), of the first protection structure (see annotated fig 1C below), away from the die (130), the first surface of the die, the first surface of the first protection structure, and the first surface of the blocking structure are flush ([0018]), the first surface of the die is away from the substrate (top of 130 is away from 120), the first surface of the first protection structure is away from the substrate (top of 150b is away from 120), the second surface of the first protection structure is in contact with the first surface of the substrate (see annotated fig 1C below), the first surface of the blocking structure is away from the substrate (top of 140 is away from 120), the first protection structure includes a material different from a material of the second protection structure ([0025]), a gap other than the connection elements between the substrate (120) and the die (130) is filled with the second protection structure (150a), and a distance (h1) between the first surface of the die and the first surface of the substrate is equal to a distance (h2) between the first surface of the first protection structure and the first surface of the first substrate (see annotated fig 1C below that shows that the distance from the top surface of substrate 120 to the top surface of 130 and 150b is equal). Cheng does not disclose that the contacts connecting the die to the substrate include a solder ball. Nonetheless, Liu discloses wherein an electrical contact is made between a die (fig 3, 106) and a substrate (102) using a solder ball (108; [0022]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the electrical connection between the contacts of Cheng as taught by Liu since this will provide reliable electrical continuity between the terminals. PNG media_image1.png 475 823 media_image1.png Greyscale As to claim 4, Cheng in view of Liu disclose the chip package according to claim 1 (paragraphs above), Cheng further discloses wherein a viscosity of the material of the first protection structure is greater than a viscosity of the material of the second protection structure ([0025]). As to claim 5, Cheng in view of Liu disclose discloses the chip package according to claim 1 (paragraphs above), Cheng further discloses a plurality of dies, wherein orthographic projections of the plurality of dies on the first surface of the substrate do not overlap with each other (fig 1C, die 130 on the right does not overlap with the die 130 on the left). As to claim 6, Cheng in view of Liu disclose the chip package according to claim 5 (paragraphs above), Cheng further discloses a plurality of first protection structures (1st protection structure for each die 130), wherein each of the plurality of first protection structures wraps at least one of the plurality of dies (150b wraps each of the die 130), and different first protection structures, from the plurality of first protection structures, wrap different dies from the plurality of dies (different 150b structures wrap different dies 130). As to claim 7, Cheng in view of Liu disclose the chip package according to claim 6 (paragraphs above), Cheng further discloses a plurality of blocking structures (blocking structures 140), wherein a quantity of the plurality of blocking structures is equal to a quantity of the plurality of first protection structures (number of 140 equals that of 150b), and the plurality of blocking structures separately wrap the plurality of first protection structures (140 wraps 150b). As to claim 14, Cheng discloses a chip package preparation method (figs 4A-E), comprising: disposing a die (fig 4A, 130) on a first surface of a substrate (top of 120); disposing a first blocking structure (140) around a side surface of the die (130) on the first surface of the substrate (120), wherein a gap exists between the first blocking structure and the die (gap between 130 and 140 shown in fig 4B), a distance between a first surface of the first blocking structure and the first surface of the substrate is greater than a distance between a first surface of the die and the first surface of the substrate ([0018]), the first surface of the first blocking structure is away from the substrate (top of 140 away from 120), and the first surface of the die is away from the substrate (top surface of 130 is away from 120); filling the gap between the first blocking structure and the die with a first filling material (fig 4C, 150), until a first surface of the first filling material is flush with the first surface of the first blocking structure (150 and 140 are flush), wherein the first surface of the first filling material is away from the substrate (top of 150 is away from 120); filling the gap other than the electrical connector between the substrate (120) and the die (130) with a second filling material (150a); wherein the third protection structure includes a material different from a material of the second protection structure ([0025]), wherein a second surface of a first protection structure (1st protection structure shown in annotated fig 1C) is in contact with the first surface of the substrate (top surface of 120), and a distance (h1) between the first surface of the die and the first surface of the substrate is equal to a distance (h2) between the first surface of the first protection structure and the first surface of the first substrate (see annotated fig 1C below that shows that the distance from the top surface of substrate 120 to the top surface of 130 and 150b is equal). Cheng does not disclose heating and solidifying the first or second filling material to form a second or third protection structure; and grinding a first surface of the third protection structure and the first surface of the first blocking structure, until the first surface of the die is exposed. Nonetheless, Liu discloses heating and solidifying a filling material to form a protection structure ([0027]); and grinding the protection structure until a die is exposed, to form a first protection structure ([0026]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to cure each of the protection structures of Cheng by heating and solidifying as taught by Liu since this will ensure that both the filler is hardened and the underfill material is hardened, and the grinding of the protection structure and blocking structure of Cheng as taught by Liu since this will improve packaging sizing by ensuring that the top surface is flat without increasing the vertical dimensions of the package. Additionally, Cheng does not disclose that the contacts connecting the die to the substrate include a solder ball. Nonetheless, Liu discloses wherein an electrical contact is made between a die (fig 3, 106) and a substrate (102) using a solder ball (108; [0022]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the electrical connection between the contacts of Cheng as taught by Liu since this will provide reliable electrical continuity between the terminals. As to claim 17, Cheng in view of Liu disclose the preparation method according to claim 14 (paragraphs above). Cheng further discloses wherein a viscosity of the material of the third protection structure is greater than a viscosity of the material of the second protection structure ([0025]). As to claim 18, Cheng in view of Liu disclose the preparation method according to claim 14 (paragraphs above). Cheng further discloses wherein disposing the die on the first surface of the substrate comprises: disposing a plurality of dies on the first surface of the substrate (dies 130 on 120), wherein orthographic projections of the plurality of dies on the first surface of the substrate do not overlap with each other (130 does not overlap). As to claim 19, Cheng in view of Liu disclose the preparation method according to claim 18 (paragraphs above). Cheng further discloses wherein disposing the first blocking structure around the side surface of the die on the first surface of the substrate comprises: disposing a plurality of first blocking structures (140) on the first surface of the substrate (top of 120), wherein each of the plurality of first blocking structures (140) surrounds a side surface of at least one of the plurality of dies (130), and a different first blocking structure surrounds different dies from the plurality of dies (each die 130 is surrounded by a different structure 140). As to claim 20, Cheng in view of Liu disclose the preparation method according to claim 19 (paragraphs above). Cheng further discloses wherein filling the gap between the first blocking structure and the die with the first filling material comprises: filling, with the first filling material, a gap between each first blocking structure and the at least one die surrounded by each first blocking structure (filling material 150 in gap between blocking structure 140 and each die 130). As to claim 21, Cheng in view of Liu disclose the preparation method according to claim 1 (paragraphs above). Liu further discloses a plurality of solder balls, wherein the plurality of solder balls are disposed between the die and substrate (fig 3, solder balls 108 between die 106 and substrate 102). As to claim 25, Cheng in view of Liu disclose the preparation method according to claim 14 (paragraphs above). Liu further discloses wherein the die (106) is disposed on the first surface of the substrate (top of 102) by using a plurality of solder balls (108), and the plurality of solder balls (108) are between the die (106) and the substrate (102). As to claim 27, Cheng in view of Shen and Liu disclose the preparation method according to claim 1 (paragraphs above). Cheng further discloses a distance (h3) between the first surface of the blocking structure and the first surface of the substrate is equal to the distance (h1) between the first surface of the die and the first surface of the substrate (annotated fig 1C above shows distances from top surface of substrate 120 to top surface of 140 and 130 are equal), and the distance (h3) between the first surface of the blocking structure and the first surface of the substrate is equal to the distance (h2) between the first surface of the first protection structure and the first surface of the first substrate (annotated fig 1C above shows distances from top surface of substrate 120 to top surface of the 1st protection structure and 140 are equal). As to claim 29, Cheng in view of Shen and Liu disclose the preparation method according to claim 14 (paragraphs above). Cheng further discloses a distance (h3) between the first surface of the blocking structure and the first surface of the substrate is equal to the distance (h1) between the first surface of the die and the first surface of the substrate (annotated fig 1C above shows distances from top surface of substrate 120 to top surface of 140 and 130 are equal), and the distance (h3) between the first surface of the blocking structure and the first surface of the substrate is equal to the distance (h2) between the first surface of the first protection structure and the first surface of the first substrate (annotated fig 1C above shows distances from top surface of substrate 120 to top surface of the 1st protection structure and 140 are equal). Claim(s) 8, 11-13, 23 and 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Liu and further in view of Shen et al. (US Pub. No. 2021/0375711 A1), hereafter referred to as Shen. As to claim 8, Cheng discloses a chip package (title, Fig 1C), comprising: a substrate (120) having at least a first surface (top); a die (130) having at least a first surface (top) and a side surface (side); a first protection structure (see annotated fig 1C above) having at least a first surface (top) and a second surface (bottom), wherein the first protection structure (fig 1C) wraps the side surface of the die (130); a second protection structure (see annotated fig 1C above) disposed between the substrate (120) and the die (130); and a blocking structure (140) having at least a first surface (top), wherein the die (130), the first protection structure (fig 1C), and the blocking structure (140) are all disposed on the first surface (top) of the substrate (120), the blocking structure (140) wraps a surface (side), of the first protection structure (fig 1C), away from the die (130), the first surface of the die, the first surface of the first protection structure, and the first surface of the blocking structure are flush ([0018]), the first surface of the die is away from the substrate (top of 130 is away from 120), the first surface of the first protection structure is away from the substrate (top of 150b is away from 120), the second surface of the first protection structure (fig 1C) is in contact with the first surface of the substrate (top of 120), the first surface of the blocking structure is away from the substrate (top of 140 is away from 120), the first protection structure includes a material different from a material of the second protection structure ([0025]), and a distance (h1) between the first surface of the die and the first surface of the substrate is equal to a distance (h2) between the first surface of the first protection structure and the first surface of the first substrate (see annotated fig 1C below that shows that the distance from the top surface of substrate 120 to the top surface of 130 and 150b is equal). However, Cheng does not explicitly disclose the IC or printed circuit board. Nonetheless, Shen discloses an IC comprising a PCB (fig 1L, [0027]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the chip package of Cheng in an IC with a PCB as taught by Shen since this will improve the interconnection of the chip package into a larger semiconductor component. Cheng does not disclose that the contacts connecting the die to the substrate include a solder ball. Nonetheless, Liu discloses wherein an electrical contact is made between a die (fig 3, 106) and a substrate (102) using a solder ball (108; [0022]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the electrical connection between the contacts of Cheng as taught by Liu since this will provide reliable electrical continuity between the terminals. As to claim 11, Cheng in view of Shen and Liu disclose the IC according to claim 8 (paragraphs above). Cheng further discloses wherein a viscosity of the material of the first protection structure is greater than a viscosity of the material of the second protection structure ([0025]). As to claim 12, Cheng in view of Shen and Liu disclose the IC according to claim 8 (paragraphs above). Cheng further discloses a plurality of dies, wherein orthographic projections of the plurality of dies on the first surface of the substrate do not overlap with each other (fig 1C, die 130 on the right does not overlap with the die 130 on the left). As to claim 13, Cheng in view of Shen and Liu disclose the IC according to claim 12 (paragraphs above). Cheng further discloses a plurality of first protection structures (150b for each die 130), wherein each of the plurality of first protection structures wraps at least one of the plurality of dies (150b wraps each of the die 130), and different first protection structures, from the plurality of first protection structures, wrap different dies from the plurality of dies (different 150b structures wrap different dies 130). As to claim 23, Cheng in view of Shen and Liu disclose the preparation method according to claim 8 (paragraphs above). Liu further discloses a plurality of solder balls (108), wherein the plurality of solder balls are disposed between the die (106) and the substrate (102). As to claim 28, Cheng in view of Shen and Liu disclose the preparation method according to claim 8 (paragraphs above). Cheng further discloses a distance (h3) between the first surface of the blocking structure and the first surface of the substrate is equal to the distance (h1) between the first surface of the die and the first surface of the substrate (annotated fig 1C above shows distances from top surface of substrate 120 to top surface of 140 and 130 are equal), and the distance (h3) between the first surface of the blocking structure and the first surface of the substrate is equal to the distance (h2) between the first surface of the first protection structure and the first surface of the first substrate (annotated fig 1C above shows distances from top surface of substrate 120 to top surface of the 1st protection structure and 140 are equal). Response to Arguments Applicant's arguments filed 03/06/2026 have been fully considered but they are not persuasive. Applicant argued that Cheng does not show the first filling material as being in contact with the substrate, as such, the first filling material cannot meet the limitation of the first protection structure. Examiner disagrees because Cheng does meet the claim limitation because the claimed first protection structure is considered to be a structured element that includes the region of 150a that is surrounding the periphery of the die 130, as well as, material 150b that surrounds the periphery of the die 130. Applicant argued that Liu fails to cure the deficiency of Cheng. Examiner disagrees because as newly considered in view of the claim amendments, Cheng does not include the argued deficiency. Pertinent Art The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Patent No. 9543249 B2; US Pub. No. 2009/0108429 A1; and US Pub. No. 2006/0091509 A1. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAUN M CAMPBELL whose telephone number is (571)270-3830. The examiner can normally be reached on MWFS: 7:30-6pm Thurs 1-2pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Purvis, Sue can be reached at (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SHAUN M CAMPBELL/Primary Examiner, Art Unit 2893 4/17/2026
Read full office action

Prosecution Timeline

Jun 15, 2023
Application Filed
Aug 20, 2025
Non-Final Rejection mailed — §103
Nov 17, 2025
Response Filed
Dec 11, 2025
Final Rejection mailed — §103
Mar 06, 2026
Response after Non-Final Action
Apr 07, 2026
Request for Continued Examination
Apr 15, 2026
Response after Non-Final Action

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12642082
CUTTING STRUCTURE, SEMICONDUCTOR DEVICE COMPRISING THE SAME, AND METHOD FOR FABRICATING THE SAME
2y 5m to grant Granted May 26, 2026
Patent 12635357
DISPLAY PANEL AND FABRICATION METHOD THEREOF, AND MOBILE TERMINAL
2y 11m to grant Granted May 19, 2026
Patent 12628499
DISPLAY DEVICE AND METHOD OF REPAIRING THE SAME
3y 11m to grant Granted May 12, 2026
Patent 12615925
DISPLAY APPARATUS HAVING A LIGHT-EMITTING DEVICE
3y 4m to grant Granted Apr 28, 2026
Patent 12604764
DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME
4y 0m to grant Granted Apr 14, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

2-3
Expected OA Rounds
73%
Grant Probability
81%
With Interview (+8.2%)
2y 6m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 1033 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month