DETAILED ACTION
This office action is in response to the amendments on April 24, 2026. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on April 24, 2026 has been entered. Accordingly, claims 1-20 are currently pending in this application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on June 15, 2023 is being considered by the examiner.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10, 16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kang (US 2020/0126919) in view of Sano (US 2022/0285320) and in further view of Kang (US 11,569,193).
With respect to Claim 1, Kang ‘919 shows (Fig. 7-8) most aspects of the current invention including a semiconductor device, comprising:
a first chip stacked body (2300) including a plurality of first semiconductor chips (2310) stacked in a stacking direction (vertical), the first chip stacked body having a first surface (lower) and a second surface (upper) at respective ends on a first side and a second side in the stacking direction;
a spacer (2550) extending in the stacking direction and positioned with respect to the first chip stacked body in a direction (horizontal) intersecting the stacking direction, the spacer having a third surface (lower) and a fourth surface (upper) at the respective ends on the first side and the second side in the stacking direction;
a second semiconductor chip (2410B) and a first resin layer (2430B) provided across the second surface of the first chip stacked body and the fourth surface of the spacer, the first resin layer (2430B) being positioned between the second semiconductor chip and each of the spacer and the first chip stacked body;
a second resin layer (2565; see Fig 7-8) provided on the third surface (lower) of the spacer and having a thickness larger than a thickness of the first resin layer
Furthermore, Kang ‘919 shows wherein the first resin layer (2430B) and the second resin layer (2565) are made of an adhesive or non-conductive film (NCF) and the second resin layer having a thickness larger than a thickness of the first resin layer.
However, Kang ‘919 does not explicitly disclose a thickness of a portion of the first resin layer that contacts with the fourth surface being smaller than a thickness of a portion of the first resin layer that contacts with the second surface, wherein each of the first resin layer and the second resin layer is a die attach film, the second semiconductor chip is thicker than at least one of the plurality of first semiconductor chips and an elastic modulus of the second resin layer is smaller than an elastic modulus of the first resin layer at a temperature before curing.
On the other hand, and in the same field of endeavor, Sano teaches (Fig 18) a semiconductor device, comprising a first chip stacked body including a plurality of first semiconductor chips (10) stacked in a stacking direction (vertical), a spacer (400) extending in the stacking direction, and positioned with respect to the first chip stacked body in a direction (horizontal) intersecting the stacking direction, a second semiconductor chip (500), the second semiconductor chip is thicker than at least one of the plurality of first semiconductor chips, a first resin layer (510) being positioned between the second semiconductor chip and each of the spacer and the first chip stacked body, wherein a thickness of a portion of the first resin layer that contacts with a fourth surface (upper surface of the spacer) being smaller than a thickness of a portion of the first resin layer that contacts with a second surface (upper surface of the first chip stacked body). Sano teaches this arrangement allows the desire to reduce a size of the package.
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have the arrangement of wherein a thickness of a portion of the first resin layer that contacts with the fourth surface being smaller than a thickness of a portion of the first resin layer that contacts with the second surface, and the second semiconductor chip is thicker than at least one of the plurality of first semiconductor chips in the device of Kang ‘919, as suggested by Sano because this arrangement allows the desire to reduce a size of the package.
However, Sano does not teach wherein each of the first resin layer and the second resin layer is a die attach film, and an elastic modulus of the second resin layer is smaller than an elastic modulus of the first resin layer at a temperature before curing.
On the other hand, and in the same field of endeavor, Kang ‘193 teaches (Fig 2) a semiconductor device, comprising a first chip stacked body including a plurality of first semiconductor chips (T1) stacked in a stacking direction (vertical), a spacer (27) extending in the stacking direction and positioned with respect to the first chip stacked body in a direction (horizontal) intersecting the stacking direction, a second semiconductor chip (21), a first resin layer (72) provided across a second surface (lower) of the first chip stacked body and between the second semiconductor chip and the first chip stacked body, and a second resin layer (71) provided on a third surface (lower) of the spacer, wherein each of the first resin layer and the second resin layer is a die attach film. Kang ‘193 teaches using the first resin layer and the second resin layer as a die attach film to support the attachment of the plurality of first semiconductor chips in the chip stacked body and to support the attachment of the spacer to the semiconductor substrate.
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have wherein each of the first resin layer and the second resin layer is a die attach film, in the device of Kang ‘919 and Sano, as suggested by Kang ‘193, which allows using the first resin layer to support the attachment of the plurality of first semiconductor chips in the chip stacked body and using the second resin layer to support the attachment of the spacer to the semiconductor substrate.
Furthermore, Kang ‘919 shows wherein the second resin layer having a thickness larger than a thickness of the first resin layer. Although Kang ‘919 in view of Sano and Kang ‘193 does not disclose an elastic modulus of the second resin layer is smaller than an elastic modulus of the first resin layer at a temperature before curing, note that a limitation in a claim with respect to a material property in a claimed device does not differentiate the claimed device from prior-art device if the prior-art device teaches all the structural limitations in the claims. As stated in Best, where the claimed and prior art products are identical or substantially identical in structure or composition, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F. 2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977).
In the instant case, Kang ‘919 in view of Sano and Kang ‘193 teaches all structural limitations, similar to the instant invention. Accordingly, the structure of Kang ‘919 in view of Sano and Kang ‘193 is understood as also teaching an elastic modulus of the second resin layer is smaller than an elastic modulus of the first resin layer at a temperature before curing.
Note that the applicant has a burden of proof once the examiner establishes a sound basis for believing that the products of the applicant and the prior art are the same. See In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed, Cir. 1990).
With respect to Claim 2, Kang ‘919 shows (Fig. 7-8) wherein an interval between the first surface and the third surface in the stacking direction is larger than an interval between the second surface and the fourth surface in the stacking direction.
With respect to Claim 3, Kang ‘919 shows (Fig. 7-8) wherein each of the first resin layer and the second resin layer is made of heat-curable resin.
With respect to Claim 4, Kang ‘919 shows (Fig. 7-8) wherein in the first chip stacked body, the plurality of first semiconductor chips are stacked such that a first stair portion is formed at a side surface facing the spacer, the first stair portion having a stair shape in which the first stair portion is further apart from the spacer at a position further apart from the second semiconductor chip.
With respect to Claim 5, Kang ‘919 shows (Fig. 7-8) wherein in the first chip stacked body, the plurality of first semiconductor chips are stacked such that a second stair portion is formed at a side surface on a side further apart from the spacer, the second stair portion having a stair shape in which the second stair portion is further apart from the spacer at a position further apart from the second semiconductor chip.
With respect to Claim 6, Kang ‘919 shows (Fig. 7-8) wherein the second semiconductor chip and the first resin layer are apart from the second stair portion in a plan view in which the second surface is viewed in the stacking direction.
With respect to Claim 7, Kang ‘919 shows (Fig. 7-8) further comprising a wire (2370) extending toward the second side from a surface of the second stair portion on the second side.
With respect to Claim 8, Kang ‘919 shows (Fig. 7-8) further comprising a second chip stacked body (2400) including the second semiconductor chip (2410B) and a plurality of third semiconductor chips (2410) stacked in the stacking direction on the second side of the second semiconductor chip
With respect to Claim 9, Kang ‘919 shows (Fig. 7-8) wherein in the first chip stacked body, the plurality of first semiconductor chips are stacked such that a first stair portion is formed at a side surface facing the spacer, the first stair portion having a stair shape in which the first stair portion is further apart from the spacer at a position further apart from the second semiconductor chip, and in the second chip stacked body, the second semiconductor chip and the plurality of third semiconductor chips are stacked such that a third stair portion is formed, the third stair portion having a stair shape having a second stair up-down direction intersecting a first stair up-down direction of the first stair portion.
With respect to Claim 10, Kang ‘919 shows (Fig. 7-8) wherein further comprising: a third resin layer (2250) provided on the first surface of the first chip stacked body; and a support substrate (2100) provided across a surface of the second resin layer (2565) on the first side and a surface of the third resin layer on the first side (see par 55 with respect to adhesive 250/2250).
With respect to Claim 16, Kang ‘193 teaches (Fig 2) wherein the first resin layer (72) is thicker than a fourth resin layer (73), the fourth resin layer being at least one resin layer provided between the plurality of first semiconductor chips.
With respect to Claim 20, Sano teaches (Fig 18) wherein a distance between the first surface and the fourth surface (upper surface of the spacer) along the stacking direction is greater than a distance between the first surface (lower surface of the first chip stacked body) and the second surface (upper surface of the first chip stacked body) along the stacking direction.
Claims 11-15, 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kang (US 2020/0126919) in view of Sano (US 2022/0285320) and in further view of Kang (US 11,569,193) and Nishimura US (2008/0150157).
With respect to Claim 11, Kang ‘919 shows (Fig. 7-8) most aspects of the current invention including a semiconductor device manufacturing method, comprising:
forming a first chip stacked body (2300) and a third resin layer (2250) on a principal surface of a support substrate (2100), the first chip stacked body including a plurality of first semiconductor chips (2310) stacked in a stacking direction (vertical), the first chip stacked body having a first surface (lower) and a second surface (upper) at respective ends on a first side and a second side in the stacking direction, and the third resin layer being provided between the first surface of the first chip stacked body and the principal surface (see par 55 with respect to adhesive 250/2250)
disposing a spacer (2550) at a position on the principal surface with a second resin layer (2565) interposed between the spacer and the principal surface, the spacer extending in the stacking direction and having a third surface (lower) and a fourth surface (upper) at the respective ends on the first side and the second side in the stacking direction, the position being apart from the first chip stacked body in a direction (horizontal) intersecting the stacking direction, and the second resin layer (2565) having a thickness with which a distance between the principal surface and the fourth surface is larger than a distance between the principal surface and the second surface
disposing a first resin layer (2430B), which is thinner than the second resin layer, and a second semiconductor chip (2410B) while performing heating across the second surface of the first chip stacked body and the fourth surface of the spacer such that the first resin layer is positioned between the second semiconductor chip and each of the spacer and the first chip stacked body
when the second semiconductor chip is disposed on the first chip stacked body and the spacer
Furthermore, Kang ‘919 shows wherein the first resin layer (2430B) and the second resin layer (2565) and the third resin layer (2250) are made of an adhesive or non-conductive film (NCF) and the second resin layer having a thickness larger than a thickness of the first resin layer.
However, Kang ‘919 does not explicitly disclose a thickness of a portion of the first resin layer that contacts with the fourth surface being smaller than a thickness of a portion of the first resin layer that contacts with the second surface, curing at least the first resin layer and the second resin layer by heating, wherein each of the first resin layer, the second resin layer, and the third resin layer is a die attach film and an elastic modulus of the second resin layer is lower than an elastic modulus of the first resin layer.
On the other hand, and in the same field of endeavor, Sano teaches (Fig 18) a semiconductor device manufacturing method, comprising forming a first chip stacked body including a plurality of first semiconductor chips (10) stacked in a stacking direction (vertical), forming a spacer (400) extending in the stacking direction, and positioned with respect to the first chip stacked body in a direction (horizontal) intersecting the stacking direction, forming a second semiconductor chip (500), the second semiconductor chip is thicker than at least one of the plurality of first semiconductor chips, a first resin layer (510) being positioned between the second semiconductor chip and each of the spacer and the first chip stacked body, wherein a thickness of a portion of the first resin layer that contacts with a fourth surface (upper surface of the spacer) being smaller than a thickness of a portion of the first resin layer that contacts with a second surface (upper surface of the first chip stacked body). Sano teaches this arrangement allows the desire to reduce a size of the package.
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have the arrangement of wherein a thickness of a portion of the first resin layer that contacts with the fourth surface being smaller than a thickness of a portion of the first resin layer that contacts with the second surface, and the second semiconductor chip is thicker than at least one of the plurality of first semiconductor chips in the device of Kang ‘919, as suggested by Sano because this arrangement allows the desire to reduce a size of the package.
However, Sano does not teach curing at least the first resin layer and the second resin layer by heating, wherein each of the first resin layer, the second resin layer, and the third resin layer is a die attach film and an elastic modulus of the second resin layer is lower than an elastic modulus of the first resin layer.
On the other hand, and in the same field of endeavor, Kang ‘193 teaches (Fig 2) a semiconductor device, comprising a first chip stacked body including a plurality of first semiconductor chips (T1) stacked in a stacking direction (vertical), a spacer (27) extending in the stacking direction, a second semiconductor chip (21), a first resin layer (72) provided across a second surface (lower) of the first chip stacked body and between the second semiconductor chip and the first chip stacked body, and a second resin layer (71) provided on a third surface (lower) of the spacer, wherein each of the first resin layer and the second resin layer is a die attach film. Kang ‘193 teaches using the first resin layer and the second resin layer as a die attach film to support the attachment of the plurality of first semiconductor chips in the chip stacked body and to support the attachment of the spacer to the semiconductor substrate.
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have wherein each of the first resin layer, the second resin layer, and the third resin layer is a die attach film in the device of Kang ‘919 and Sano, as suggested by Kang ‘193, which allows using the first resin layer to support the attachment of the plurality of first semiconductor chips in the chip stacked body and using the second resin layer to support the attachment of the spacer to the semiconductor substrate.
Furthermore, Kang ‘919 shows wherein the second resin layer having a thickness larger than a thickness of the first resin layer. Although Kang ‘919 in view of Sano and Kang ‘193 does not disclose an elastic modulus of the second resin layer is lower than an elastic modulus of the first resin layer, note that a limitation in a claim with respect to a material property in a claimed device does not differentiate the claimed device from prior-art device if the prior-art device teaches all the structural limitations in the claims. As stated in Best, where the claimed and prior art products are identical or substantially identical in structure or composition, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F. 2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977).
In the instant case, Kang ‘919 in view of Sano and Kang ‘193 teaches all structural limitations, similar to the instant invention. Accordingly, the structure of Kang ‘919 in view of Sano and Kang ‘193 is understood as also teaching an elastic modulus of the second resin layer is lower than an elastic modulus of the first resin layer at a temperature before curing.
Note that the applicant has a burden of proof once the examiner establishes a sound basis for believing that the products of the applicant and the prior art are the same. See In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed, Cir. 1990).
However, Kang ‘919 in view of Sano and Kang ‘193 does not teach curing at least the first resin layer and the second resin layer by heating.
On the other hand, and in the same field of endeavor, Nishimura teaches (Fig 45) a semiconductor device, comprising a second semiconductor chip (44) and a first resin layer (45) provided across a second surface of a first chip (42) and a second resin layer (43) provided on a first surface of the first chip, wherein the first resin layer and the second resin layer cured by heating (par 314, 374-377).
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have curing at least the first resin layer and the second resin layer by heating in the device of Kang ‘919 in view of Sano and Kang ‘193, because heat-curable resins are well-known in the semiconductor packaging art for their use as means to securely attach elements and/or components to a surface, as suggested by Nishimura, and applying a known method step for its conventional use/purpose would have been a common sense choice by one skilled in the semiconductor art. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007).
With respect to Claim 12, Kang ‘919 shows (Fig. 7-8) wherein in the disposing of the first resin layer and the second semiconductor chip, the third surface of the spacer is displaced toward the principal surface.
With respect to Claim 13, Kang ‘919 shows (Fig. 7-8) wherein the second resin layer having a thickness larger than a thickness of the first resin layer. Although Kang ‘919 in view of Sano and in further view of Kang ‘193 and Nishimura does not disclose wherein the elastic modulus of the second resin layer when the third surface of the spacer is displaced closer to the principal surface is smaller than the elastic modulus of the first resin layer, note that a limitation in a claim with respect to a material property in a claimed device does not differentiate the claimed device from prior-art device if the prior-art device teaches all the structural limitations in the claims. As stated in Best, where the claimed and prior art products are identical or substantially identical in structure or composition, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F. 2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977).
In the instant case, Kang ‘919 in view of Sano and in further view of Kang ‘193 and Nishimura teaches all structural limitations, similar to the instant invention. Accordingly, the structure of Kang ‘919 in view of Sano and in further view of Kang ‘193 and Nishimura is understood as also teaching wherein the elastic modulus of the second resin layer when the third surface of the spacer is displaced closer to the principal surface is smaller than the elastic modulus of the first resin layer.
Note that the applicant has a burden of proof once the examiner establishes a sound basis for believing that the products of the applicant and the prior art are the same. See In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed, Cir. 1990).
With respect to Claim 14, Kang ‘919 shows (Fig. 7-8) wherein the second resin layer having a thickness larger than a thickness of the first resin layer. Although Kang ‘919 in view of Sano and in further view of Kang ‘193 and Nishimura does not disclose wherein the elastic modulus of the second resin layer is smaller than the elastic modulus of the first resin layer before the curing, note that a limitation in a claim with respect to a material property in a claimed device does not differentiate the claimed device from prior-art device if the prior-art device teaches all the structural limitations in the claims. As stated in Best, where the claimed and prior art products are identical or substantially identical in structure or composition, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F. 2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977).
In the instant case, Kang ‘919 in view of Sano and in further view of Kang ‘193 and Nishimura teaches all structural limitations, similar to the instant invention. Accordingly, the structure of Kang ‘919 in view of Sano and in further view of Kang ‘193 and Nishimura is understood as also teaching wherein the elastic modulus of the second resin layer is smaller than the elastic modulus of the first resin layer before the curing.
Note that the applicant has a burden of proof once the examiner establishes a sound basis for believing that the products of the applicant and the prior art are the same. See In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed, Cir. 1990).
With respect to Claim 15, Kang ‘919 shows (Fig. 7-8) wherein the second resin layer having a thickness larger than a thickness of the first resin layer. Although Kang ‘919 in view of Sano and in further view of Kang ‘193 and Nishimura does not disclose wherein a thickness of the second resin layer is larger than a sum of an upper limit value of tolerance of the first chip stacked body, an upper limit value of tolerance of the third resin layer, a lower limit value of tolerance of the spacer, and a lower limit value of tolerance of the second resin layer, note that a limitation in a claim with respect to a material property in a claimed device does not differentiate the claimed device from prior-art device if the prior-art device teaches all the structural limitations in the claims. As stated in Best, where the claimed and prior art products are identical or substantially identical in structure or composition, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F. 2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977).
In the instant case, Kang ‘919 in view of Sano and in further view of Kang ‘193 and Nishimura teaches all structural limitations, similar to the instant invention. Accordingly, the structure of Kang ‘919 in view of Sano and in further view of Kang ‘193 and Nishimura is understood as also teaching wherein a thickness of the second resin layer is larger than a sum of an upper limit value of tolerance of the first chip stacked body, an upper limit value of tolerance of the third resin layer, a lower limit value of tolerance of the spacer, and a lower limit value of tolerance of the second resin layer.
Note that the applicant has a burden of proof once the examiner establishes a sound basis for believing that the products of the applicant and the prior art are the same. See In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed, Cir. 1990).
With respect to Claim 17, Kang ‘193 teaches (Fig 2) wherein the first resin layer (72) is thicker than a fourth resin layer (73), the fourth resin layer being at least one resin layer provided between the plurality of first semiconductor chips.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Kang (US 2020/0126919) in view of Sano (US 2022/0285320) and in further view of Kang (US 11,569,193) and Takemoto (US 2019/0287939).
With respect to Claim 18, Kang ‘919 in view of Sano and Kang ‘193 shows most aspects of the present invention. Furthermore, Kang ‘919 shows (Fig. 7-8) wherein a thickness of a third resin layer (2250) provided on the first side of a fourth semiconductor chip (lowermost 310) is thicker than a thickness of a fourth resin layer, the fourth resin layer being at least one resin layer provided between the plurality of first semiconductor chips. However, the combination of references do not show wherein a thickness of a fourth semiconductor chip, which is the first semiconductor chip provided on the first side among the plurality of first semiconductor chips, is thicker than the others of the plurality of first semiconductor chips.
On the other hand, and in the same field of endeavor, Takemoto teaches (Fig 1) a semiconductor device, comprising a first chip stacked body (package 20 comprising chips CH2 in the lowermost portion of the stack) including a plurality of first semiconductor chips (CH2) stacked in a stacking direction (vertical), a second semiconductor chip (middlemost CH2), a first resin layer (middlemost DAF) provided across a second surface of the first chip stacked body and between the second semiconductor chip and the first chip stacked body, wherein a thickness of a fourth semiconductor chip (lowermost CH2), which is the first semiconductor chip provided on the first side (lower side) among the plurality of first semiconductor chips, is thicker than the others of the plurality of first semiconductor chips.
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have wherein a thickness of a fourth semiconductor chip, which is the first semiconductor chip provided on the first side among the plurality of first semiconductor chips, is thicker than the others of the plurality of first semiconductor chips in the device of Kang ‘919 in view of Sano and Kang ‘193, because chip stacking of a plurality of first semiconductor chips with various thicknesses are well-known in the semiconductor packaging art for their use as means to prevent one semiconductor chip from overlapping and blocking an electrode pad (bonding wire terminal) of another semiconductor chip in the stack, as suggested by Takemoto, and applying a known feature for its conventional use/purpose would have been a common sense choice by one skilled in the semiconductor art. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Kang (US 2020/0126919) in view of Sano (US 2022/0285320) and in further view of Kang (US 11,569,193), Nishimura US (2008/0150157) and Takemoto (US 2019/0287939).
With respect to Claim 19, Kang ‘919 in view of Sano and in further view of Kang ‘193 and Nishimura teach most aspects of the present invention. Furthermore, Kang ‘919 shows (Fig. 7-8) wherein a thickness of a third resin layer (2250) provided on the first side of a fourth semiconductor chip (lowermost 310) is thicker than a thickness of a fourth resin layer, the fourth resin layer being at least one resin layer provided between the plurality of first semiconductor chips. However, the combination of references do not show wherein a thickness of a fourth semiconductor chip, which is the first semiconductor chip provided on the first side among the plurality of first semiconductor chips, is thicker than the others of the plurality of first semiconductor chips.
On the other hand, and in the same field of endeavor, Takemoto teaches (Fig 1) a semiconductor device, comprising a first chip stacked body (package 20 comprising chips CH2 in the lowermost portion of the stack) including a plurality of first semiconductor chips (CH2) stacked in a stacking direction (vertical), a second semiconductor chip (middlemost CH2), a first resin layer (middlemost DAF) provided across a second surface of the first chip stacked body and between the second semiconductor chip and the first chip stacked body, wherein a thickness of a fourth semiconductor chip (lowermost CH2), which is the first semiconductor chip provided on the first side (lower side) among the plurality of first semiconductor chips, is thicker than the others of the plurality of first semiconductor chips.
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have wherein a thickness of a fourth semiconductor chip, which is the first semiconductor chip provided on the first side among the plurality of first semiconductor chips, is thicker than the others of the plurality of first semiconductor chips in the device of Kang ‘919 in view of Sano and in further view of Kang ‘193 and Nishimura, because chip stacking of a plurality of first semiconductor chips with various thicknesses are well-known in the semiconductor packaging art for their use as means to prevent one semiconductor chip from overlapping and blocking an electrode pad (bonding wire terminal) of another semiconductor chip in the stack, as suggested by Takemoto, and applying a known method step for its conventional use/purpose would have been a common sense choice by one skilled in the semiconductor art. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007).
Response to Arguments
Applicant’s amendments filed on April 24, 2026, with respect to claims 1-20 have been considered but are moot because the new ground of rejection provided above teaches the matters specifically challenged in the argument.
Conclusion
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/Q.A.B/ Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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