Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions Applicant’s election without traverse of Species I Modification I in the reply filed on 2/6/2026 FILLIN "Enter mail date of the reply." \* MERGEFORMAT is acknowledged. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. Claim s 1, 4, 7-9, 12, 13 are rejected under 35 U.S.C. 102 (a)(1) FILLIN "Insert either \“(a)(1)\” or \“(a)(2)\” or both. If paragraph (a)(2) of 35 U.S.C. 102 is applicable, use form paragraph 7.15.01.aia, 7.15.02.aia or 7.15.03.aia where applicable." \d "[ 2 ]" as being anticipated by Lee et al. US 20190131269 A1 (hereinafter referred to as Lee) . Regarding claim 1 , Lee teaches A packaged integrated circuit (“integrated fan-out package 11” para. 0039 FIG. 2) , comprising: a redistribution layer (“second redistribution layer structure RDL2” para. 0030) including a plurality of electrically conductive vias extending at least partially therethrough (“second redistribution layer structure RDL2” para. 0030), and a plurality of lower pads (“UBM pads 123” para. 0032) electrically connected to corresponding ones of the plurality of electrically conductive vias (“UBM pads 123” are electrically connected to the last layer of “second redistribution layer structure RDL2”) ; a semiconductor chip (“semiconductor chip 100” para. 0028) on the redistribution layer; and external connection terminals (“bumps 124” para. 0032) electrically contacting corresponding ones of the plurality of lower pads within the redistribution layer (“bumps 124 are formed respectively on the UBM pads 123” para. 0032); wherein each of the plurality of lower pads includes: ( i ) a lower under-bump metallization (UBM) layer in contact with a corresponding external connection terminal (flipping FIG. 2 180 degrees, the portion of “UBM pads 132” formed over the bottommost “polymer layer 120” corresponds to the lower UBM layer, drawn in annotated FIG. 2), and (ii) an upper UBM layer extending on and contacting the lower UBM layer (the portion of “UBM pads 123” embedded in the “polymer layer 120” correspond to the upper UBM layer); and wherein an upper surface of the lower UBM layer has a greater lateral width dimension relative to an upper surface of the upper UBM layer (the upper surface of the lower portion of “UBM pad 123” is under and extends past the opening in the “polymer layer 120” while the upper surface of the upper portion of “UBM pad 123” is within the opening on “polymer layer 120”), which contacts a corresponding electrically conductive via (the “UBM pads 123” are in electrical contact with corresponding bottommost via portions of “second redistribution layers 122”). Regarding claim 4 , Lee teaches t he packaged integrated circuit of Claim 1, wherein the upper surface of the upper UBM layer is planar (the upper surface of the upper portion of “UBM pad 123” is shown as substantially planar). Regarding claim 7 , Lee teaches the packaged integrated circuit of Claim 1, wherein a center of the upper UBM layer is vertically aligned to a center of the lower UBM layer (the centers of the upper and lower portion of “UBM pads 123” appear to be aligned). Regarding claim 8 , Lee teaches A packaged integrated circuit (“integrated fan-out package 11” para. 0039 FIG. 2), comprising: a redistribution layer (“second redistribution layer structure RDL2” para. 0030) including a plurality of conductive lines (line portions of “second redistribution layer structure RDL2” para. 0030) , a plurality of electrically conductive vias connected to the plurality of conductive lines (via portions of “second redistribution layer structure RDL2” ), a plurality of lower pads (“UBM pads 123” para. 0032) electrically connected to the plurality of electrically conductive vias (“UBM pads 123” are electrically connected to the last layer of “second redistribution layer structure RDL2”), and a plurality of redistribution insulating layers (“polymer layers 120” para. 0031) ; an integrated circuit chip (“semiconductor chip 100” para. 0028) on the redistribution layer; and a plurality of external connection terminals (“bumps 124” para. 0032) attached to the plurality of lower pads in the redistribution layer (“bumps 124 are formed respectively on the UBM pads 123” para. 0032); wherein each of the plurality of lower pads is embedded within a lowermost redistribution insulating layer (“UBM pads 123” are formed in an opening of the last “polymer layer 120”, FIG. 2) of the plurality of redistribution insulating layers, and extends between a corresponding one of the plurality of conductive vias and a corresponding one of the plurality of external connection terminals (“UBM pads 123” are between the via portion of “second redistribution layer structure RDL2” and the “bump 124”); wherein each of the plurality of lower pads comprises a lower under-bump metallization (UBM) layer that contacts one of the plurality of external connection terminals (flipping FIG. 2 180 degrees, the portion of “UBM pads 132” formed over the bottommost “polymer layer 120” corresponds to the lower UBM layer, drawn in annotated FIG. 2), and an upper UBM layer extending on the lower UBM layer (the portion of “UBM pads 123” embedded in the “polymer layer 120” correspond to the upper UBM layer); and wherein an upper surface of the lower UBM layer has a greater than or equivalent lateral width dimension relative to an upper surface of the upper UBM layer (the upper surface of the lower portion of “UBM pad 123” is under and extends past the opening in the “polymer layer 120” while the upper surface of the upper portion of “UBM pad 123” is within the opening on “polymer layer 120”). Regarding claim 9 , Lee teaches the packaged integrated circuit of claim 8, wherein a portion of the upper surface of the lower UBM layer is in contact with a lower surface of the upper UBM layer (lower and upper portions of “UBM pad 123” are in contact near the edge of the upper portion); and wherein a remaining portion of the upper surface of the lower UBM layer is in contact with at least one of the plurality of redistribution insulating layers (remaining upper surface of lower portion of “UBM pad 123” is shown in contact with the last “polymer layer 120”). Regarding claim 12 , Lee teaches the packaged integrated circuit of Claim 8, wherein when viewed from a cross-sectional perspective, an outer wall of the upper UBM layer is not vertically aligned with an outer wall of the upper surface of the lower UBM layer, but is disposed inward on the upper surface of the lower UBM layer to a greater extent than the outer wall of the upper surface of the lower UBM layer in a horizontal direction (the upper surface of the lower portion of “UBM pad 123” is under and extends past the opening in the “polymer layer 120” while the upper surface of the upper portion of “UBM pad 123” is within the opening on “polymer layer 120”). Regarding claim 13 , Lee teaches the packaged integrated circuit of Claim 8, wherein the upper UBM layer and the lower UBM layer are contiguous (lower and upper portions of “UBM pad 123” are continuously connected). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness . This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Lee. Regarding claim 5 , Lee teaches t he packaged integrated circuit of Claim 1 but fails to expressly teach wherein the upper surface of the upper UBM layer has a concave shape that is recessed in a direction of the corresponding external connection terminal. Nevertheless, the specification does not teach or suggest any reason or advantage of such a shape. Changes of shape are a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed UBM layer was significant. See MPEP 2144.IV Section B. Regarding claim 6 , Lee teaches t he packaged integrated circuit of Claim 1 but fails to expressly teach wherein a lateral width dimension of the upper surface of the upper UBM layer is greater than or equal to a maximum lateral width dimension of the corresponding external connection terminal. Nevertheless, the size of an external connection terminal such as a bump can be chosen based on the desired size of the conductive element to which it connects to on an external device. Also, the total current is proportional to the width of the external connection terminal. As a result of using smaller “bumps 124”, the width may be than the width of the upper surface of the upper portion of “UMB pads 123”. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the width of the “bumps 124” in Lee can be set based on the size of the conductive elements of an external device and of the desired current. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the external connection terminal. The width is a result effective variable that affects the possible current flowing through the external connection terminal to or from an external device. Claim s 2 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Lee as applied to claim 1 above, in view of Nakano US 20120139107 A1 (hereinafter referred to as Nakano). Regarding claim 2 , Lee teaches t he packaged integrated circuit of Claim 1 but fails to teach wherein the lower UBM layer has a sidewall that is slanted when viewed from a cross-sectional perspective such that a width of the lower UBM layer adjacent an interface with the corresponding external connection terminal is less than a width of the lower UBM layer adjacent an interface with the corresponding upper UBM layer. Nevertheless, Nakano teaches wherein the lower UBM layer has a sidewall that is slanted when viewed from a cross-sectional perspective (lower portion of “UBM layer 2” makes an angle less than 90 degrees with respect to the surface of “protective film 3”, para. 0039 annotated FIG. 2A) such that a width of the lower UBM layer adjacent an interface with the corresponding external connection terminal is less than a width of the lower UBM layer adjacent an interface with the corresponding upper UBM layer (surface of “UBM layer 2” in contact with “bump 6” is shown as wider than the surface in contact with the upper portion of “UBM layer 2” due to the contact angle, para. 0040 annotated FIG. 2). Lee and Nakano teach external connection terminals on UBM layers. The “UBM layer 2” makes a contact angle with the “protective film 3” of less than 90 degrees to reduce the possibility of removal of the “UBM layer 2” due to stress (para. 0041). The “UBM layer 2” is more reliable device performance is better guaranteed. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that having the side surface of the bottom of “UBM pads 132” in Lee with an angle as taught in Nakano reduces stress concentration between “UBM pads 132” and “polymer layer 120”. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the packaged integrated circuit in Lee with the UBM layer as taught in Nakano. When the lower UBM layer has a slanted side surface that reduces in width in a direction towards the external connection terminal, damage due to stress can be reduced. Regarding claim 3 , Lee teaches the packaged integrated circuit of Claim 1, wherein a lateral width dimension of the upper surface of the upper UBM layer is greater than the width of the lower UBM layer adjacent an interface with the corresponding external connection terminal. Nevertheless, Nakano teaches a “UBM layer 2” that makes a contact angle with the “protective film 3” of less than 90 degrees to reduce the possibility of removal of the “UBM layer 2” due to stress (para. 0041). It is further taught that “The smaller the contact angle between the UBM layer 2 and the first protective film 3 around the UBM layer 2, and the contact angle between the bump 6 and the UBM layer 2 around the bump 6 are formed, the greater the advantage of reducing removal can be expected.” (para. 0041). The examiner thus understands that the angle of the sidewall of “UBM layer 2” with respect to the lower surface of “protection layer 3” is a result effective variable: the smaller the angle, the less stress is concentrated between “UBM layer 2” and “ protective film 3”. A change of the angle is proportional to a change in the difference between widths of the upper surface and the lower surface of the lower “UBM layer 2”. At lower angles, the width of the lower surface of the lower “UBM layer 2” may be lesser than the width the upper surface of the upper “UBM layer 2”. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the sidewall angle of the “UBM layer 2” is a variable that affects the concentration of stress between “UBM layer 2” and “protection layer 3”. Smaller angles lead to less stress concentration, which can also lead to a smaller width of the lower surface of the lower portion of “UBM layer 2”. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the UBM layer in Lee with that of Nakano. The UBM layer in Nakano achieves a reduced stress and thus a reduced risk of removal of the layers. The reduction is increased by lowering the sidewall angle of the UBM layer. This also leads to a reduction in width of the lower UBM layer adjacent an interface with the corresponding external connection terminal. Claim s 14 - 18 are rejected under 35 U.S.C. 103 as being unpatentable over Lee, in view of Nakano US 20120139107 A1 (hereinafter referred to as Nakano). Regarding claim 14, Lee teaches A packaged integrated circuit (“integrated fan-out package 11” para. 0039 FIG. 2), comprising: a first redistribution layer (“second redistribution layer structure RDL2” para. 0030) including a plurality of first conductive lines (line portions of “second redistribution layer structure RDL2” para. 0030), a plurality of first conductive vias (via portions of “second redistribution layer structure RDL2”) electrically connected to corresponding ones of the plurality of first conductive lines, a plurality of first lower pads (“UBM pads 123” para. 0032) electrically connected to corresponding ones of the plurality of first conductive vias (“UBM pads 123” are electrically connected to the last layer of “second redistribution layer structure RDL2”), and a plurality of lower redistribution insulating layers (“polymer layers 120” para. 0031); a semiconductor chip (“semiconductor chip 100” para. 0028) on the first redistribution layer; connection structures (“integrated fan-out vias TIV”), which are arranged on the first redistribution layer and spaced apart from the semiconductor chip in a horizontal direction (“through integrated fan-out vias TIV are aside or around the semiconductor chip 100”, para. 0028); a second redistribution layer (“first redistribution layer 115” para. 0024) extending on the connection structures, said second redistribution layer including a plurality of second conductive lines (226) and a plurality of second conductive vias electrically connected to corresponding ones of the plurality of second conductive lines (“metal layers 116” include via portions and line portions as seen in FIG. 2); and a plurality of external connection terminals (“bumps 124” para. 0032) attached to the plurality of first lower pads of the first redistribution layer (“bumps 124 are formed respectively on the UBM pads 123” para. 0032); wherein each of the plurality of first lower pads extends within a lowermost lower redistribution insulating layer of the plurality of lower redistribution insulating layers (“UBM pads 123” are formed in an opening of the last “polymer layer 120”, FIG. 2), and between one of the plurality of first conductive vias and one of the plurality of external connection terminals (“UBM pads 123” are between the via portion of “second redistribution layer structure RDL2” and the “bump 124”, annotate FIG. 2); wherein each of the plurality of first lower pads includes a lower under-bump metallization (UBM) layer (flipping FIG. 2 180 degrees, the portion of “UBM pads 132” formed over the bottommost “polymer layer 120” corresponds to the lower UBM layer, drawn in annotated FIG. 2) provided in contact with one of the plurality of external connection terminals and an upper UBM layer disposed on the lower UBM layer (the portion of “UBM pads 123” embedded in the “polymer layer 120” correspond to the upper UBM layer) . However, Lee fails to teach wherein the lower UBM layer has a tapered shape with a downwardly decreasing horizontal width as measured between slanted sidewalls thereof; and wherein a first width, which is a horizontal width of the upper UBM layer, is equal to or less than a second width, which is a horizontal width of an upper surface of the lower UBM layer. Nevertheless, Nakano teaches the lower UBM layer has a tapered shape with a downwardly decreasing horizontal width as measured between slanted sidewalls thereof (lower portion of “UBM layer 2” makes an angle less than 90 degrees with respect to the surface of “protective film 3”, para. 0039 annotated FIG. 2A); and wherein a first width, which is a horizontal width of the upper UBM layer, is equal to or less than a second width, which is a horizontal width of an upper surface of the lower UBM layer (the upper portion of “UBM layer 2”, which is formed within the “ protective film 3”, is shown having a lesser width than the upper surface of the lower portion of “UBM layer 2” that extends under the “ protective film 3”). Lee and Nakano teach external connection terminals on UBM layers. The “UBM layer 2” makes a contact angle with the “protective film 3” of less than 90 degrees to reduce the possibility of removal of the “UBM layer 2” due to stress (para. 0041). The “UBM layer 2” is more reliable device performance is better guaranteed. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that having the side surface of the bottom of “UBM pads 132” in Lee with an angle as taught in Nakano reduces stress concentration between “UBM pads 132” and “polymer layer 120”. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the packaged integrated circuit in Lee with the UBM layer as taught in Nakano. When the lower UBM layer has a slanted side surface that reduces in width in a direction towards the external connection terminal, damage due to stress can be reduced. Regarding claim 15 , Lee, modified by Nakano, teach the packaged integrated circuit of Claim 14, but fail to expressly teach wherein the first width is equal to or greater than each of a third width, which is a horizontal width of a lower surface of the lower UBM layer, and a fourth width, which is a horizontal width of each of the plurality of external connection terminals. Nevertheless, Nakano teaches a “UBM layer 2” that makes a contact angle with the “protective film 3” of less than 90 degrees to reduce the possibility of removal of the “UBM layer 2” due to stress (para. 0041). It is further taught that “The smaller the contact angle between the UBM layer 2 and the first protective film 3 around the UBM layer 2, and the contact angle between the bump 6 and the UBM layer 2 around the bump 6 are formed, the greater the advantage of reducing removal can be expected.” (para. 0041). The examiner thus understands that the angle of the sidewall of “UBM layer 2” with respect to the lower surface of “protection layer 3” is a result effective variable: the smaller the angle, the less stress is concentrated between “UBM layer 2” and “ protective film 3”. A change of the angle is proportional to a change in the difference between widths of the upper surface and the lower surface of the lower “UBM layer 2”. At lower angles, the width of the lower surface of the lower “UBM layer 2” may be lesser than the width the upper surface of the upper “UBM layer 2”. Also, the size of an external connection terminal such as a bump can be chosen based on the desired size of the conductive element to which it connects to on an external device. Also, the total current is proportional to the width of the external connection terminal. As a result of using smaller “bumps 124”, the width may be than the width of the upper surface of the upper portion of “UMB pads 123 One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the sidewall angle of the “UBM layer 2” is a variable that affects the concentration of stress between “UBM layer 2” and “protection layer 3”. Smaller angles lead to less stress concentration, which can also lead to a smaller width of the lower surface of the lower portion of “UBM layer 2”. Furthermore. the width of the “bumps 124” in Lee can be set based on the size of the conductive elements of an external device and of the desired current. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the UBM layer in Lee with that of Nakano. The UBM layer in Nakano achieves a reduced stress and thus a reduced risk of removal of the layers. The reduction is increased by lowering the sidewall angle of the UBM layer. This also leads to a reduction in width of the lower UBM layer adjacent an interface with the corresponding external connection terminal. Regarding the width of the external connection terminal, the width is a result effective variable that affects the possible current flowing through the external connection terminal to or from an external device. Regarding claim 16 , Lee, modified by Nakano, teach the packaged integrated circuit of Claim 15, but fails to expressly teach wherein the second width and the third width are different from each other by about 5 micrometers to about 20 micrometers. Nevertheless, a change of the angle of the sidewall of “UBM layer 2” is proportional to a change in the difference between widths of the upper surface and the lower surface of the lower “UBM layer 2”. At lower angles, the width of the lower surface of the lower “UBM layer 2” may be lesser than the width the upper surface of the upper “UBM layer 2”. Nakano teaches that “The smaller the contact angle between the UBM layer 2 and the first protective film 3 around the UBM layer 2, and the contact angle between the bump 6 and the UBM layer 2 around the bump 6 are formed, the greater the advantage of reducing removal can be expected.” (para. 0041). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the “UBM layer 2” sidewall angle is a result effective variable that determines the reduction of stress between “UBM layer 2” and “protection layer 3”. The choice of sidewall angle will affect the difference in width between the upper and lower surfaces of the lower UBM layer. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention t hat the difference between the second and third width is a result of the desired contact angle between the UBM layer and the lowest insulating layer. The angle of the sidewall determines the reduction in removal of the UBM layer due to stress. Regarding claim 17 , Lee, modified by Nakano, teach t he packaged integrated circuit of Claim 14, wherein an upper surface of the upper UBM layer has a flat shape or a concave shape that is recessed in a vertical downward direction toward at least one of the plurality of external connection terminals (upper surface of “UBM layer 2” is shown having a substantially flat shape). Regarding claim 18 , Lee, modified by Nakano, teach the packaged integrated circuit of Claim 14, wherein a lower surface of the upper UBM layer is entirely in direct contact with the upper surface of the lower UBM layer (the entire lower surface of the upper portion of “UBM layer 2” is in contact with the upper surface of the lower portion of “UBM layer 2”). Regarding claim 19 , Lee, modified by Nakano, teach the packaged integrated circuit of Claim 18 but fails to expressly teach wherein the first width ranges from about 150 micrometers to about 250 micrometers; and wherein the upper UBM layer has a height of about 2 micrometers to about 8 micrometers. Nevertheless, the width of the upper portion of the UBM layer is subject to the size of the opening formed in “polymer layer 120” of Lee, or “protective film 3” of Nakano. This can help determine the overall width of the UBM layer and size of the external connection terminal. The height is a consequence of filling the opening with UBM layer material: the upper portion of “UBM pad 123” in Lee and “UBM layer 2” in Nakano have a thickness equal to the depth of the opening in respective insulating layers. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the dimensions of the upper UBM layer depend on the size of the opening in the last insulating layer of the redistribution layer. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention t hat the upper UBM layer will have a width of the corresponding opening in the insulating layer and a thickness of the depth of the opening. The size of the opening, and therefore the upper UBM layer, can be set based on the desired overall width of the UBM layer for accommodating the external connection terminal. Furthermore, the claimed dimensions The instant application specification contains no disclosure of either the critical nature of the claimed widths and thicknesses, i.e., “ wherein the first width ranges from about 150 micrometers to about 250 micrometers; and wherein the upper UBM layer has a height of about 2 micrometers to about 8 micrometers ” or of any unexpected results arising therefrom. Applicant has not disclosed that having such thickness and width solves any stated problem or is for any particular purpose. "Where the issue of criticality is involved, the applicant has the burden of establishing his position by a proper showing of the facts upon which he relies." - In re Scherl , 156 F.2d 72, 74-75, 70 USPQ 204, 205 (CCPA 1946), see MPEP 2144.05.III.A. Where patentability is said to be based upon particular chosen dimensions, alignment, positioning, or upon another variable recited in a claim, the applicant must show that the chosen dimension are critical ( In re Woodruff , 919 F.2d 1575, 1578 (Fed. Cir. 1990).). In view of the above, inter alia, the limitation of “ wherein the first width ranges from about 150 micrometers to about 250 micrometers; and wherein the upper UBM layer has a height of about 2 micrometers to about 8 micrometers ” is not patentable over Lee, in view of Nakano. Regarding claim 20 , Lee, modified by Nakano, teach the packaged integrated circuit of Claim 14, wherein the connection structures each include one selected from a through-mold via (TMV), conductive solder, a conductive pillar, and a conductive bump (“ through integrated fan-out vias TIV ” are copper structures that resemble pillars or through-mold vias) . Allowable Subject Matter Claim s 10 and 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 10, the most relevant prior art Chen et al. US 20160079191 A1 teaches a seed layer formed before formation of the UBM layer. An upper layer of the UBM layer is covered by the seed layer. Chen fails to teach or render obvious and wherein a sidewall of the upper UBM layer is in contact with at least one of the plurality of redistribution insulating layers. Therefore, claim 10 is considered allowable. Regarding claim 11, t he most relevant prior art Chen et al. US 20200083189 A1 teaches a seed layer provided over a via portion of a redistribution metal layer. Chen and Lee teach the formation of a redistribution layer built up in the direction away from the semiconductor chip, such that each redistribution line and via will have a seed layer formed above. As such, Lee and Chen fail to teach or render obvious wherein a seed layer is provided on a sidewall and on a lower surface of an electrically conductive via extending on the upper UBM layer. Therefore, claim 11 is considered allowable. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT ERIC MULERO FLORES whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-0070 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Mon-Fri 8am-5pm (typically) . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Julio Maldonado can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT (571)272-1864 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ERIC MANUEL MULERO FLORES/ Examiner, Art Unit 2898 /JULIO J MALDONADO/ Supervisory Patent Examiner, Art Unit 2898