Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicants’ amendments filed 6/22/2026 have been entered and considered. The amendments to claims 1, 8, and 14 are acknowledged.
Response to Arguments
Applicant’s arguments with respect to claims 1, 8, and 14 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-9, 12-20 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. US 20210391304 A1 (hereinafter referred to as Wang), in view of Nakano US 20120139107 A1 (hereinafter referred to as Nakano).
Regarding claim 1, Wang teaches
A packaged integrated circuit (“semiconductor device 200”, para. 0014 FIG. 2), comprising:
a redistribution layer (“redistribution structure 105” para. 0012) including a plurality of electrically conductive vias extending at least partially therethrough (“redistribution structure 105” is understood to be like any one of the embodiments from FIG. 5-62, such as FIG. 6, para. 0008. FIG. 6 shows “redistribution structure 105” including “via portions 601V”, para. 0044), and a plurality of lower pads (“bump portions 601B” para. 0044) electrically connected to corresponding ones of the plurality of electrically conductive vias (“via portions 601V” and connected to “bump portions 601B”);
a semiconductor chip (“integrated circuit die 201” para. 0014 FIG. 2) on the redistribution layer; and
external connection terminals (“connectors 603”, para. 0004) and electrically contacting corresponding ones of the plurality of lower pads within the redistribution layer (“connectors 603” are formed on “UBMs 601”, para. 0044);
However, Wang fails to teach wherein each of the plurality of lower pads includes: (i) a lower under-bump metallization (UBM) layer in contact with a corresponding external connection terminal, and (ii) an upper UBM layer extending on and contacting the lower UBM layer; and wherein an upper surface of the lower UBM layer has a greater lateral width dimension relative to an upper surface of the upper UBM layer, which directly contacts a corresponding electrically conductive via.
Nevertheless, Nakano teaches
wherein each of the plurality of lower pads (“under barrier metal layer (UBM) 2” para. 0038 FIG. 2A) includes: (i) a lower under-bump metallization (UBM) layer (turning FIG. 2A around, the lower layer of “UBM layer 2” is the layer below “first protective film 3”) in contact with a corresponding external connection terminal (“bump 6” para. 0038), and (ii) an upper UBM layer extending on and contacting the lower UBM layer (layer of “UBM layer 2” in opening of “first protective film 3” extends along the upper surface of the lower layer of “UBM layer 2”); and
wherein an upper surface of the lower UBM layer has a greater lateral width dimension relative to an upper surface of the upper UBM layer (the lower surface of the lower layer of “UBM layer 2” extends further outward away from the center than the upper surface of the upper layer of “UBM layer 2”, which is inside the opening of “first protective film 3”).
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Wang and Nakano teach external connection terminals on UBM layers. “UBM layer 2” covers an edge of “protective film 3”, which is made of silicon nitride such that it helps reduce the chance of removal of layers under pressure (para. 0041). Furthermore, the “UBM layer 2” makes a contact angle with the “protective film 3” of less than 90 degrees to further reduce the possibility of removal of the “UBM layer 2” due to stress (para. 0041). The “UBM layer 2” is more reliable and device performance is better guaranteed. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that having the “bump portion 601B” with a lower layer wider than an upper layer and side surface of the “bump portion 601B” with an angle as taught in Nakano reduces the risk of removal of “bump portion 601B” under stress.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the packaged integrated circuit in Wang with the UBM layer as taught in Nakano. A UBM layer with a lower layer having greater lateral width than an upper layer and with the lower UBM layer having a slanted side surface, damage due to stress can be reduced. The protective film overlapping the upper surface of the lower layer also helps reduce the possibility of layer removal.
Wang, modified by Nakano, further teaches
The upper surface of the upper UBM layer, which directly contacts a corresponding electrically conductive via (upper surface of upper layer of “UBM layer 2” from Nakano is in contact with “via portion 601V” in Wang).
Regarding claim 2, Wang, modified by Nakano, teach the packaged integrated circuit of Claim 1, wherein the lower UBM layer has a sidewall that is slanted when viewed from a cross-sectional perspective (lower portion of “UBM layer 2” makes an angle less than 90 degrees with respect to the surface of “protective film 3”, para. 0039 annotated FIG. 2A) such that a width of the lower UBM layer adjacent an interface with the corresponding external connection terminal is less than a width of the lower UBM layer adjacent an interface with the corresponding upper UBM layer (surface of “UBM layer 2” in contact with “bump 6” is shown as wider than the surface in contact with the upper portion of “UBM layer 2” due to the contact angle, para. 0040 annotated FIG. 2).
Regarding claim 3, Wang, modified by Nakano, teach the packaged integrated circuit of Claim 1, but fail to expressly teach wherein a lateral width dimension of the upper surface of the upper UBM layer is greater than the width of the lower UBM layer adjacent an interface with the corresponding external connection terminal.
Nevertheless, Nakano teaches a “UBM layer 2” that makes a contact angle with the “protective film 3” of less than 90 degrees to reduce the possibility of removal of the “UBM layer 2” due to stress (para. 0041). It is further taught that “The smaller the contact angle between the UBM layer 2 and the first protective film 3 around the UBM layer 2, and the contact angle between the bump 6 and the UBM layer 2 around the bump 6 are formed, the greater the advantage of reducing removal can be expected.” (para. 0041). The examiner thus understands that the angle of the sidewall of “UBM layer 2” with respect to the lower surface of “protection layer 3” is a result effective variable: the smaller the angle, the less stress is concentrated between “UBM layer 2” and “protective film 3”. A change of the angle is proportional to a change in the difference between widths of the upper surface and the lower surface of the lower “UBM layer 2”. At lower angles, the width of the lower surface of the lower “UBM layer 2” may be lesser than the width the upper surface of the upper “UBM layer 2”. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the sidewall angle of the “UBM layer 2” is a variable that affects the concentration of stress between “UBM layer 2” and “protection layer 3”. Smaller angles lead to less stress concentration, which can also lead to a smaller width of the lower surface of the lower portion of “UBM layer 2”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the reduction of stress is increased by lowering the sidewall angle of the UBM layer. This also leads to a reduction in width of the lower UBM layer adjacent an interface with the corresponding external connection terminal.
Regarding claim 4, Wang, modified by Nakano, teach the packaged integrated circuit of Claim 1, wherein the upper surface of the upper UBM layer is planar (the upper surface of the upper portion of “UBM layer 2” is shown as substantially planar).
Regarding claim 5, Wang, modified by Nakano, teach the packaged integrated circuit of Claim 1 but fails to expressly teach wherein the upper surface of the upper UBM layer has a concave shape that is recessed in a direction of the corresponding external connection terminal.
Nevertheless, the specification does not teach or suggest any reason or advantage of such a shape. Changes of shape are a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed UBM layer was significant. See MPEP 2144.IV Section B.
Regarding claim 6, Wang, modified by Nakano, teach the packaged integrated circuit of Claim 1 but fails to expressly teach wherein a lateral width dimension of the upper surface of the upper UBM layer is greater than or equal to a maximum lateral width dimension of the corresponding external connection terminal.
Nevertheless, the size of an external connection terminal such as a bump can be chosen based on the desired size of the conductive element to which it connects to on an external device. Also, the total current is proportional to the width of the external connection terminal. As a result of using smaller “connectors 603”, the width may be smaller than the width of the upper surface of the upper portion of “bump portion 601B”, now modified as “UBM layer 2” in Nakano. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the width of the “connectors 603” in Wang can be set based on the size of the conductive elements of an external device and of the desired current.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the external connection terminal. The width is a result effective variable that affects the possible current flowing through the external connection terminal to or from an external device and also depends on the size of the terminals of device to which connection is made.
Regarding claim 7, Wang, modified by Nakano, teach the packaged integrated circuit of Claim 1, wherein a center of the upper UBM layer is vertically aligned to a center of the lower UBM layer (the centers of the upper and lower portion of “UBM layer 2” appear to be substantially aligned).
Regarding claim 8, Wang teaches
A packaged integrated circuit (“semiconductor device 200”, para. 0014 FIG. 2), comprising:
a redistribution layer (“redistribution structure 105” para. 0012) including a plurality of conductive lines (“redistribution structure 105” is understood to be like any one of the embodiments from FIG. 5-62, such as FIG. 6, para. 0008. FIG. 6 shows “metallization patterns 505, 509, 513 and 517” in “redistribution layer 105” that includes lines, para. 0031, 0038-0040), a plurality of electrically conductive vias (“via portions 601V” para. 0044) connected to the plurality of conductive lines (“via portions 601V” couple to “metallization pattern 517”, para. 0044), a plurality of lower pads (“bump portions 601B” para. 0044) electrically connected to the plurality of electrically conductive vias (“via portions 601V” and connected to “bump portions 601B”), and a plurality of redistribution insulating layers (“insulating layers 503, 507, 511, 515 and 519” para. 0031);
an integrated circuit chip (“integrated circuit die 201” para. 0014 FIG. 2) on the redistribution layer; and
a plurality of external connection terminals (“connectors 603”, para. 0044) attached to the plurality of lower pads in the redistribution layer (“connectors 603” are formed on the “UBMs 601” para. 0044);
each of the plurality of lower pads extends between a corresponding one of the plurality of conductive vias and a corresponding one of the plurality of external connection terminals (“bump portions 601B” extend between “via portions 601V” and “connectors 603”);
However, Wang fails to teach wherein each of the plurality of lower pads is embedded within a lowermost redistribution insulating layer of the plurality of redistribution insulating layers, wherein each of the plurality of lower pads comprises a lower under-bump metallization (UBM) layer that contacts one of the plurality of external connection terminals, and an upper UBM layer extending on the lower UBM layer, the upper UBM layer in direct contact with the corresponding one of the plurality of conductive vias; and wherein an upper surface of the lower UBM layer has a greater than or equivalent lateral width dimension relative to an upper surface of the upper UBM layer.
Nevertheless, Nakano teaches
wherein each of the plurality of lower pads (“under barrier metal layer (UBM) 2” para. 0038 FIG. 2A) is embedded within a lowermost redistribution insulating layer (“first protective film 3” para. 0038) of the plurality of redistribution insulating layers,
wherein each of the plurality of lower pads comprises a lower under-bump metallization (UBM) layer (turning FIG. 2A around, the lower layer of “UBM layer 2” is the layer below “first protective film 3”) that contacts one of the plurality of external connection terminals (“bump 6” para. 0038), and an upper UBM layer extending on the lower UBM layer (layer of “UBM layer 2” in opening of “first protective film 3” extends along the upper surface of the lower layer of “UBM layer 2”),
wherein an upper surface of the lower UBM layer has a greater than or equivalent lateral width dimension relative to an upper surface of the upper UBM layer (the lower surface of the lower layer of “UBM layer 2” extends further outward away from the center than the upper surface of the upper layer of “UBM layer 2”, which is inside the opening of “first protective film 3”).
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Wang and Nakano teach external connection terminals on UBM layers. “UBM layer 2” covers an edge of “protective film 3”, which is made of silicon nitride such that it helps reduce the chance of removal of layers under pressure (para. 0041). Furthermore, the “UBM layer 2” makes a contact angle with the “protective film 3” of less than 90 degrees to further reduce the possibility of removal of the “UBM layer 2” due to stress (para. 0041). The “UBM layer 2” is more reliable and device performance is better guaranteed. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that having the “bump portion 601B” with a lower layer wider than an upper layer and side surface of the “bump portion 601B” with an angle as taught in Nakano reduces the risk of removal of “bump portion 601B” under stress.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the packaged integrated circuit in Wang with the UBM layer as taught in Nakano. A UBM layer with a lower layer having greater lateral width than an upper layer and with the lower UBM layer having a slanted side surface, damage due to stress can be reduced. The protective film overlapping the upper surface of the lower layer also helps reduce the possibility of layer removal.
Wang, modified by Nakano, further teaches
the upper UBM layer in direct contact with the corresponding one of the plurality of conductive vias (upper surface of upper layer of “UBM layer 2” from Nakano is in contact with “via portion 601V” in Wang).
Regarding claim 9, Wang, modified by Nakano, teach the packaged integrated circuit of Claim 8wherein a portion of the upper surface of the lower UBM layer is in contact with a lower surface of the upper UBM layer (upper surface of lower portion of “UBM layer 2” is in contact with the lower surface of the upper portion of “UBM layer 2”); and wherein a remaining portion of the upper surface of the lower UBM layer is in contact with at least one of the plurality of redistribution insulating layers (part of the upper surface of the lower portion of “UBM layer 2” is in contact with “first protective film 3”).
Regarding claim 12, Wang, modified by Nakano, teach the packaged integrated circuit of Claim 8, wherein when viewed from a cross-sectional perspective, an outer wall of the upper UBM layer is not vertically aligned with an outer wall of the upper surface of the lower UBM layer, but is disposed inward on the upper surface of the lower UBM layer to a greater extent than the outer wall of the upper surface of the lower UBM layer in a horizontal direction (sidewalls of upper layer of “UBM layer 2” are within the opening of “protective film 3” while to sidewall of the lower layer of “UBM layer 2” extends outwards beyond the width of the opening of “protective film 3”).
Regarding claim 13, Wang, modified by Nakano, teach the packaged integrated circuit of Claim 8, wherein the upper UBM layer and the lower UBM layer are contiguous (the upper and lower layers of “UBM layer 2” are continuously connected).
Regarding claim 14, Wang teaches
A packaged integrated circuit (“semiconductor device 400”, para. 0027 FIG. 4), comprising:
a first redistribution layer (“redistribution structure 105” para. 0012) including a plurality of first conductive lines (“redistribution structure 105” is understood to be like any one of the embodiments from FIG. 5-62, such as FIG. 6, para. 0008. FIG. 6 shows “metallization patterns 505, 509, 513 and 517” in “redistribution layer 105” that includes lines, para. 0031, 0038-0040), a plurality of first conductive vias (“via portions 601V” para. 0044) electrically connected to corresponding ones of the plurality of first conductive lines (“via portions 601V” couple to “metallization pattern 517”, para. 0044), a plurality of first lower pads (“bump portions 601B” para. 0044) electrically connected to corresponding ones of the plurality of first conductive vias (“via portions 601V” and connected to “bump portions 601B”), and a plurality of redistribution insulating layers (“insulating layers 503, 507, 511, 515 and 519” para. 0031);
a semiconductor chip (“integrated circuit die 407A” para. 0028 FIG. 4) on the first redistribution layer;
connection structures (“through vias (TVs) 405”, para. 0044), which are arranged on the first redistribution layer and spaced apart from the semiconductor chip in a horizontal direction (“TVs 405” are formed on “redistribution layer 105” and spaced away laterally from “integrated circuit die 407A”);
a second redistribution layer (“backside structure 409” para. 0029) extending on the connection structures, said second redistribution layer including a plurality of second conductive lines and a plurality of second conductive vias electrically connected to corresponding ones of the plurality of second conductive lines (“backside structure 409 is a redistribution structure comprising a plurality of insulating and conductive layers (not individually shown)” para. 0029. Redistribution structures are known to have lines and vias, such as “redistribution structure 105”); and
a plurality of external connection terminals (“connectors 603”, para. 0044) attached to the plurality of first lower pads of the first redistribution layer (“connectors 603” are formed on the “UBMs 601” para. 0044); wherein each of the plurality of first lower pads extends between one of the plurality of first conductive vias and one of the plurality of external connection terminals (“bump portions 601B” extend between “via portions 601V” and “connectors 603”).
However, Wang fails to teach wherein each of the plurality of first lower pads extends within a lowermost lower redistribution insulating layer of the plurality of lower redistribution insulating layers, wherein each of the plurality of first lower pads includes a lower under-bump metallization (UBM) layer provided in contact with one of the plurality of external connection terminals and an upper UBM layer disposed on the lower UBM layer, the upper UBM layer being in direct contact with the respective one of the plurality of first conductive vias; wherein the lower UBM layer has a tapered shape with a downwardly decreasing horizontal width as measured between slanted sidewalls thereof; and wherein a first width, which is a horizontal width of the upper UBM layer, is equal to or less than a second width, which is a horizontal width of an upper surface of the lower UBM layer.
Nevertheless, Nakano teaches
wherein each of the plurality of first lower pads (“under barrier metal layer (UBM) 2” para. 0038 FIG. 2A) extends within a lowermost lower redistribution insulating layer (“first protective film 3” para. 0038) of the plurality of lower redistribution insulating layers,
wherein each of the plurality of first lower pads includes a lower under-bump metallization (UBM) layer (turning FIG. 2A around, the lower layer of “UBM layer 2” is the layer below “first protective film 3”) provided in contact with one of the plurality of external connection terminals (“bump 6” para. 0038) and an upper UBM layer (upper layer of “UBM layer 2”) disposed on the lower UBM layer,
wherein the lower UBM layer has a tapered shape with a downwardly decreasing horizontal width as measured between slanted sidewalls thereof (lower portion of “UBM layer 2” makes an angle less than 90 degrees with respect to the surface of “protective film 3”, para. 0039 annotated FIG. 2A); and
wherein a first width, which is a horizontal width of the upper UBM layer, is equal to or less than a second width, which is a horizontal width of an upper surface of the lower UBM layer (sidewalls of upper layer of “UBM layer 2” are within the opening of “protective film 3” while to sidewall of the lower layer of “UBM layer 2” extends outwards beyond the width of the opening of “protective film 3”. As such, the width of the upper layer of “UBM layer 2” is understood to be less than the width of the lower layer of “UBM layer 2”.).
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Wang and Nakano teach external connection terminals on UBM layers. “UBM layer 2” covers an edge of “protective film 3”, which is made of silicon nitride such that it helps reduce the chance of removal of layers under pressure (para. 0041). Furthermore, the “UBM layer 2” makes a contact angle with the “protective film 3” of less than 90 degrees to further reduce the possibility of removal of the “UBM layer 2” due to stress (para. 0041). The “UBM layer 2” is more reliable and device performance is better guaranteed. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that having the “bump portion 601B” with a lower layer wider than an upper layer and side surface of the “bump portion 601B” with an angle as taught in Nakano reduces the risk of removal of “bump portion 601B” under stress.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the packaged integrated circuit in Wang with the UBM layer as taught in Nakano. A UBM layer with a lower layer having greater lateral width than an upper layer and with the lower UBM layer having a slanted side surface, damage due to stress can be reduced. The protective film overlapping the upper surface of the lower layer also helps reduce the possibility of layer removal.
Wang, modified by Nakano, further teaches
the upper UBM layer being in direct contact with the respective one of the plurality of first conductive vias (upper surface of upper layer of “UBM layer 2” from Nakano is in contact with “via portion 601V” in Wang).
Regarding claim 15, Wang, modified by Nakano, teach the packaged integrated circuit of Claim 14, but fail to expressly teach wherein the first width is equal to or greater than each of a third width, which is a horizontal width of a lower surface of the lower UBM layer, and a fourth width, which is a horizontal width of each of the plurality of external connection terminals.
Nevertheless, Nakano teaches a “UBM layer 2” that makes a contact angle with the “protective film 3” of less than 90 degrees to reduce the possibility of removal of the “UBM layer 2” due to stress (para. 0041). It is further taught that “The smaller the contact angle between the UBM layer 2 and the first protective film 3 around the UBM layer 2, and the contact angle between the bump 6 and the UBM layer 2 around the bump 6 are formed, the greater the advantage of reducing removal can be expected.” (para. 0041). The examiner thus understands that the angle of the sidewall of “UBM layer 2” with respect to the lower surface of “protection layer 3” is a result effective variable: the smaller the angle, the less stress is concentrated between “UBM layer 2” and “protective film 3”. A change of the angle is proportional to a change in the difference between widths of the upper surface and the lower surface of the lower “UBM layer 2”. At lower angles, the width of the lower surface of the lower “UBM layer 2” may be lesser than the width the upper surface of the upper “UBM layer 2”. Also, the size of an external connection terminal such as a bump can be chosen based on the desired size of the conductive element to which it connects to on an external device. Also, the total current is proportional to the width of the external connection terminal. As a result of using smaller “connectors 603”, the width may smaller be than the width of the upper surface of the upper portion of “bump portions 601B”, modified to be “UBM layer 2”. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the sidewall angle of the “UBM layer 2” is a variable that affects the concentration of stress between “UBM layer 2” and “protection layer 3”. Smaller angles lead to less stress concentration, which can also lead to a smaller width of the lower surface of the lower portion of “UBM layer 2”. Furthermore, the width of the “connectors 603” in Wang can be set based on the size of the conductive elements of an external device and of the desired current.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the UBM layer in Wang with that of Nakano. The UBM layer in Nakano achieves a reduced stress and thus a reduced risk of removal of the layers. The reduction is increased by lowering the sidewall angle of the UBM layer. This also leads to a reduction in width of the lower UBM layer adjacent an interface with the corresponding external connection terminal. Regarding the width of the external connection terminal, the width is a result effective variable that affects the possible current flowing through the external connection terminal to or from an external device.
Regarding claim 16, Wang, modified by Nakano, teach the packaged integrated circuit of Claim 15, but fails to expressly teach wherein the second width and the third width are different from each other by about 5 micrometers to about 20 micrometers.
Nevertheless, a change of the angle of the sidewall of “UBM layer 2” is proportional to a change in the difference between widths of the upper surface and the lower surface of the lower “UBM layer 2”. At lower angles, the width of the lower surface of the lower “UBM layer 2” may be lesser than the width the upper surface of the upper “UBM layer 2”. Nakano teaches that “The smaller the contact angle between the UBM layer 2 and the first protective film 3 around the UBM layer 2, and the contact angle between the bump 6 and the UBM layer 2 around the bump 6 are formed, the greater the advantage of reducing removal can be expected.” (para. 0041). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the “UBM layer 2” sidewall angle is a result effective variable that determines the reduction of stress between “UBM layer 2” and “protection layer 3”. The choice of sidewall angle will affect the difference in width between the upper and lower surfaces of the lower UBM layer.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the difference between the second and third width is a result of the desired contact angle between the UBM layer and the lowest insulating layer. The angle of the sidewall determines the reduction in removal of the UBM layer due to stress.
Regarding claim 17, Wang, modified by Nakano, teach the packaged integrated circuit of Claim 14, wherein an upper surface of the upper UBM layer has a flat shape or a concave shape that is recessed in a vertical downward direction toward at least one of the plurality of external connection terminals (upper surface of “UBM layer 2” is shown having a substantially flat shape).
Regarding claim 18, Wang, modified by Nakano, teach the packaged integrated circuit of Claim 14, wherein a lower surface of the upper UBM layer is entirely in direct contact with the upper surface of the lower UBM layer (the entire lower surface of the upper portion of “UBM layer 2” is in contact with the upper surface of the lower portion of “UBM layer 2”).
Regarding claim 19, Wang, modified by Nakano, teach the packaged integrated circuit of Claim 18 but fails to expressly teach wherein the first width ranges from about 150 micrometers to about 250 micrometers; and wherein the upper UBM layer has a height of about 2 micrometers to about 8 micrometers.
Nevertheless, the width of the upper portion of the UBM layer is subject to the size of the opening formed in “protective film 3” of Nakano. This can help determine the overall width of the UBM layer and size of the external connection terminal. The height is a consequence of filling the opening with UBM layer material: the upper portion of “UBM layer 2” in Nakano has a thickness equal to the depth of the opening in respective insulating layers. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the dimensions of the upper UBM layer depend on the size of the opening in the last insulating layer of the redistribution layer.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the upper UBM layer will have a width of the corresponding opening in the insulating layer and a thickness of the depth of the opening. The size of the opening, and therefore the upper UBM layer, can be set based on the desired overall width of the UBM layer for accommodating the external connection terminal.
Furthermore, the instant application specification contains no disclosure of either the critical nature of the claimed widths and thicknesses, i.e., “wherein the first width ranges from about 150 micrometers to about 250 micrometers; and wherein the upper UBM layer has a height of about 2 micrometers to about 8 micrometers” or of any unexpected results arising therefrom. Applicant has not disclosed that having such thickness and width solves any stated problem or is for any particular purpose. "Where the issue of criticality is involved, the applicant has the burden of establishing his position by a proper showing of the facts upon which he relies." - In re Scherl, 156 F.2d 72, 74-75, 70 USPQ 204, 205 (CCPA 1946), see MPEP 2144.05.III.A.
Where patentability is said to be based upon particular chosen dimensions, alignment, positioning, or upon another variable recited in a claim, the applicant must show that the chosen dimension are critical (In re Woodruff, 919 F.2d 1575, 1578 (Fed. Cir. 1990).). In view of the above, inter alia, the limitation of “wherein the first width ranges from about 150 micrometers to about 250 micrometers; and wherein the upper UBM layer has a height of about 2 micrometers to about 8 micrometers” is not patentable over Wang, in view of Nakano.
Regarding claim 20, Wang, modified by Nakano, teach the packaged integrated circuit of Claim 14, wherein the connection structures each include one selected from a through-mold via (TMV), conductive solder, a conductive pillar, and a conductive bump (“through vias (TVs) 405” extend through “encapsulant 403”, which comprises a molding compound, and are understood to be through-mold vias, para. 0028 and 0030).
8. A packaged integrated circuit (“semiconductor package 10” para. 0075 FIG. 1S), comprising:
a redistribution layer (“redistribution substrate 100” para. 0070) including a plurality of conductive lines (“first interconnection portions 131W”, para. 0034), a plurality of electrically conductive vias (“first via portions V1” para. 0034) connected to the plurality of conductive lines, a plurality of lower pads (“terminal pad 410” para. 0075) electrically connected to the plurality of electrically conductive vias, and a plurality of redistribution insulating layers (“insulating layers 111, 112, 113, 114, 115 and 116” para. 0070);
an integrated circuit chip (“semiconductor chip 200” para. 0072) on the redistribution layer; and
a plurality of external connection terminals (“external connection terminal 420” para. 0075) attached to the plurality of lower pads in the redistribution layer;
each of the plurality of lower pads extends between a corresponding one of the plurality of conductive vias and a corresponding one of the plurality of external connection terminals (“terminal pads 410” extend between “first via portions V1” and “external connection terminal 420”).
Claims 8 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Suk et al US 20200083201 A1 (hereinafter referred to as Suk), in view of Nakano.
Regarding claim 8, Suk teaches
A packaged integrated circuit (“semiconductor package 10” para. 0075 FIG. 1S), comprising:
a redistribution layer (“redistribution substrate 100” para. 0070) including a plurality of conductive lines (“first interconnection portions 131W”, para. 0034), a plurality of electrically conductive vias (“first via portions V1” para. 0034) connected to the plurality of conductive lines, a plurality of lower pads (“terminal pad 410” para. 0075) electrically connected to the plurality of electrically conductive vias, and a plurality of redistribution insulating layers (“insulating layers 111, 112, 113, 114, 115 and 116” para. 0070);
an integrated circuit chip (“semiconductor chip 200” para. 0072) on the redistribution layer; and
a plurality of external connection terminals (“external connection terminal 420” para. 0075) attached to the plurality of lower pads in the redistribution layer;
each of the plurality of lower pads extends between a corresponding one of the plurality of conductive vias and a corresponding one of the plurality of external connection terminals (“terminal pads 410” extend between “first via portions V1” and “external connection terminal 420”).
However, Suk fails to teach wherein each of the plurality of lower pads is embedded within a lowermost redistribution insulating layer of the plurality of redistribution insulating layers, wherein each of the plurality of lower pads comprises a lower under-bump metallization (UBM) layer that contacts one of the plurality of external connection terminals, and an upper UBM layer extending on the lower UBM layer, the upper UBM layer in direct contact with the corresponding one of the plurality of conductive vias; and wherein an upper surface of the lower UBM layer has a greater than or equivalent lateral width dimension relative to an upper surface of the upper UBM layer.
Nevertheless, Nakano teaches
wherein each of the plurality of lower pads (“under barrier metal layer (UBM) 2” para. 0038 FIG. 2A) is embedded within a lowermost redistribution insulating layer (“first protective film 3” para. 0038) of the plurality of redistribution insulating layers,
wherein each of the plurality of lower pads comprises a lower under-bump metallization (UBM) layer (turning FIG. 2A around, the lower layer of “UBM layer 2” is the layer below “first protective film 3”) that contacts one of the plurality of external connection terminals (“bump 6” para. 0038), and an upper UBM layer extending on the lower UBM layer (layer of “UBM layer 2” in opening of “first protective film 3” extends along the upper surface of the lower layer of “UBM layer 2”),
wherein an upper surface of the lower UBM layer has a greater than or equivalent lateral width dimension relative to an upper surface of the upper UBM layer (the lower surface of the lower layer of “UBM layer 2” extends further outward away from the center than the upper surface of the upper layer of “UBM layer 2”, which is inside the opening of “first protective film 3”).
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Suk and Nakano teach external connection terminals on UBM layers. “UBM layer 2” covers an edge of “protective film 3”, which is made of silicon nitride such that it helps reduce the chance of removal of layers under pressure (para. 0041). Furthermore, the “UBM layer 2” makes a contact angle with the “protective film 3” of less than 90 degrees to further reduce the possibility of removal of the “UBM layer 2” due to stress (para. 0041). The “UBM layer 2” is more reliable and device performance is better guaranteed. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that having the “terminal pad 410” with a lower layer wider than an upper layer and side surface of the “terminal pads 410” with an angle as taught in Nakano reduces the risk of removal of “terminal pads 410” under stress.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the packaged integrated circuit in Suk with the UBM layer as taught in Nakano. A UBM layer with a lower layer having greater lateral width than an upper layer and with the lower UBM layer having a slanted side surface, damage due to stress can be reduced. The protective film overlapping the upper surface of the lower layer also helps reduce the possibility of layer removal.
Suk, modified by Nakano, further teaches
the upper UBM layer in direct contact with the corresponding one of the plurality of conductive vias (upper surface of upper layer of “UBM layer 2” from Nakano is in contact with “first via portion V1” in Suk).
Regarding claim 11, Suk, modified by Nakano, teaches the packaged integrated circuit of Claim 8, wherein a seed layer (“first seed layer 121” para. 0035) is provided on a sidewall and on a lower surface of an electrically conductive via extending on the upper UBM layer (“first seed layer 121” is formed on bottom and sides of “first via portion V1”, para. 0035 1F-S, and extends across upper surface of “terminal pad 410”, para. 0075).
Allowable Subject Matter
Claims 10 is objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 10, the most relevant prior art Chen et al. US 20160079191 A1 teaches a seed layer formed before formation of the UBM layer. An upper layer of the UBM layer is covered by the seed layer. Chen fails to teach or render obvious and wherein a sidewall of the upper UBM layer is in contact with at least one of the plurality of redistribution insulating layers. Therefore, claim 10 is considered allowable.
Conclusion
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/ERIC MANUEL MULERO FLORES/ Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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