DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Applicant’s IDS submitted on 6/15/23, 3/26/24 and 6/20/25 in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has/have been considered by the examiner and made of record.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 14-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 14, In claim 14, the vertical structure is formed penetrating the structure, and then is removed, subsequently the vertical structure is recited to include sacrificial metal layer and a sacrificial barrier metal layer on at least part of an upper surface of the sacrificial metal layer. It is unclear how the vertical structure contains anything once it has been removed.
Claims 15-18 have been included because they depend from and therefore include all the limitations of claim 14.
For purposes of examination claim 14 has been interpreted to mean that the vertical structure refers to the stack and that a portion of the stack has been removed to form a hole in the stack.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lim et al., US 20180350830 A1, hereafter Lim.
Regarding claim 1, Lim discloses:
A non-volatile memory device (Figure 23, and [0009]-[0014] which disclose that Figures 5-23 all refer to the device of Figure 5), comprising:
a first stacking structure including first gate electrodes (Figure 19, gate electrodes G1 to G7, which correspond to mold layers 132 and mold layers 142 of Figure 23) and first interlayer insulating layers (Figure 19, lower insulating layers 131, and first intermediate insulating layers 141) alternately stacked on at least a portion of a substrate (Figure 19, substrate 26);
a second stacking structure including second gate electrodes (Figure 19, gate electrodes G8 to G10, correspond to mold layers 146 of Figure 23 ) and second interlayer insulating layers (Figure 19, striation control insulating layers 145) alternately stacked on at least a portion of the first stacking structure (Shown, Figure 19) and;
a channel structure including a first channel structure penetrating the first stacking structure (Figure 23, portion channel hole 61 in fourth region R4, having third width W3) and a second channel structure (Figure 23, channel hole 61, in third region R3, having a width that increases from third width W3 to fifth width W5) connected to the first channel structure and penetrating the second stacking structure (shown, Figure 23),
wherein the second channel structure (Figure 23, channel hole 61, in third region R3) includes a first portion having a width that narrows or is maintained as the first portion extends toward the substrate (Figure 23, width of channel hole 61 decreases at the bottom of third region R3), and a second portion having a width that increases as the second portion extends toward the substrate (Figure 23, width of channel hole 61 increases at the top of third region R3) in an area overlapping a lowermost one of the second gate electrodes that is disposed closest to the substrate in a vertical direction to the substrate (Figure 23, Region R3 overlaps lowest layer 146, which is the lowermost one of the second gate electrodes).
Regarding claim 2, Lim discloses:
The non-volatile memory device of claim 1, wherein the second stacking structure has a thickness, in a direction perpendicular to a surface of the substrate (Figure 23, R3), that is different from a thickness of the first stacking structure in the direction perpendicular to the surface of the substrate (Figure 23, R4, shown with more layers and a greater thickness than R3).
Claims 1-3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al., US 20200411535 A1, hereafter Wang.
Regarding claim 1, Wang discloses the following limitations:
A non-volatile memory device (Wang, Figure 7, semiconductor device 100, and [0046] which discloses that the string can be a NAND memory device), comprising:
a first stacking structure including first gate electrodes and first interlayer insulating layers alternately stacked on at least a portion of a substrate (Wang, Figure 7, first stack 110, between substrate 101 and boundary 173);
a second stacking structure including second gate electrodes and second interlayer insulating layers alternately stacked on at least a portion of the first stacking structure (Wang, Figure 7, third stack 130, second stack 120 and portion of first stack 110 above boundary 173); and
a channel structure including a first channel structure penetrating the first stacking structure (Wang, Figure 7, second portion 310b) and a second channel structure connected to the first channel structure and penetrating the second stacking structure (Wang, Figure 7, via 630, extending from insulating layers 553 down to boundary 173),
wherein the second channel structure includes a first portion having a width that narrows or is maintained as the first portion extends toward the substrate (Wang, Figure 7, portion in region 130), and
a second portion having a width that increases as the second portion extends toward the substrate in an area overlapping a lowermost one of the second gate electrodes that is disposed closest to the substrate in a vertical direction to the substrate (Wang, Figure 7, portion of via 630 that decreases in width between CD3 and CD2).
Regarding claim 2, Wang discloses the following limitations:
The non-volatile memory device of claim 1, wherein the second stacking structure has a thickness, in a direction perpendicular to a surface of the substrate, that is different from a thickness of the first stacking structure in the direction perpendicular to the surface of the substrate (Wang, Shown, Figure 7, stack 110 from boundary 173 down to substrate 101 has a different thickness than the rest of the stack).
Regarding claim 3, Wang discloses the following limitations:
The non-volatile memory device of claim 1, wherein the second channel structure includes the second portion of which the width increases as it extends toward the substrate in the area overlapping a lower second gate electrode most adjacent to the lowermost one of the second gate electrodes in a vertical direction to the substrate (Wang, Figure 7, width of via 630 increases between CD6 and CD3).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Wang as applied to claim 1 under 35 U.S.C. §102 above, and further in view of Pachamuthu et al., US 20150236038 A1, hereafter Pachamuthu.
Wang fails to disclose the following limitations:
The non-volatile memory device of claim 1, wherein
the second stacking structure is disposed on a first capping insulation layer on the first stacking structure, and a cross-sectional thickness of the first capping insulation layer interposed between an uppermost one of the first gate electrodes of the first stacking structure and the lowermost one of the second gate electrodes of the second stacking structure is greater than a thickness of a given one of the first interlayer insulating layers or a given one of the second interlayer insulating layers.
Pachamuthu discloses the following imitations:
the second stacking structure (Figure 22, 232 and 242) is disposed on a first capping insulation layer (Figure 22, interstack dielectric layer 180, and [0089] discloses that layers 170 and 190 are optional) on the first stacking structure (Figure 22, 146 and 132), and a cross-sectional thickness of the first capping insulation layer interposed between an uppermost one of the first gate electrodes of the first stacking structure and the lowermost one of the second gate electrodes of the second stacking structure is greater than a thickness of a given one of the first interlayer insulating layers or a given one of the second interlayer insulating layers (Shown, Figure 22, [0003] and [0057] discloses 20-50 nm for insulating layers, [0066] discloses that 180 is 30-100 nm, [0089] discloses that one of 170, 180 and 190 has a thickness that is greater than the maximum thickness of layers 132 or 232, and [0089] discloses that 170 and 190 are optional.).
It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have applied the teachings of Pachamuthu to the device of Wang and to therefore have used a dielectric capping layer between the first stack and the second stack. Doing so provides a layer that can be used to planarize and improve the stacking of the lower and upper stack layers.
Claim 10 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Wang as applied to claim 1 under 35 U.S.C. §102 above, and further in view of Ariyoshi, US 10115681 B1, hereafter Ariyoshi.
Regarding claim 10, Wang fails to disclose the following limitations:
The non-volatile memory device of claim 1, further comprising a common source line disposed on at least a portion of the substrate, wherein the channel structure includes a channel layer that is connected to the common source line.
Ariyoshi discloses the following limitations:
further comprising a common source line disposed on at least a portion of the substrate (Figure 30, buried source layer 14), wherein the channel structure includes a channel layer that is connected to the common source line (Figure 30, memory opening fill structures 58 (a channel layer), goes through the stack and contact source layer 14).
It would have been obvious to one oof ordinary skill in the art at the time of the effective filing date of the invention to have applied the teachings of Ariyoshi to the device of Wang and to therefore used a buried source layer to connect the memory strings. Such a structure is taught by Ariyoshi and would desirably improve the memory devices by efficiently providing necessary connections shorter source connections increases device density and improve memory speed.
Regarding claim 13, Wang fails to disclose the following limitations:
The non-volatile memory device of claim 1, further comprising a peripheral circuit substrate, a peripheral circuit pattern on the peripheral circuit substrate, and a peripheral area insulation layer on the peripheral circuit pattern are disposed under the substrate.
Ariyoshi discloses the following limitations:
The non-volatile memory device of claim 1, further comprising a peripheral circuit substrate (Figure 30, substrate 9), a peripheral circuit pattern (Figure 30, and col. 33, lines 23-36, discloses that an integrated circuit can be formed on the semiconductor substrate) on the peripheral circuit substrate, and a peripheral area insulation layer on the peripheral circuit pattern are disposed under the substrate (Figure 30, dielectric layers 760).
It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have applied the teachings of Ariyoshi to the device of Wang and to therefore have included a peripheral circuit in a substrate below the memory device. Such a circuit is taught by Ariyoshi to desirably supply the required circuitry for the memory device to function and does so in a compact manner that increases device density.
Claim 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Wang as applied to claim 1 under 35 U.S.C. §102 above, and further in view of Okada et al., US 20220077088 A1, hereafter Okada.
Regarding claim 19, Wang discloses:
An electronic system, comprising:
a semiconductor device (Figure 7, semiconductor device 100) on a main substrate (Wang, Figure 7, substrate 101); and
wherein the semiconductor device includes a non-volatile memory device including:
a substrate (Wang, Figure 7, substrate 101),
a first stacking structure including first gate electrodes and first interlayer insulating layers alternately stacked on at least a portion of the substrate (Wang, Figure 7, first stack 110, between substrate 101 and boundary 173),
a second stacking structure including second gate electrodes and second interlayer insulating layers alternately stacked on at least a portion of the first stacking structure (Wang, Figure 7, third stack 130, second stack 120 and portion of first stack 110 above boundary 173), and
a channel structure including a first channel structure penetrating the first stacking structure (Wang, Figure 7, second portion 310b) and a second channel structure connected to the first channel structure and penetrating the second stacking structure (Wang, Figure 7, via 630, extending from insulating layers 553 down to boundary 173),
wherein the second channel structure includes a first portion having a width that decreases or is maintained as to the first portion extends toward the substrate (Wang, Figure 7, portion in region 130), and
a second portion having a width that increases as to the second portion extends toward the substrate in an area overlapping a lowermost one of the second gate electrodes that is closest to the substrate in a vertical direction to the substrate (Wang, Figure 7, portion of via 630 that decreases in width between CD3 and CD2), and
Wang fails to disclosed:
a semiconductor device on a main substrate; and
a controller electrically connected to the semiconductor device on the main substrate,
a peripheral circuit substrate disposed under the substrate,
a peripheral circuit pattern disposed on at least a portion of the peripheral circuit
substrate, a peripheral area insulation layer on at least a portion of the peripheral circuit pattern,
an input and output pad electrically connected to the peripheral circuit pattern of the non-volatile memory device.
Okada discloses the following limitations:
a controller (Okada, Figure 4, and [0102] discloses that CP contains an input/output control circuit) electrically connected to the semiconductor device on the main substrate (Okada, Figure 4, shows I/O connected to MCA, memory cell array),
a peripheral circuit substrate (Okada, Figure 20, CP is below CM when viewed from above) disposed under the substrate,
a peripheral circuit pattern disposed on at least a portion of the peripheral circuit
substrate (Okada, Figure 20, show a pattern of circuits in device layer LDL in CP), a peripheral area insulation layer on at least a portion of the peripheral circuit pattern (Okada, Figure 20, and [0154] an insulating layer is formed on the upper surface of semiconductor substrate 200),
an input and output pad (Okada, Figure 20, bonding pad electrode PX(MZ)) electrically connected to the peripheral circuit pattern of the non-volatile memory device (Okada, Shown, Figure 20 and Figure 4).
It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have applied the teachings of Okada to the device of Wang and to therefore have combined the memory device of Wang with the circuitry as taught by Okada, doing so will supply the memory device with the circuitry necessary to operate the device as intended in a compact format that allows for increased density.
Regarding claim 20, Wang and Okada disclose the following limitations:
The electronic system of claim 19, wherein the non-volatile memory device further includes:
a common source line on the substrate (Okada, Figure 30, conductive layer 111), a channel pad on the channel structure (Okada, Figure 30, contacts Ch),
a channel contact plug (Okada, Figure 30, contacts Cb) on the channel pad,
a bit line on the channel contact plug (Okada, Figure 30, bit line, BL), and
gate contact plugs connected to corresponding ones of the first and second gate electrodes (Okada, Figure 30, contacts CC).
Allowable Subject Matter
Claims 5-9 and 11-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 5: The prior art of record fails to teach or disclose a memory device containing a third portion that has a width that increases in width as it extends towards the substrate.
Claims 6-9, which depend from claim 5 have been included because they, by their dependency contain all of the limitations of claim 5.
Regarding claim 11: The prior art fails to teach or disclose a memory device with two or more stacking structures stacked perpendicular to the substrate that each contain a second channel structure penetrating that are connected to the channel structure in the first stacking structure.
Claim 12, which depends from claim 11 has been included because it, by its dependency contains all of the limitations of claim 11.
Claims 14-18 would be allowable if re-written to overcome the 112(b) rejection above.
Regarding claim 14, the prior art of record fails to teach or disclose in the etching of a hole in a stack by using a gas that etches the sacrificial barrier metal layer and where such etching produces a byproduct is that can then etch the second material of the stack.
Claims 15-18 have been included because they depend from claim 14, and therefore include the allowable subject matter.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Mun et al., US 20230130126 A1, discloses a memory device with shaped channel structures.
Yun et al., US 202100366008 A1, discloses a memory device with three stacks.
Baek et al., US 20200185409 A1, discloses a memory device with shaped channel layer where the increase in width occurs in a inter stack dielectric.
Han et al., US 20170062470 A1, discloses a bowed channel structure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LINDA J FLECK whose telephone number is (703)756-1253. The examiner can normally be reached 10-2 ET.
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/LINDA J. FLECK/ Examiner, Art Unit 2812
/William B Partridge/ Supervisory Patent Examiner, Art Unit 2812
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