DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 9, and 21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 20160013277 (Ho et al).
Concerning claim 1, Ho discloses a layer structure comprising (Fig. 5): a first substrate (202); a second substrate (206) surrounded by the first substrate (Fig. 5, note that the boundaries of the second substrate are formed completely within the boundaries of the first substrate); and a two-dimensional (2D) channel layer including a transition metal dichalcogenide (204) ([0032]) on the second substrate, wherein an interfacial energy of the second substrate is less than an interfacial energy of the first substrate ([0015] and [0039], note that the buffer layer undergoes a sulfurization process which allows for a lattice constant mismatch of less than 5% with the lattice constant of the channel layer material).
Continuing to claim 9, Ho discloses wherein the second substrate has a fin shape and protrudes in a direction perpendicular to a surface of the first substrate (Fig. 5).
Considering claim 21, Ho discloses wherein the second substrate includes one of an insulating metal oxide, parylene-C, polyimide, SiO2, a ceramic material, or silicon (Si) ([0015], note that a material for the buffer layer (second substrate) is disclosed to be SiC which is a ceramic material and the examiner is relying on this material for rejection purposes).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-6, 8, 11, 12, and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20160013277 (Ho et al) in view of US 7858989 (Chen et al).
Referring to claim 2, Ho discloses forming a first and second substrate.
Ho does not disclose wherein the first substrate includes a trench and the second substrate is in the trench. However, Chen discloses a layer structure comprising (Fig. 3A): a first substrate (10); a second substrate (18) surrounded by the first substrate (Fig. 3A, note that the boundaries of the second substrate are formed completely in the trench and within the boundaries of the first substrate); and a two-dimensional (2D) channel layer (20) formed over the second substrate (Fig. 3A) and includes a first electrode layer and a second electrode layer separated from each other on the 2D channel layer (Fig. 3A); and the plurality of electrode layers further include a third electrode layer (52) on the 2D channel layer between the first electrode layer and the second electrode layer (Fig. 3A), and the third electrode layer is spaced part from the 2D channel layer (Fig. 3A, note that a gate insulation layer (50) separates the gate electrode 52 from the 2D channel layer 20) in a configuration such that the first substrate includes a trench (12), and the second substrate is in the trench (Chen Fig. 3A). In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (The court held that the configuration of the claimed disposable plastic nursing container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant.). MPEP 2144.04 IV B. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the configuration of the first and second substrate of Ho such that the first substrate includes a trench and the second substrate is in the trench with the electrode spaced from one another and the third electrode spaced apart from the channel as disclosed by Chen absent evidence such configuration is significant.
Considering claim 3, Ho in view of Chen discloses wherein the second substrate is along a surface of the trench, and the 2D channel layer is along a surface of the second substrate (Chen Fig. 3A).
Referring to claim 4, Ho in view of Chen discloses wherein the 2D channel layer fills the trench in the first substrate (Chen Fig. 3A, note that the 2D layer 18 fills the horizontal dimension of the trench in the first substrate).
Regarding claim 5, Ho in view of Chen discloses wherein the second substrate completely fills the trench (Chen Fig. 3A).
Pertaining to claim 6, Ho in view of Chen discloses wherein the second substrate completely fills the trench (Chen Fig. 3A), and an upper surface of the second substrate higher than an upper surface of the first substrate (Chen Fig. 3A, note that the fist substrate has at least two upper surfaces (the upper surface of the outer regions of the substrate and the inner regions defined by the trench) the examiner is interpreting that the upper region of the second substrate has an upper surface (the top portion) that is higher than the upper surface of the trench portion of the first substrate).
Concerning claim 8, Ho in view of Chen discloses the first substrate and the second substrate have a same height (Chen Fig. 3A).
Considering claim 10, Ho in view of Chen discloses wherein the 2D channel layer includes a 2D semiconductor material layer (Ho claim 31).
Referring to claim 11, Ho in view of Chen discloses an electronic device comprising: the layer structure of claim 1 (Ho Fig. 5); and a plurality of electrode layers (Ho 208, 210, 212) on the layer structure (Ho [0034] and Chen Fig. 3A and col. 4 lines 33-35, note that in Chen there are two electrode layers 14 that are used as source drain electrodes), wherein the first substrate is a substrate (Ho Fig. 5 and Chen Fig. 3A), the two-dimensional (2D) channel layer on the second substrate is on the substrate (Ho Fig. 5 and Chen Fig. 3A); the plurality of electrode layers include a first electrode layer (Ho 208) and a second electrode layer (Ho 212) separated from each other on the 2D channel layer (Ho Fig. 5 and Chen Fig. 3A); and the plurality of electrode layers further include a third electrode layer (Ho 210 and Chen 52) on the 2D channel layer between the first electrode layer and the second electrode layer (Ho Fig. 5 and Chen Fig. 3A), and the third electrode layer is spaced part from the 2D channel layer (Chen Fig. 3A, note that a gate insulation layer (50) separates the gate electrode 52 from the 2D channel layer 20).
Regarding claim 12, Ho in view of Chen discloses an electronic apparatus comprising the electronic device of claim 11 (Chen col. 4 lines 27-35 and Fig. 3A).
Pertaining to claim 22, Ho in view of Chen discloses wherein a sidewall of the second substrate is in contact with a sidewall of the trench in the first substrate (Chen Fig. 3A, note that the sidewall of the second substrate is in contact with the sidewall of the trench via the electrode layers) .
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20160013277 (Ho et al) in view of US 7858989 (Chen et al) as applied to claim 7 above, and further in view of US 20210210347 (Sekine et al).
As to claim 7, Ho in view of Chen discloses . . . the first substrate and the second substrate have a same height (Chen Fig. 3A).
Chen in view of Sekine and Lin does not disclose the trench is a step-type trench including portions having different widths. However, Sekine discloses that two-dimensional materials are very thin, their properties are susceptible to influence of the irregularities on a substrate, and it is difficult to achieve a device with good properties ([0004]) and therefore a step-type trench is utilized configuration to form a stable crystal face, and an atomically flat face ([0005]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to form the trench of Ho in view Chen in a step type trench configuration in order to form a surface with a stable crystal face that is atomically flat to produce a 2D material layer with good characteristics.
Claim(s) 13 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20160013277 (Ho et al) in view of US 7858989 (Chen et al) as applied to claim 1 above, and further in view of US 20160099407 (Lim et al) .
Pertaining to claims 13 and 14, Ho in view of Chen discloses forming a layer structure that is utilized in a transistor (Ho [0002]).
Ho in view of Chen does not disclose a memory device comprising: a switching device; and a data storage element connected to the switching device, wherein the switching device comprises the layer structure of claim 1 or an electronic apparatus comprising the memory device of claim 13. However, Lim discloses that the suitability of the use of a graphene channel transistor device formed and connected with a storage unit in a memory device ([0038]) and that a reliable memory device with data storage property and data retention property can be achieved with such a configuration ([0007]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to form a memory device in an electronic apparatus that includes a switching device; and a data storage element connected to the switching device, wherein the switching device comprises the layer structure of Chen in view of Sekine and Lin in order to form a reliable memory apparatus.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 11 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VALERIE N NEWTON whose telephone number is (571)270-5015. The examiner can normally be reached M-F 8-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHAD DICKE can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/VALERIE N NEWTON/ Examiner, Art Unit 2897 04/17/26
/CHAD M DICKE/ Supervisory Patent Examiner, Art Unit 2897
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