Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 3-5, 10-11, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tan et al., US 2021/0288066 in view of Xu et al., “Bilayer Tellurine: A potential p-type channel material for sub 10nm Transistors”, Advanced Theory and Simulations 2021, 4, 200252, pages 1-12.
Tan et al. shows the invention as claimed including a nonvolatile memory device comprising:
A channel layer 114 extending in a first direction;
A plurality of gate electrodes 102 and a plurality of spacers alternately arranged with each other in the first direction, each of the plurality of gate electrodes 102 and each of the plurality of spacers 104 extending in a second direction crossing the first direction; and a gate insulating layer extending in the first direction, the gate insulating layer (108,110,112) between the channel layer 114 and the plurality of gate electrodes, wherein the channel layer includes a two-dimensional semiconductor material (see paragraphs 0023-0030 and figs. 1-2).
Tan et al. does not expressly disclose that the two-dimensional semiconductor material is tellurene doped with a p-type impurity. Xu et al. discloses the use of p-doped tellurene as a channel material (see abstract on page 1 and “Conclusion”, page 11). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the primary reference of Tan et al. so as to include a tellurene p-doped two-dimensional material as disclosed by Xu et al. because Xu et al. shows such a material as being suitable for forming a channel material due to its beneficial electrical characteristics.
Concerning claim 2, note that, as disclosed above, Yu discloses where the semiconductor material is WSe2.
Regarding claim 3, Tan et al. and Xu et al. do not expressly disclose the claimed hole and electron mobility of the channel layer. However, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to determine through routine experimentation the optimum hole and electron mobility depending upon a variety of considerations including the desired speed and conductivity type of the device and such limitation would not lend patentability to the instant application absent a showing of unexpected results.
With respect to dependent claim 4, note that Tan et al. discloses that the channel layer is a monolayer or a few layers of monolayers of molybdenum disulfide (see paragraph 0024) which ranges from 0.65nm to about 2nm which overlaps with the claimed range establishing a prima facie case of obviousness (see MPEP 2144.5). Furthermore, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to form a channel layer of the claimed thickness because Tan et al. shows that particular thickness to be suitable as a channel material.
Concerning dependent claim 5, note that Tan et al. discloses the nonvolatile memory device further comprising: an insulating support 220 extending in the first direction, wherein the channel layer 114 surrounds the insulating support.
As to dependent claim 10, note that Tan et al. discloses a nonvolatile memory device comprising: a gate insulating layer including a charge blocking layer 208, a charge trap layer 210, and a tunneling dielectric layer 212, the charge blocking layer is between the channel layer 214 and the plurality of gate electrodes, the charge trap layer is between the channel layer and the charge blocking layer, and the tunneling dielectric layer is between the channel layer and the charge trap layer (see fig. 2 and its description).
Concerning dependent claim 11, note that Tan et al. discloses wherein the tunneling dielectric layer, the charge trap layer, and the charge blocking layer extend in the first direction along the surface of the channel layer and are arranged in a concentric circular shape (see fig. 2).
With respect to dependent claim 17, note that the plurality of gate electrodes in Tan et al. include at least one conductive material that can be tungsten, for example (see paragraph 0026).
Claim(s) 6-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tan et al., US 2021/0288066 in view of Xu et al., “Bilayer Tellurene: A potential p-type channel material for sub 10nm Transistors”, Advanced Theory and Simulations 2021, 4, 200252, pages 1-12, as applied to claims 1, 3-5, 10-11, and 17 above, and further in view of O’Brien et al., US 2022/0199799.
Tan et al. and Xu et al. are applied as above but do not expressly disclose a first boron nitride layer between the insulating support and the channel layer, wherein the first boron nitride layer surrounds the insulating support and extends in the first direction. O’Brien et al. discloses integrating a hexagonal boron nitride layer (106a,106b) on the top and bottom of two-dimensional semiconductor channel material 104 (see paragraph 0021). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the device of Tan et al. modified by Xu et al. so as to comprise a hexagonal boron nitride layer between the insulating support and channel layer because in such a way an optimized channel can be produced.
Concerning dependent claim 7, note that in O’Brien et al. the boron nitride is hexagonal (see abstract).
With respect to dependent claim 8, note that the hexagonal boron nitride layer has a thickness of from 0.3-10 nanometers (see paragraph 0026 of O’Brien et al.) which overlaps with the claimed range and creates a prima facie case of obviousness (see MPEP 2144.05). Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have a thickness in the claimed range because in such a way a suitable active layer of a device can be produced.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tan et al., US 2021/0288066 in view of Xu et al., “Bilayer Tellurine: A potential p-type channel material for sub 10nm Transistors”, Advanced Theory and Simulations 2021, 4, 200252, pages 1-12 as applied to claims 1, 3-5, 10-11, and 17 above, and further in view of Cho et al., US 2012/0281484.
Tan et al. and Xu et al. are applied as above but do not expressly disclose where the gate electrode can be one of the claimed two dimensional materials. However, Cho et al. discloses a non-volatile memory device comprising a graphene gate electrode (see abstract). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the memory device of Tan et al. modified by Xu et al. so as to comprise a graphene electrode because such an electrode has a high work function and does not cause deterioration of a lower insulating film.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tan et al., US 2021/0288066 in view of Xu et al., “Bilayer Tellurene: A potential p-type channel material for sub 10nm Transistors”, Advanced Theory and Simulations 2021, 4, 200252, pages 1-12, as applied to claims 1-5, 10-11, and 17 above, and further in view of Brown et al., US 2017/0372205.
Tan et al. and Xu et al. are applied as above with respect to claims 1-5, 10, and 17 but do not expressly disclose a neuromorphic apparatus comprising a processing circuit and the claimed memory system. However, Brown et al. discloses a neuromorphic apparatus (see paragraph 0025) comprising a processing circuit (see paragraph 0009) and a memory system 8 (see fig. 1 and paragraphs 0017-0030). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the device of Tan et al. modified by Xu et al. so as to make the device part of the claimed neuromorphic apparatus as suggested by Brown et al. because in such a way an apparatus capable of predicting future states of a hardware system can be fabricated.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 3-8, 10-11, 17-18, and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/RICHARD A BOOTH/ Primary Examiner, Art Unit 2812
July 7, 2026
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