DETAILED ACTION
This office action is in response to the Response to the Election/Restriction filed on October 27, 2025. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgement
Applicant’s election without traverse of Group 1 (Claims 1-12 and 22-34) in the reply filed on October 27, 2025, is acknowledged. The present office action is made with all the suggested amendments being fully considered. Accordingly, claims 1-34 are currently pending in this application. Claims 13-21 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 1/17/2025 are being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 5-7, 9-10, 12, 22-24, 26-28, 30-31, 33-34 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Su (US 2024/0113159).
With respect to Claim 1, Su shows (Fig. 2B,3B) all aspects of the current invention including a semiconductor device comprising:
a first-tier passive device (206) including a substrate portion (bottom portion of 210), a passive device portion (218), and a metallization portion (212) disposed in a stacked configuration, the passive device portion being disposed between the substrate portion and the metallization portion
one or more second-tier passive devices (202) disposed over the first-tier passive device, each one of the one or more second-tier passive devices including:
a substrate portion (bottom portion of 214), a passive device portion (220a-220c), and a metallization portion (216) disposed in a stacked configuration, the passive device portion disposed between the substrate portion and the metallization portion;
a set of through substrate vias (TSVs) (240) passing through a corresponding substrate portion and electrically coupled to a corresponding metallization portion;
a passive component including the passive device portion of the first-tier passive device (see par 41; 218 may include one or more of capacitors, resistors, inductors, etc.) electrically coupled to one or more passive device portions of the one or more second-tier passive devices (see par 42; 220a-220c may include one or more of decoupling trench capacitor structures) through the metallization portion (212) of the first-tier passive device, one or more sets of TSVs (240) of the one or more second-tier passive devices, and one or more metallization portions (216) of the one or more second-tier passive devices
With respect to Claim 2, Su shows (Fig. 2B,3B) wherein the first-tier passive device (206) further comprises an electrostatic discharge (ESD) protection circuit (312) disposed in the substrate portion of the first-tier passive device and electrically coupled to the passive device portion of the first-tier passive device (see Fig 3B; par 69-70)
With respect to Claim 3, Su shows (Fig. 2B,3B) wherein a thickness of the substrate portion (bottom portion of 210) of the first-tier passive device is greater than a thickness of substrate portion (bottom portion of 214) of the one or more second-tier passive devices
With respect to Claim 5, Su shows (Fig. 2B,3B) further comprising at least two electrical terminal structures (244) disposed on an upper surface of an uppermost second-tier passive device of the one or more second-tier passive devices, the at least two electrical terminal structures being configured as electrical terminals of the passive component
With respect to Claim 6, Su shows (Fig. 2B,3B) wherein the passive device portion of the first-tier passive device is disposed over the substrate portion of the first-tier passive device, the first-tier passive device further comprises first conductive structures (226) that are disposed on an upper surface of the first-tier passive device, the one or more second-tier passive devices include a first second-tier passive device, the first second-tier passive device includes second conductive structures (232), and the first conductive structures are bonded to the second conductive structures
With respect to Claim 7, Su shows (Fig. 2B,3B) wherein the first conductive structures are connected to the second conductive structures based on fusion bonding or hybrid bonding (par 110)
With respect to Claim 9, Su shows (Fig. 2B,3B) wherein the passive device portion of the first second-tier passive device is disposed over the substrate portion of the first second-tier passive device, and the second conductive structures are disposed on a lower surface of the first second-tier passive device and are connected to the set of TSVs of the first second-tier passive device
With respect to Claim 10, Su shows (Fig. 2B,3B) wherein the substrate portion of the first second-tier passive device is disposed over the passive device portion of the first second-tier passive device, and the second conductive structures are disposed on a lower surface of the first second-tier passive device and are adjacent the metallization portion of the first second-tier passive device
With respect to Claim 12, Su shows (Fig. 2B,3B) wherein the passive device portion of the first-tier passive device and the one or more passive device portions of the one or more second-tier passive devices comprise a deep trench capacitor, an integrated stack capacitor, a metal-insulator-metal capacitor, a metal-oxide-metal capacitor, or a combination thereof (par 41-43)
With respect to Claim 22, Su shows (Fig. 2B,3B) all aspects of the current invention including an electronic device including a semiconductor device (200) (See also par 2), and the semiconductor device comprising:
a first-tier passive device (206) including a substrate portion (bottom portion of 210), a passive device portion (218), and a metallization portion (212) disposed in a stacked configuration, the passive device portion being disposed between the substrate portion and the metallization portion
one or more second-tier passive devices (202) disposed over the first-tier passive device, each one of the one or more second-tier passive devices including:
a substrate portion (bottom portion of 214), a passive device portion (220a-220c), and a metallization portion (216) disposed in a stacked configuration, the passive device portion disposed between the substrate portion and the metallization portion;
a set of through substrate vias (TSVs) (240) passing through a corresponding substrate portion and electrically coupled to a corresponding metallization portion;
a passive component including the passive device portion of the first-tier passive device (see par 41; 218 may include one or more of capacitors, resistors, inductors, etc.) electrically coupled to one or more passive device portions of the one or more second-tier passive devices (see par 42; 220a-220c may include one or more of decoupling trench capacitor structures) through the metallization portion (212) of the first-tier passive device, one or more sets of TSVs (240) of the one or more second-tier passive devices, and one or more metallization portions (216) of the one or more second-tier passive devices
With respect to Claim 23, Su shows (Fig. 2B,3B) wherein the first-tier passive device (206) further comprises an electrostatic discharge (ESD) protection circuit (312) disposed in the substrate portion of the first-tier passive device and electrically coupled to the passive device portion of the first-tier passive device (see Fig 3B; par 69-70)
With respect to Claim 24, Su shows (Fig. 2B,3B) wherein a thickness of the substrate portion (bottom portion of 210) of the first-tier passive device is greater than a thickness of substrate portion (bottom portion of 214) of the one or more second-tier passive devices
With respect to Claim 26, Su shows (Fig. 2B,3B) further comprising at least two electrical terminal structures (244) disposed on an upper surface of an uppermost second-tier passive device of the one or more second-tier passive devices, the at least two electrical terminal structures being configured as electrical terminals of the passive component.
With respect to Claim 27, Su shows (Fig. 2B,3B) wherein the passive device portion of the first-tier passive device is disposed over the substrate portion of the first-tier passive device, the first-tier passive device further comprises first conductive structures (226) that are disposed on an upper surface of the first-tier passive device, the one or more second-tier passive devices include a first second-tier passive device, the first second-tier passive device includes second conductive structures (232), and the first conductive structures are bonded to the second conductive structures
With respect to Claim 28, Su shows (Fig. 2B,3B) wherein the first conductive structures are connected to the second conductive structures based on fusion bonding or hybrid bonding (par 110)
With respect to Claim 30, Su shows (Fig. 2B,3B) wherein the passive device portion of the first second-tier passive device is disposed over the substrate portion of the first second-tier passive device, and the second conductive structures are disposed on a lower surface of the first second-tier passive device and are connected to the set of TSVs of the first second-tier passive device
With respect to Claim 31, Su shows (Fig. 2B,3B) wherein the substrate portion of the first second-tier passive device is disposed over the passive device portion of the first second-tier passive device, and the second conductive structures are disposed on a lower surface of the first second-tier passive device and are adjacent the metallization portion of the first second-tier passive device
With respect to Claim 33, Su shows (Fig. 2B,3B) wherein the passive device portion of the first-tier passive device and the one or more passive device portions of the one or more second-tier passive devices comprise a deep trench capacitor, an integrated stack capacitor, a metal-insulator-metal capacitor, a metal-oxide-metal capacitor, or a combination thereof (par 41-43)
With respect to Claim 34, Su shows (Fig. 2B,3B) wherein the electronic device comprises a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, or a device in an automotive vehicle (See also par 121-126; Fig 10)
Claims 1, 3, 6-7, 9-10, 12, 22, 24, 27-28, 30-31, 33-34 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kao (US 2022/0278095)
With respect to Claim 1, Kao shows (Fig. 1-6, 24, 26-27) all aspects of the current invention including a semiconductor device comprising:
a first-tier passive device (100) including a substrate portion (101), a passive device portion (103), and a metallization portion (105) disposed in a stacked configuration, the passive device portion being disposed between the substrate portion and the metallization portion
one or more second-tier passive devices (200) disposed over the first-tier passive device, each one of the one or more second-tier passive devices including:
a substrate portion (201), a passive device portion (217), and a metallization portion (219) disposed in a stacked configuration, the passive device portion disposed between the substrate portion and the metallization portion;
a set of through substrate vias (TSVs) (225a) passing through a corresponding substrate portion and electrically coupled to a corresponding metallization portion;
a passive component including the passive device portion of the first-tier passive device (see par 41; 103 may be a passive device (capacitors, resistors, inductors, etc.)) electrically coupled to one or more passive device portions of the one or more second-tier passive devices (see par 55; 217 may be a passive device (capacitors)) through the metallization portion (105) of the first-tier passive device, one or more sets of TSVs (225a) of the one or more second-tier passive devices, and one or more metallization portions (219) of the one or more second-tier passive devices
With respect to Claim 3, Kao shows (Fig. 1-6, 24, 26-27) wherein a thickness of the substrate portion of the first-tier passive device is greater than a thickness of substrate portions of the one or more second-tier passive devices.
With respect to Claim 6, Kao shows (Fig. 1-6, 24, 26-27) wherein the passive device portion of the first-tier passive device is disposed over the substrate portion of the first-tier passive device, the first-tier passive device further comprises first conductive structures (115a/115b) that are disposed on an upper surface of the first-tier passive device, the one or more second-tier passive devices include a first second-tier passive device, the first second-tier passive device includes second conductive structures (231a/231b), and the first conductive structures are bonded to the second conductive structures
With respect to Claim 7, Kao shows (Fig. 1-6, 24, 26-27) wherein the first conductive structures are connected to the second conductive structures based on fusion bonding or hybrid bonding (par 93)
With respect to Claim 9, Kao shows (Fig. 1-6, 24, 26-27) wherein the passive device portion of the first second-tier passive device is disposed over the substrate portion of the first second-tier passive device, and the second conductive structures are disposed on a lower surface of the first second-tier passive device and are connected to the set of TSVs of the first second-tier passive device
With respect to Claim 10, Kao shows (Fig. 1-6, 24, 26-27) wherein the substrate portion of the first second-tier passive device is disposed over the passive device portion of the first second-tier passive device, and the second conductive structures are disposed on a lower surface of the first second-tier passive device and are adjacent the metallization portion of the first second-tier passive device
With respect to Claim 12, Kao shows (Fig. 1-6, 24, 26-27) wherein the passive device portion of the first-tier passive device and the one or more passive device portions of the one or more second-tier passive devices comprise a deep trench capacitor, an integrated stack capacitor, a metal-insulator-metal capacitor, a metal-oxide-metal capacitor, or a combination thereof (par 55)
With respect to Claim 22, Kao shows (Fig. 1-6, 24, 26-27) all aspects of the current invention including an electronic device including a semiconductor device (1000) (See also par 2), and the semiconductor device comprising:
a first-tier passive device (100) including a substrate portion (101), a passive device portion (103), and a metallization portion (105) disposed in a stacked configuration, the passive device portion being disposed between the substrate portion and the metallization portion
one or more second-tier passive devices (200) disposed over the first-tier passive device, each one of the one or more second-tier passive devices including:
a substrate portion (201), a passive device portion (217), and a metallization portion (219) disposed in a stacked configuration, the passive device portion disposed between the substrate portion and the metallization portion;
a set of through substrate vias (TSVs) (225a) passing through a corresponding substrate portion and electrically coupled to a corresponding metallization portion;
a passive component including the passive device portion of the first-tier passive device (see par 41; 103 may be a passive device (capacitors, resistors, inductors, etc.)) electrically coupled to one or more passive device portions of the one or more second-tier passive devices (see par 55; 217 may be a passive device (capacitors)) through the metallization portion (105) of the first-tier passive device, one or more sets of TSVs (225a) of the one or more second-tier passive devices, and one or more metallization portions (219) of the one or more second-tier passive devices
With respect to Claim 24, Kao shows (Fig. 1-6, 24, 26-27) wherein a thickness of the substrate portion of the first-tier passive device is greater than a thickness of substrate portions of the one or more second-tier passive devices.
With respect to Claim 27, Kao shows (Fig. 1-6, 24, 26-27) wherein the passive device portion of the first-tier passive device is disposed over the substrate portion of the first-tier passive device, the first-tier passive device further comprises first conductive structures (115a/115b) that are disposed on an upper surface of the first-tier passive device, the one or more second-tier passive devices include a first second-tier passive device, the first second-tier passive device includes second conductive structures (231a/231b), and the first conductive structures are bonded to the second conductive structures
With respect to Claim 28, Kao shows (Fig. 1-6, 24, 26-27) wherein the first conductive structures are connected to the second conductive structures based on fusion bonding or hybrid bonding (par 93)
With respect to Claim 30, Kao shows (Fig. 1-6, 24, 26-27) wherein the passive device portion of the first second-tier passive device is disposed over the substrate portion of the first second-tier passive device, and the second conductive structures are disposed on a lower surface of the first second-tier passive device and are connected to the set of TSVs of the first second-tier passive device
With respect to Claim 31, Kao shows (Fig. 1-6, 24, 26-27) wherein the substrate portion of the first second-tier passive device is disposed over the passive device portion of the first second-tier passive device, and the second conductive structures are disposed on a lower surface of the first second-tier passive device and are adjacent the metallization portion of the first second-tier passive device
With respect to Claim 33, Kao shows (Fig. 1-6, 24, 26-27) wherein the passive device portion of the first-tier passive device and the one or more passive device portions of the one or more second-tier passive devices comprise a deep trench capacitor, an integrated stack capacitor, a metal-insulator-metal capacitor, a metal-oxide-metal capacitor, or a combination thereof (par 55)
With respect to Claim 34, Kao shows (Fig. 1-6, 24, 26-27) wherein the electronic device comprises a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, or a device in an automotive vehicle (See also par 2).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Su (US 2024/0113159) in view of Lee (US 9,570,431).
With respect to Claim 4, Su shows (Fig. 2B,3B) most aspects of the current invention. However, Su does not show wherein a thickness of the semiconductor device ranges from 1.2 mm to 1.8 mm.
On the other hand, and in the same field of endeavor, Lee teaches (Fig 1) a semiconductor device (600) comprising a first-tier device (300), one or more second-tier devices (500) disposed over the first-tier device, wherein a thickness of the semiconductor device ranges from 0.795 mm to 0.805 mm. Lee teaches doing so to achieve a smaller form factor/profile for the device package by a thinning process to allow the semiconductor device to achieve a thickness of the desire range.
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have wherein a thickness of the semiconductor device ranges from 1.2 mm to 1.8 mm, in the device of Su, a taught by Lee to achieve a smaller form factor/profile for the device package by a thinning process to allow the semiconductor device to achieve a thickness of the desire range.
Regarding claim 4, the courts have held that differences in the thicknesses will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such thicknesses are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation.” See In re Aller, 220 F.2d 454, 456, 105, USPQ 233, 235 (CCPA 1955).
Since the applicant has not established the criticality of the thicknesses and similar thicknesses are known in the art (see e.g. Lee), it would have been obvious to one of the ordinary skill in the art to use these values in the device of Su.
Criticality: The specification contains no disclosure of either the critical nature of the claimed thicknesses or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ 2d 1934, 1936 (Fed Cir. 1990).
With respect to Claim 25, Su shows (Fig. 2B,3B) most aspects of the current invention. However, Su does not show wherein a thickness of the semiconductor device ranges from 1.2 mm to 1.8 mm.
On the other hand, and in the same field of endeavor, Lee teaches (Fig 1) a semiconductor device (600) comprising a first-tier device (300), one or more second-tier devices (500) disposed over the first-tier device, wherein a thickness of the semiconductor device ranges from 0.795 mm to 0.805 mm. Lee teaches doing so to achieve a smaller form factor/profile for the device package by a thinning process to allow the semiconductor device to achieve a thickness of the desire range.
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have wherein a thickness of the semiconductor device ranges from 1.2 mm to 1.8 mm, in the device of Su, a taught by Lee to achieve a smaller form factor/profile for the device package by a thinning process to allow the semiconductor device to achieve a thickness of the desire range.
Regarding claim 25, the courts have held that differences in the thicknesses will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such thicknesses are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation.” See In re Aller, 220 F.2d 454, 456, 105, USPQ 233, 235 (CCPA 1955).
Since the applicant has not established the criticality of the thicknesses and similar thicknesses are known in the art (see e.g. Lee), it would have been obvious to one of the ordinary skill in the art to use these values in the device of Su.
Criticality: The specification contains no disclosure of either the critical nature of the claimed thicknesses or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ 2d 1934, 1936 (Fed Cir. 1990).
Claims 8 and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Su (US 2024/0113159) in view of Karp (US 11,398,469).
With respect to Claim 8, Su shows (Fig. 2B,3B) most aspects of the current invention including wherein the first conductive structures are bonded to the second conductive structures. However, Su does not show further comprising first soldering structures that connect the first conductive structures to the second conductive structures.
On the other hand, and in the same field of endeavor, Karp teaches (Fig 1) a semiconductor device comprising a first-tier device (102), one or more second-tier devices (104) disposed over the first-tier device, the first-tier device further comprises first conductive structures (152) that are disposed on an upper surface of the first-tier device, the first second-tier device includes second conductive structures (154), the first conductive structures are bonded to the second conductive structures, and further comprising first soldering structures that connect the first conductive structures to the second conductive structures (column 6 lines 18-25). Karp teaches using a suitable bonding method of bonding of a first device to a second device such that the interconnects of the first device can be electrically and communicatively coupled to the other chips of the chip stack and signals can be transmitted in the interconnect of the first device and then vertically (through metallization and TSVs) to an appropriate device in the stack.
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have further comprising first soldering structures that connect the first conductive structures to the second conductive structures in the device of Su, a taught by Karp to use a suitable bonding method of bonding of a first device to a second device such that the interconnects of the first device can be electrically and communicatively coupled to the other chips of the chip stack and signals can be transmitted in the interconnect of the first device and then vertically (through metallization and TSVs) to an appropriate device in the stack.
With respect to Claim 29, Su shows (Fig. 2B,3B) most aspects of the current invention including wherein the first conductive structures are bonded to the second conductive structures. However, Su does not show further comprising first soldering structures that connect the first conductive structures to the second conductive structures.
On the other hand, and in the same field of endeavor, Karp teaches (Fig 1) a semiconductor device comprising a first-tier device (102), one or more second-tier devices (104) disposed over the first-tier device, the first-tier device further comprises first conductive structures (152) that are disposed on an upper surface of the first-tier device, the first second-tier device includes second conductive structures (154), the first conductive structures are bonded to the second conductive structures, and further comprising first soldering structures that connect the first conductive structures to the second conductive structures (column 6 lines 18-25). Karp teaches using a suitable bonding method of bonding of a first device to a second device such that the interconnects of the first device can be electrically and communicatively coupled to the other chips of the chip stack and signals can be transmitted in the interconnect of the first device and then vertically (through metallization and TSVs) to an appropriate device in the stack.
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have further comprising first soldering structures that connect the first conductive structures to the second conductive structures in the device of Su, a taught by Karp to use a suitable bonding method of bonding of a first device to a second device such that the interconnects of the first device can be electrically and communicatively coupled to the other chips of the chip stack and signals can be transmitted in the interconnect of the first device and then vertically (through metallization and TSVs) to an appropriate device in the stack.
Claims 11 and 32 are rejected under 35 U.S.C. 103 as being unpatentable over Su (US 2024/0113159) in view of Delacruz (US 2020/0075553).
With respect to Claim 11, Su shows (Fig. 2B,3B) most aspects of the current invention. However, Su does not show an encapsulation structure based on a molding material on the first-tier passive device and surrounding the one or more second-tier passive devices.
On the other hand, and in the same field of endeavor, Delacruz teaches (Fig 2A-2C) a semiconductor device comprising a first-tier device (232), one or more second-tier devices (212/214) disposed over the first-tier device, and further comprising an encapsulation structure (234) based on a molding material on the first-tier passive device and surrounding the one or more second-tier passive devices. Delacruz teaches providing the encapsulation surrounding the one or more second-tier devices to protect them from physical, chemical, and electrical damage (par 49).
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have further comprising an encapsulation structure based on a molding material on the first-tier passive device and surrounding the one or more second-tier passive devices in the device of Su, a taught by Delacruz the encapsulation surrounding the one or more second-tier devices helps protect them from physical, chemical, and electrical damage.
With respect to Claim 32, Su shows (Fig. 2B,3B) most aspects of the current invention. However, Su does not show an encapsulation structure based on a molding material on the first-tier passive device and surrounding the one or more second-tier passive devices.
On the other hand, and in the same field of endeavor, Delacruz teaches (Fig 2A-2C) a semiconductor device comprising a first-tier device (232), one or more second-tier devices (212/214) disposed over the first-tier device, and further comprising an encapsulation structure (234) based on a molding material on the first-tier passive device and surrounding the one or more second-tier passive devices. Delacruz teaches providing the encapsulation surrounding the one or more second-tier devices to protect them from physical, chemical, and electrical damage (par 49).
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have further comprising an encapsulation structure based on a molding material on the first-tier passive device and surrounding the one or more second-tier passive devices in the device of Su, a taught by Delacruz the encapsulation surrounding the one or more second-tier devices helps protect them from physical, chemical, and electrical damage.
Conclusion
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/Q.A.B/ Examiner, Art Unit 2814
/WAEL M FAHMY/ Supervisory Patent Examiner, Art Unit 2814