DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Arguments
Applicant’s arguments with respect to claims 1-11, 13, 15-17 and 19-22 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claims 1 and 17 (and their dependent claims) are objected to because of the following informalities: the applicant did not underline the amendments. So it becomes difficult for examiner to see all amendments and response accordingly. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, 10 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over TSENG et al. (US PGpub: 2013/0161739 A1), herein after TSENG, in view of CHIDAMBARAM P (US PGpub: 2006/0006461 A1), herein after CHIDAMBARAM and in further view of known arts like HSIEH; Fu-Yuan (US 2021/0126124 A1).
Regarding claim 1, TSENG teaches a high voltage switching device (Fig. 18 and par. [0014] to be seen together with Fig. 1 A and pars. [0012-0013]), including an integrated circuit that combines, in a unitary structure:
(a) a transistor structure (102) having a source (119), a channel (upper part of regions 107,105) adjacent the source, a gate structure (123) including regions (125,127, 129) overlaying the channel, and a drain ( 121) spaced from the channel;
(b) an integrated, co-fabricated drift region (109) formed between the channel and the drain;
(c) one or more dummy polysilicon structures (145, FIG. 1B is the use of a dummy gate structure 145…. The gate electrode layers 490, 491, and 492 may each include a polysilicon material or metal or a combination of these) (Fig. 1 B or Fig. 2 together with the last but one sentence of paragraph [0022]) formed overlaying the drift region (109) between the gate structure (123) and the drain (121 ), wherein the dummy polysilicon structure (145) is adjacent the gate structure (123); and
(d) at least one implant resistance pocket (103) formed within the drift region (109) and between the gate structure (123) and the first dummy polysilicon structure (145).
TSENG does not explicitly teach at least one electrical terminal in electrical contact with a corresponding implant resistance pocket of the at least one implant resistance pocket, wherein each of electrical terminal is configured to be coupled to a bias voltage source, and wherein the implant resistance pockets having electrical terminals control the resistance of the drift region upon application to such electrical terminals of a bias voltage from the bias voltage source.
However, In CHIDAMBARAM, formation of the transistor (52) according to Fig. 5C, wherein source (72), gates (66,66a), drain (74) and implant resistance pocket region (80) are exposed, is followed by a silicidation, that would imply that a contact is formed also over and in contact with the corresponding implant resistance pocket (80). It is evident to the person skilled in the art that, thereafter two options are possible: either leaving the region (80) unconnected and thus floating or to connect it to a terminal (source, drain, gate or external terminal). Choosing, in accordance with the circumstances, the first option (according to Fig. 5 and (Paragraph [0026) of Lee et al. (US PGpub: 2018/0012992 A1) and as disclosed for example in Fig. 1 B of TSENG) would appear obvious to the person skilled in the art, thereby arriving to a device according to claim 12.
Hence, it would have been obvious to one of ordinary skill in the art before the effective fling date of the claimed invention to use TSENG’s high voltage switching device to modify with teachings from CHIDAMBARAM such that mitigating or avoiding degradation of the DEMOS transistors in semiconductor products are possible.
TSENG or CHIDAMBARAM does not explicitly teach wherein each of electrical terminal is configured to be coupled to a bias voltage source, and wherein the implant resistance pockets having electrical terminals control the resistance of the drift region upon application to such electrical terminals of a bias voltage from the bias voltage source.
This is well known in the industry. Please see HSIEH; Fu-Yuan (US 2021/0126124 A1). FIG. 2, 216 is the terminal connecting implant resistance pocket 210 to control the resistance of the drift region by application of source bias. See US 20140077290 A1, FIG. 4 as well.
Hence, it would have been obvious to one of ordinary skill in the art before the effective fling date of the claimed invention to use TSENG and CHIDAMBARAM’s high voltage switching device to modify with teachings from HSIEH such that mitigating or avoiding degradation of the DEMOS transistors in semiconductor products are possible.
Regarding claim 2, TSENG teaches the invention of claim 1, wherein the first dummy polysilicon structure is adjacent to but spaced from the gate structure (Fig. 1 B wherein the dummy polysilicon structure (145) is adjacent to but spaced from the gate structure (123)).
Regarding claim 3, TSENG teaches the invention of claim 1, wherein there are at least two adjacent dummy polysilicon structures, further including, for each pair of adjacent dummy polysilicon structures, an implant resistance pocket formed within the drift region and between the pair of adjacent dummy poly-silicon structures (Paragraph [0042], it would be obvious to insert in the device of Fig. 1B, more than two adjacent dummy polysilicon/gate structures, each pair of adjacent dummy polysilicon structures including an implant resistance pocket/counter doped region formed within the drift region and between the pair of adjacent dummy polysilicon structures).
Regarding claim 4, TSENG teaches the invention of claim 1, wherein the source and drain are doped with a first dopant, the drift region is doped with a second dopant, and the at least one implant resistance pocket is doped with a third dopant (Fig. 1 B together with Fig. 7 and par. [0028], with Fig. 4A and par. [0020] and with Fig. 6B and par.[0025] the at least one implant resistance pocket is doped with a third dopant).
Regarding claim 5, TSENG teaches the invention of claim 1, wherein the source and drain are N+ doped, the drift region is N doped, and each of the at least one implant resistance pocket are P doped (Paragraph [0019]).
Regarding claim 6, TSENG teaches the invention of claim 1, wherein the source and drain are P+ doped, the drift region is P doped, and each of the at least one implant resistance pocket are N doped (Paragraph [0019]).
Regarding claim 7, TSENG teaches the invention of claim 1, wherein the gate structure partially overlays the drift region (Fig. 1 B, wherein the gate structure (123) partially overlays the drift region (109)).
Regarding claim 8, TSENG does not explicitly teach the invention of claim 1, wherein the gate structure includes doped polysilicon material.
However, CHIDAMBARAM discloses in Fig. 4C and Paragraph [0033]-[0034] to be seen together with Fig. 4D, wherein the gate structure (64,66,320) includes doped polysilicon material.
Hence, it would have been obvious to one of ordinary skill in the art before the effective fling date of the claimed invention to use TSENG’s high voltage switching device to modify with teachings from CHIDAMBARAM such that mitigating or avoiding degradation of the DEMOS transistors in semiconductor products are possible.
Regarding claim 10, TSENG teaches the invention of claim 1, wherein the at least one implant resistance pocket is formed by implantation of a dopant (Fig. 1 B together with fourth sentence of Paragraph [0014] , according to which the implant resistance pocket (103) is formed by implantation of a dopant).
Regarding claim 15, TSENG teaches, perhaps does not explicitly teach, the invention of claim 1, wherein the unitary structure is formed on a wafer including a substrate, a buried oxide layer formed on the substrate, and a silicon active layer formed on the buried oxide layer. When referring to CHIDAMBARAM Fig. 2, Paragraph [0021]-[0025]), disclosing the unitary structure ·as formed on a silicon-over-insulator (SOI) wafer thus including a substrate, a buried oxide layer formed on the substrate, and a silicon active layer formed on the buried oxide layer.).
Regarding claim 16, TSENG teaches the invention of claim 1, wherein the unitary structure is formed on a wafer including a substrate, a triple-well implant structure formed on the substrate, and a silicon active layer formed on the triple-well implant structure (forming the unitary structure on a wafer including a substrate, a triple-well implant structure formed on the substrate, and a silicon active layer formed on the triple-well implant structure is a well-known alternative option to forming the unitary structure on a SOI wafer)..
Claims 9, 11, 13, 17 and 19-22 are rejected under 35 U.S.C. 103 as being unpatentable over TSENG, in view of CHIDAMBARAM, in view of known arts like HSIEH and in further view of known arts like Tsai et al. (US 2014/0021558 A1 or US patent 8552495), herein after Tsai or Lee et al. (US PGpub: 2018/0012992 A1) or SHAFI et al. (2022/0005950 A1).
Regarding claim 9, TSENG does not explicitly teach the invention of claim 1, wherein the one or more dummy polysilicon structures include undoped polysilicon material . However, according to Lee, the dummy polysilicon structure and the gate structure include the same material (332, Fig. 5), that can be undoped polysilicon (Paragraph [0026) where it include undoped polysilicon material, doped polysilicon material, amorphous silicon or metal materials among other materials in order to select suitable material among many choices.
Regarding claim 11, TSENG teaches the invention of claim 1, wherein the at least one implant resistance pocket is formed by angled implantation of a dopant. Forming at least one implant resistance pocket by angled implantation of a dopant is a well-known process option, which does not seem to provide any unexpected technical effect on the transistor structure, thus not being inventive. See Parker et al. (US 20100244106 A1) in Paragraph [0334] and many others.
Product by process:
Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 777 F.2d 695,698,227 USPQ 964, 966 (Fed. Cir. 1985) (citations omitted) (Claim was directed to a novolac color developer. The process of making the developer was allowed. The difference between the inventive process and the prior art was the addition of metal oxide and carboxylic acid as separate ingredients instead of adding the more expensive pre-reacted metal carboxylate. The product-by-process claim was rejected because the end product, in both the prior art and the allowed process, ends up containing metal carboxylate. The fact that the metal carboxylate is not directly added, but is instead produced in-situ does not change the end product.). MPEP §2113.
Regarding claim 13, TSENG teaches the invention of claim 1, further including at least one electrical terminal in electrical contact with a corresponding dummy polysilicon structure of the one or more dummy polysilicon structures, wherein the dummy polysilicon structure having electrical terminals control the resistance of the drift region upon application of a bias voltage to the electrical terminals (consider document 2022/005950 A1, SHAFI et al.: Figs. 9 and 10 and Paragraph [0057-0061], together with par. [0034], the references in parentheses apply to this document) disclosing an integrated circuit comprising a lateral MOS transistor device, similar to the one of Fig. 8 of TSAI et al., wherein the at least one electrical terminal in the drive unit (64) is in electrical contact with a corresponding dummy polysilicon structure/dummy gate (82). This is indicated in SHAFI et al as applicable to many operational modes of the device (see in particular SHAFI et al: Paragraph [0034] and [0061]). It would then be obvious to apply this feature to a device according to Fig. 8 of D4, to control the resistance of the drift region upon application of a bias voltage to electrical terminals electrically connected to corresponding dummy polysilicon structure/dummy gate (311,312,313,314) (as required in TSAI et al. col. 6, I. 18-27). The teaching of Patent#8552495 82 (TSAI et al.) and SHAFI et al. appears as obviously applicable to the integrated circuit comprising a lateral MOS transistor device according to Fig. 1 B of D1, thereby arriving at a device according to claim 13.
Regarding claim 17, TSENG teaches A high voltage switching device, including an integrated circuit that combines, in a unitary structure:
(a) a transistor structure (102) having a source (119), a channel (upper part of regions 107,105) adjacent the source, a gate structure (123) including regions (125,127, 129) overlaying the channel, and a drain ( 121) spaced from the channel;
(b) an integrated, co-fabricated drift region (109) formed between the channel and the drain; and
(c) one or more dummy polysilicon structures (145) (Fig. 1 B or Fig. 2 together with the last but one sentence of paragraph [0022]) formed overlaying the drift region (109) between the gate structure (123) and the drain (121 ), wherein the dummy polysilicon structure (145) abuts the gate structure (123) (Fig. 1B wherein the dummy polysilicon structure (145) is adjacent to but spaced from the gate structure (123). Also see US patent#8552495 B2, Fig. 8) )
It perhaps does not explicitly teach dummy polysilicon structure abuts the gate
However, In US patent 8552495 or Tsai et al. US 20140021558 A1, as mentioned in Paragraph [0039], the device gate structure including a polysilicon gate electrode, wherein an entire upper surface of the gate electrode is silicided; and a dummy gate structure disposed over the second doped well, the dummy gate structure being separated from the device gate structure by a gap, wherein a region of the second doped well underneath the gap has a silicided surface. The motivation for doing so is that the gate stack can achieve better high-frequency performance.
Regarding claim 19, TSENG teaches the invention of claim 17, wherein the gate structure partially overlays the drift region (Fig. 1 B, wherein the gate structure (123) partially overlays the drift region (109). Also see US patent#8552495 B2 (TSAI et al.), Fig. 8).
Regarding claim 20, TSENG does not explicitly teach the invention of claim 17, wherein the one or more dummy polysilicon structures include undoped polysilicon material. However, according to Lee, the dummy polysilicon structure and the gate structure include the same material (332, Fig. 5), that can be undoped polysilicon (Paragraph [0026) or include undoped polysilicon material, doped polysilicon material, amorphous silicon or metal materials among other materials in order to select suitable material among many choices.
Regarding claim 21, TSENG teaches, perhaps does not explicitly teach, the invention of claim 17, wherein the unitary structure is formed on a wafer including a substrate, a buried oxide layer formed on the substrate, and a silicon active layer formed on the buried oxide layer. When referring to CHIDAMBARAM Fig. 2, Paragraph [0021]-[0025]), disclosing the unitary structure ·as formed on a silicon-over-insulator (SOI) wafer thus including a substrate, a buried oxide layer formed on the substrate, and a silicon active layer formed on the buried oxide layer.).
Regarding claim 22, TSENG teaches the invention of claim 17, wherein the unitary structure is formed on a wafer including a substrate, a triple-well implant structure formed on the substrate, and a silicon active layer formed on the triple-well implant structure (forming the unitary structure on a wafer including a substrate, a triple-well implant structure formed on the substrate, and a silicon active layer formed on the triple-well implant structure is a well-known alternative option to forming the unitary structure on a SOI wafer).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHEIKH MARUF whose telephone number is (571)270-1903. The examiner can normally be reached M-F, 8am-6pm EDT.
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/SHEIKH MARUF/Primary Examiner, Art Unit 2897
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