DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species III (fig 6) in the reply filed on 04/06/2026 is acknowledged. Claims 1-20 are pending in this application.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5 and 14 are rejected under 35 U.S.C. 102 (a) (1) as being anticipated by Shibata et al (US 20200279608A1).
Re claim 1 Shibata teaches, teaches, a semiconductor memory device (fig 3) comprising:
stacked interconnects (100) [0057] including a first interconnect layer (SGD1A, fig 3) [0084] and a second interconnect layer (SGD0A) [0084], the first interconnect layer (SGD1A, fig 3) including a first area (SU1, fig 3) [0080] and a second area (SU0, fig 3) [0080] arranged in a first direction (Y-direction, fig 3), the second interconnect layer (SGD0A, fig 3) [0080] being arranged above the first interconnect layer (SGD1A) in a second direction (Z-direction) intersecting the first direction (see fig 3), the second interconnect layer (SGD0A is not including SU1, fig 3) is not including the first area and including the second area (SGD0A is including SU0, fig 3);
a first memory pillar (middle CL, fig 3) [0064] arranged in the first area (SU1) and passing through the first interconnect layer (SGD1A, fig 3) in the second direction (Z direction); and
a second memory pillar (left CL, fig 3) arranged in the second area (SGD0A, fig 3) and passing through the first interconnect layer (SGD1A, fig 3) and the second interconnect layer (SGD0A, fig 3) in the second direction (Z- direction).
Re claim 5 Shibata teaches the device according to claim 1, wherein in the second direction (z-direction), a height from an upper end of the first memory pillar (upper end of middle CL, fig 3) to the first interconnect layer (SGD1A, fig 3) is approximately (more or less or roughly) equal to a height from an upper end of the second memory (left CL, fig 3) to the second interconnect layer pillar (upper end of left SGD0A, fig 3) [0063].
Re claim 14 Shibata teaches the device according to claim 1, further comprising: a first plug (middle V1, fig 2/3) [0060] arranged in the first area (SU1, fig 3) [0080] and provided on the first memory pillar (middle CL); and
a second plug (left V1, fig 2/3) arranged in the second area (SU0, fig 3) [0080] and provided on the second memory pillar (left CL), wherein in the second direction (z-axis), a length of the second plug (V1 in left CL) is different from a length of the first plug (V1 in middle CL).[0060].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Shibata in view of Ge et al (US 20200312865A1).
Re claim 4 Shibata teaches the device according to claim 1, the second interconnect layer (SGD0A, fig 3) is an interconnect layer positioned first from an upper end of the second memory pillar (left CL, fig 3) [0063].
Shibata does not teach the first interconnect layer is an interconnect layer positioned first from an upper end of the first memory pillar.
Ge teaches the first interconnect layer (4th 46-layer, fig 14A) [0121] is an interconnect layer (46, fig 14A) [0121] positioned first from an upper end of the first memory pillar (from top of 20, fig 14A) [0141].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught into the structure of to include as claimed
The ordinary artisan would have been motivated to modify Shibata based on the teaching of Ge in the above manner for the purpose to provide a manufacturing process friendly design at a lower cost but at a higher performance [0150].
Claims 6-9, and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Shibata et al (US20200279608A1).
Re claim 6 Shibata teaches the device according to claim 1, wherein a first transistor (STD1A, fig 5) is formed in a portion in which the second memory pillar (left CL, fig 3) intersects the first interconnect layer (SGD1A, fig 5), a second transistor (STD0A, fig 5) is formed in a portion in which the second memory pillar (left CL, fig 3) intersects the second interconnect layer (SGD0A, fig 5), a third transistor (left STD1A, fig 5) is formed in a portion in which the first memory pillar (middle CL, fig 3) intersects the first interconnect layer (SGD1A, fig 3, 5),
Shibata fig 3 does not teach a first threshold voltage of the first transistor is smaller than a second threshold voltage of the second transistor and is smaller than a third threshold voltage of the third transistor.
Shibata fig 22A [0195] teaches a first threshold voltage (L level, fig 22A) [0250] of the first transistor (STD1, shown in fig 20 ) is smaller than a second threshold voltage (last H level) of the second transistor (STD5) and is smaller than a third threshold voltage (middle H) of the third transistor (STD3).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Shibata to include a first threshold voltage of the first transistor is smaller than a second threshold voltage of the second transistor and is smaller than a third threshold voltage of the third transistor as claimed.
The ordinary artisan would have been motivated to modify Shibata in the above for the purpose of improve the reliability of the device.
Since it has been held that mere duplication of essential working parts of a device involves only routine skill in the art. St Regis Paper Co.v. Bemis Co., 193 USPQ 8.
Re claim 7 Shibata teaches the device according to claim 6, wherein the second threshold voltage (last H, fig 22A) [0195] is approximately (roughly or more or less) equal to the third threshold voltage (middle H, fig 22A) [0195].
Re claim 8 Shibata teaches the device according to claim 6, wherein in a case where a first voltage greater than the first threshold voltage (L level , fig 22A) and smaller than the third threshold voltage (middle H, fig 20/22) is applied to the first interconnect layer (SGD1A, fig 22A)[ and a second voltage greater than the second threshold voltage (last H level, fig 22)is applied to the second interconnect layer (SGD0A, fig 22), the second area is selected and the first area is not selected [0195].
Re claim 9 Shibata teaches the device according to claim 6, wherein the first transistor (middle STD01A), the second transistor (STD0A, fig 3, 5), and the third transistor (left STD01A )are select transistors [ Shibata, 0141].
Re claim 17 Shibata teaches a semiconductor memory device comprising:
stacked interconnects (SGD0A/SGD1A, fig 3) [0082] including a first interconnect layer (SGD1A, fig 3)[0084] and a second interconnect layer (SGD0A, fig 3) [0082], the first interconnect layer (SGD1A, fig 3) [0084] including a first area (SU1, fig 3) and a second area (SU0, fig 3) arranged in a first direction (Y-direction), the second interconnect layer (SGD0, fig 3)[0082] being spaced apart (by 72, fig 3) [0106] from the first interconnect layer (SGD1A, fig 3)[0082] in a second direction (Z-direction) intersecting the first direction (Y-direction), the second interconnect layer (SGDOA) including the second area (SU0, fig 3);
a plurality of first members (60, 62a, 62b, fig 3) [0117] spaced apart from each other in the first direction (Y-direction) with the stacked interconnects (SGD1A/SGD0) interposed therebetween, extending in the second direction (Z-drection) and a third direction (x-direction) intersecting the first direction (Y-dorection) and the second direction (Z-direction), and dividing the stacked interconnects ( by 62a/62b, fig 3) in the first direction (Y-direction);
a first semiconductor layer (middle 20, fig 3) [0063] arranged in the first area (SU1) and passing through the first interconnect layer (SGD1, fig 3) in the second direction (Z-direction); and
a second semiconductor layer (left 20, fig 3) [0063 arranged in the second area (SU0, fig 3), having an upper end (top of left 20), and passing through the first interconnect layer (SGD1A) and the second interconnect layer (SDG0, fig3) in the second direction (Z-direction).
Shibata (fig 3) does not teach the second semiconductor layer having the upper end located above an upper end of the first semiconductor layer in the second direction.
Shibata (fig 13) does teach the second semiconductor layer (75A, fig 13) [0208] having the upper end (upper end of 75A) located above an upper end of the first semiconductor layer (75B, fig 13) in the second direction (D3, fig 13).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Toshifumi into the structure of Shibata to include an upper end of the second semiconductor layer is located above an upper end of the first semiconductor layer in the second direction as claimed.
The ordinary artisan would have been motivated to modify Shibata based on the teaching of Toshifumi in the above manner for the purpose of improving reliability of a memory device [0018].
Re claim 18 Shibata teaches the device according to claim 17, wherein the second interconnect layer (SGD0, fig 3) [Shibata, 0082] is arranged above the first interconnect layer (SGD1A, fig 3) in the second direction (Z-direction).
Re claim 19. Shibata teaches the device according to claim 18, wherein the stacked interconnects further include, a third interconnect layer (bottom 70, fig 3) arranged below the first interconnect layer ( SGD1A, fig 3)[Shibata 0082] in the second direction (Z-axis), the third interconnect layer (bottom 70, fig 3) being passed through by the first memory pillar (middle CL, fig 3) and the second memory pillar (left CL, fig 3) and having an intersecting portion (intersecting portion of 70 and middle CL, fig 3) with the first memory pillar (middle CL) and an intersecting portion (intersecting portion of 70 and left CL, fig 3) with the second memory pillar (left CL), the intersecting portions being respectively provided with memory cell, select transistors (vertical transistor structure) [0068] are respectively formed in a portion in which the first memory pillar (middle CL) intersects the first interconnect layer (SGDA1) [Shibata 0082] and portions in which the second memory pillar (left CL) intersects the first interconnect layer (SGDA1) and the second interconnect layer (SGDA0), and the third interconnect layer (bottom 70) and the first interconnect layer (SGDA1) are approximately equal to each other in length in the first direction (Y-axis) between the plurality of first members (left/right 60, fig 3) [Shibata, 0155].
Re claim 20. Shibata teaches a semiconductor memory device (fig 3) comprising: a first bit line (BL, fig 5) [0065] ;
a source line (SL, fig 5) [0061];
first to n-th (where n is an integer equal to or greater than 2) memory strings (MS, fig 5) [0061] each including a plurality of memory cell transistors (MC, fig 5) [0068] coupled in series (fig 5), the first to n-th memory strings (MS, fig 5) each being coupled between the first bit line (BL) and the source line (SL);
a first word line (WL, fig 5) [0068]; and
first to n-th gate lines (SGD0A, SGD1A, SGD0B, SGD1B, fig 5) [0081];
wherein among the first to n-th memory strings (MS, fig 5) gates of corresponding memory cell transistors (MC, fig 5) of the plurality of memory transistors each are coupled to the first word line (WL, see fig 5), the first memory string (left MS) includes a first transistor (left MC, fig 5) between the first bit line (BL, fig 5) and the plurality of memory cell transistors (MC, fig 5) coupled in series (see fig 5), a drain (drain of STD0A, fig 5) of the first transistor being coupled to the first bit line (BL, fig 5), and a source (source of STD0A, fig 5) of the first transistor (Mc, fig 5) being coupled to one end of the plurality of memory cell transistors coupled in series (fig 5),
the n-th memory string (right MS, fig 5) includes first to n-th transistors (right MC) coupled in series (fig 5) between the first bit line (Bl) and the plurality of memory cell transistors (MC, fig 5) coupled in series (see fig 5), a drain of the n-th transistor (left top drain of STD0A, fig 5) of the first to n-th transistors (right MC) being coupled to the first bit line (BL, fig 5) and a source (source of left STD0A, fig 5) of the first transistor (MC, fig 5) of the first to n-th transistors (right Mc, fig 5) being coupled to one end of the plurality of memory cell transistors (MC, fig 5) coupled in series, gates of the first to n-th transistors in the n-th memory string are respectively coupled to the first to n-th gate lines (SGDA1, SGD0), and a gate (left SGS, fig 5) [0175] of the first transistor (left MC, fig 5) in the first memory string (left MS) is coupled to the first gate line (SGD1A, fig 5) together with a gate (left SGS, fig 5) of the first transistor in the n-th memory string, and of the first to n-th transistors (left to right MCs, fig 5) in the n-th memory string (left MS),
Shibata do not teach the n-th transistor has a threshold voltage greater than a transistor except for the n-th transistor, and the first transistor in the first memory string has a threshold voltage greater than the first transistor in the n-th memory string.
Shibata in fig 22A [0195] teaches the n-th transistor (transistor of the enhancement type) has a threshold voltage greater than a transistor (depletion type) [0195]except for the n-th transistor, and the first transistor (STD5, fig 20) in the first memory string (MS, fig 22) [00195] has a threshold voltage greater than the first transistor (STD1) in the n-th memory string [0195].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Shibata to include the n-th transistor has a threshold voltage greater than a transistor except for the n-th transistor, and the first transistor in the first memory string has a threshold voltage greater than the first transistor in the n-th memory string as claimed.
The ordinary artisan would have been motivated to modify Shibata in the above for the purpose of improve the reliability of the device.
Since it has been held that mere duplication of essential working parts of a device involves only routine skill in the art. St Regis Paper Co.v. Bemis Co., 193 USPQ 8.
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Shibata in view of Toshifumi et al (US20170076814A1).
Re claim 2 Shibata teaches, the device according to claim 1,
wherein the first memory pillar (middle CL, fig 3) [0063] includes a first semiconductor layer (20 in middle CL, fig 3) [0063] passing through the first interconnect layer (SGD1A, fig 3) in the second direction (Z-axis, fig 3), the second memory pillar (left CL, fig 3) includes a second semiconductor layer (20 in left CL, fig 3) passing through the first interconnect layer (SGD1A, fig 3) and the second interconnect layer (SGD0A, fig 3) in the second direction (Z-axis),
Shibata does not teach an upper end of the second semiconductor layer is located above an upper end of the first semiconductor layer in the second direction.
Toshifumi teaches an upper end of the second semiconductor layer (75A, fig 13) [0208] is located above an upper end of the first semiconductor layer (75B, fig 13) [0208] in the second direction (D3, fig 13).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Toshifumi into the structure of Shibata to include an upper end of the second semiconductor layer is located above an upper end of the first semiconductor layer in the second direction as claimed.
The ordinary artisan would have been motivated to modify Shibata based on the teaching of Toshifumi in the above manner for the purpose of improving reliability of a memory device [0018].
Re claim 3 Shibata in view of Toshifumi teach the device according to claim 2, wherein in the second direction (D3, fig 13) [Toshifumi, 0065], the upper end of the first semiconductor layer (75A, fig 13) [Toshifumi, 0204] is located between the first interconnect layer (BL, fig 13) and the second interconnect layer (72, fig 13) [0207], and the upper end of the second semiconductor layer (75B, fig 13) is located above the second interconnect layer (72, fig 13) [Toshifumi, 0067].
Claims 10-13 are rejected under 35 U.S.C. 103 as being unpatentable over Shibata et al in view of Rabkin et al (US20150318380A1).
Re claim 10 Shibata teaches the device according to claim 1, wherein the first memory pillar (middle CL, fig 3) [0059] includes a first semiconductor layer (middle 20, fig 3) [0068] passing through the first interconnect layer (SGD1A, fig 3) [0088] in the second direction (Z-axis), the second memory pillar (left CL, fig 3) [0059] includes a second semiconductor layer (left 20, fig 3) [0059] passing through the first interconnect layer (SGD1A, fig 3) [0059] and the second interconnect layer (SGD0A, fig 3)[0082] in the second direction (Z-axis), and a third area (middle area of SGD1A, fig 3) surrounded by the first interconnect layer (SGD1A, fig 3) of the first semiconductor layer (middle 20) and a fourth area (left area of SGD1A, fig 3) surrounded by the second interconnect layer (SGD0A, fig 3) of the second semiconductor layer (left 2, fig 3)
Shibata do not teach the third area and the fourth area include an impurity.
Rabkin teaches the third area (WL select gate in 303a , fig 3A-3B, 4B) [0171] and the fourth area (WL select gate 303b, fig 3A-3b, 4B) [0171] include an impurity (n-type or p-type).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Rabkin into the structure of Shibata to include the third area and the fourth area include an impurity as claimed.
The ordinary artisan would have been motivated to modify Shibata based on the teaching of Rabkin in the above manner for the purpose of improving performance, reduced power consumption, and better reliability [0087].
Re claim 11 Shibata in view of Rabkin teach the device according to claim 10, wherein a concentration (doping concentration of third area) of the impurity in the third area is approximately equal to a concentration of the impurity in the fourth area (doping concentration of fourth area) (doping concentration of 1.0×1015 to 1.0×1017 cm-3 or less) [Rabkin, 0237] .
Re claim 12 Shibata in view of Rabkin teach the device according to claim 10, wherein a concentration of the impurity in the fourth area (WL select gate 303b, fig 3A-3b, 4B) [0171] is greater [0171] than a concentration of the impurity in a fifth area (area of transistor body, fig 4B) surrounded by the first interconnect layer of the second semiconductor layer (doping concentration in the body area may be significantly lower than the dopant concentration in the word lines) [Rabkin, 0171].
Re claim 13 Shibata in view of Rabkin teach the device according to claim 10, wherein the impurity includes boron (boron) [Rabkin, 0094].
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Shibata in view of Lee et al (US20220293180A1)
Re claim 15 Shibata teaches the device according to claim 1, further comprising a plurality of first members (left/right 60, 62a, 62b fig 3) [0117] spaced apart from each other in the first direction (Y-axis) with the stacked interconnects (100, fig 3) [0082] interposed therebetween (fig 3), extending in the second direction (Z-axis) and a third direction (x-axis, fig 2, 3) intersecting the first direction (Y-axis) and the second direction (Z-axis), and dividing the stacked interconnects (100, fig 3) in the first direction (Y-axis), wherein the stacked interconnects (100, fig 3) further include a third interconnect layer (bottom 70, fig 3) arranged below the first interconnect layer ( SGD1A, fig 3) in the second direction (Z-axis), the third interconnect layer (bottom 70, fig 3) being passed through by the first memory pillar (middle CL, fig 3) and the second memory pillar (left CL, fig 3) and having an intersecting portion (intersecting portion of 70 and middle CL, fig 3) with the first memory pillar (middle CL) and an intersecting portion (intersecting portion of 70 and left CL, fig 3) with the second memory pillar (left CL), the intersecting portions being respectively provided with memory cell, select transistors (vertical transistor structure) [0068] are respectively formed in a portion in which the first memory pillar (middle CL) intersects the first interconnect layer (SGDA1) and portions in which the second memory pillar (left CL) intersects the first interconnect layer (SGDA1) and the second interconnect layer (SGDA0),
Shibata do not teach the third interconnect layer and the first interconnect layer are approximately equal to each other in length in the first direction between the plurality of first members.
Lee does teach the third interconnect layer (29, SSL2, fig 2) [0049] and the first interconnect layer (SSL_C, fig 2) [0049] are approximately equal to each other in length in the first direction (X-axis) between the plurality of first members (66a and 66b, fig 2) [0048].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Lee into the structure of Shibata to include the third interconnect layer and the first interconnect layer are approximately equal to each other in length in the first direction between the plurality of first members as claimed.
The ordinary artisan would have been motivated to modify Shibata based on the teaching of Lee in the above manner for the purpose of improving the degree of integration.[0217].
Since it has been held that mere duplication of essential working parts of a device involves only routine skill in the art. St Regis Paper Co.v. Bemis Co., 193 USPQ 8.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Shibata modified by Lee as applied to claim 15 in view of Shimabukuro et al (US20190221574A1).
Re claim 16 Shibata in view of Lee teach the device according to claim 15,
Shibata and Lee do not teach a first plug arranged in the first area and provided on the first memory pillar;
a second plug arranged in the second area and provided on the second memory pillar; and a fourth interconnect layer arranged above the stacked interconnects and electrically coupled to the first memory pillar and the second memory pillar via the first plug and the second plug, and
a fourth interconnect layer arranged above the stacked interconnects and electrically coupled to the first memory pillar and the second memory pillar via the first plug the second plug.
Shimabukuro teaches a first plug (left 88, fig 21A) [0160] arranged in the first area (left area, fig 21A) [0160] and provided on the first memory pillar (left 55, fig 21A) [0160];
a second plug (right 88, fig 13A) [0160] arranged in the second area (right side area, fig 13A) and provided on the second memory pillar (right 88, fig 13A) [0160]; and
a fourth interconnect layer (98, fig 21A) [0161] arranged above the stacked interconnects (46/32, fig 21A) [0160] and electrically coupled to the first memory pillar (55, fig 21A) and the second memory pillar (right 55, fig 21A) via the first plug (left 88) and the second plug (right 88)[0160].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Shimabukuro into the structure of Shibata and Lee to include a first plug arranged in the first area and provided on the first memory pillar;
a second plug arranged in the second area and provided on the second memory pillar; and a fourth interconnect layer arranged above the stacked interconnects and electrically coupled to the first memory pillar and the second memory pillar via the first plug and the second plug, and
a fourth interconnect layer arranged above the stacked interconnects and electrically coupled to the first memory pillar and the second memory pillar via the first plug the second plug as claimed.
The ordinary artisan would have been motivated to modify Shibata and Lee based on the teaching of Shimabukuro e in the above manner for the purpose of improving the functionality of the device.
Since it has been held that mere duplication of essential working parts of a device involves only routine skill in the art. St Regis Paper Co.v. Bemis Co., 193 USPQ 8.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRATIKSHA J LOHAKARE whose telephone number is (571)270-1920. The examiner can normally be reached Monday - Friday 7.30 am-4.30 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, EVA MONTALVO can be reached at 571-270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PRATIKSHA JAYANT LOHAKARE/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 6/23/26
Prosecution Insights