DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election filed on 11/21/2025, without traverse to prosecute the claims of Invention I, claims 1-18 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/15/2023 is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-8 and 10-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheng et al. (US 20190148515 A1).
Re Claim 1 Cheng teaches a transistor (FIG. 16B) comprising:
a gate (84) [0031] around a channel (20) [0038];
a top funneling inner spacer (top 65) directly upon a top surface of the channel (20); and
a source/drain (S/D) region (55) [0039] directly upon the top funneling inner spacer (65), the S/D region comprising a funneled interfacial region (55 vertically between 65) that includes a wide throat (outermost portion of 65 in direct contact with 55) and a narrow throat (55 in direct contact with 20) that is directly upon an end surface of the channel (FIG. 16B).
Re Claim 2 Cheng teaches the transistor of claim 1, wherein the wide throat (outermost portion of 65 in direct contact with 55) is an integral interface between the funneled interfacial region (55 vertically between 65) and a remainder of the S/D region (55, FIG. 16B).
Re Claim 3 Cheng teaches the transistor of claim 1, wherein the top funneling inner spacer (65) comprises a first receded non-orthogonal corner between a bottom surface of the top funneling inner spacer and an outer sidewall of the top funneling inner spacer (see image below).
The image below shows a modified fragment of FIG. 16 B to identify the first receded non-orthogonal corner
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Re Claim 4 Cheng teaches the transistor of claim 3, wherein the first receded non-orthogonal corner (use 65 in FIG. 17C as spacers) is chamfered.
Re Claim 5 Cheng teaches the transistor of claim 3, wherein the first receded non-orthogonal corner is filleted (refer to modified FIG. 16B fragment above).
Re Claim 6 Cheng teaches the transistor of claim 3, wherein the first receded non-orthogonal corner is non-linear (refer to modified FIG. 16B fragment above).
Re Claim 7 Cheng teaches the transistor of claim 3, wherein the funneled interfacial region (55 vertically between 65) further comprises one or more surfaces (use surface of 55 in direct contact with 65) that connect the narrow throat to the wide throat (FIG. 16B).
Re Claim 8 Cheng teaches the transistor of claim 3, wherein the end surface of the channel (20) is inset between the outer sidewall of the top funneling inner spacer (65) and an inner sidewall of the top funneling inner spacer (FIG. 16B).
Re Claim 10 Cheng teaches the transistor of claim 1, further comprising:
a bottom (use bottom 65) funneling inner spacer directly upon a bottom surface of the channel (use bottom 20, FIG. 16B).
Re Claim 11 Cheng teaches the transistor of claim 10, wherein the bottom funneling inner spacer (bottom 65) comprises a second receded non-orthogonal corner between a top surface of the bottom funneling inner spacer and an outer sidewall of the bottom funneling inner spacer (see image below).
The image below shows a modified fragment of FIG. 16 B to identify the second receded non-orthogonal corner
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Re Claim 12 Cheng teaches the transistor of claim 7, wherein the one or more surfaces that connect the narrow throat (surface of 55 in direct contact with 65) to the wide throat are juxtaposed directly upon the first receded non-orthogonal corner (FIG. 16B, 55 is in direct contact with the first receded non-orthogonal corner).
Re Claim 13 Cheng teaches a transistor (FIG. 16B) comprising:
a gate (84) [0031] around a channel (20) [0038]; and
a source/drain (S/D) region (55) [0039] directly upon a first funneling inner spacer (65), the S/D region comprising a funneled interfacial region (55 vertically between 65) that includes a wide throat (outermost portion of 65 in direct contact with 55) and a narrow throat (55 in direct contact with 20) that is directly upon an end surface of the channel (20, FIG. 16B).
Re Claim 14 Cheng teaches the transistor of claim 13, wherein the wide throat (outermost portion of 65 in direct contact with 55) is an integral interface between the funneled interfacial region (55 vertically between 65) and a remainder of the S/D region (55, FIG. 16B).
Re Claim 15 Cheng teaches the transistor of claim 13, wherein the wide throat has a larger circumference relative to the narrow throat (Integrate spacers 65 as shown in FIG. 17B into FIG. 16B. The wide throat has a larger circumference/cross-sectional area compared to the narrow throat, see image below).
FIG. 17B fragments are shown below to symbolize how the spacers are integrated into FIG. 16B to form the narrow and wide throats
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Re Claim 16 Cheng teaches the transistor of claim 13, wherein a linear surface (use 65 in FIG. 17B as spacers) connects the narrow throat and the wide throat (see image below claim 15).
Re Claim 17 Cheng teaches the transistor of claim 13, wherein a rounded surface (images above show rounded surfaces) connects the narrow throat and the wide throat (FIG. 16B, use surface shared by 65 and 55).
Re Claim 18 Cheng teaches the transistor of claim 13, wherein a non-linear surface (images above show rounded surfaces) connects the narrow throat and the wide throat (FIG. 16B, use surface shared by 65 and 55).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US 20190148515 A1) in view of Jeong et al. (US 20220238723 A1).
Re Claim 9 Cheng teaches the transistor of claim 1, but does not teach the end surface of the channel is concave.
Jeong teaches the end surface of the channel (120a) [0028] is concave (FIG. 1B).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Jeong into the structure of Cheng since Jeong teaches a gate all around transistor.
The ordinary artisan would have been motivated to modify Jeong in combination with Cheng in the above manner for the motivation of optimally shaping the channel regions to enable one design and build a transistor that functions optimally and can still be a minimum size as device continue to scale down in the art. [0003] states, “To improve the degree of integration of semiconductor devices, sizes of transistors need to be reduced. However, such size reduction of the transistors causes short channel effects.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH MARK SIPLING whose telephone number is (571)272-3269. The examiner can normally be reached 10 AM - 6 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KENNETH MARK SIPLING/ Examiner, Art Unit 2818
/DUY T NGUYEN/ Primary Examiner, Art Unit 2818 2/25/26