DETAILED ACTION
Examiner’s Note
The prior arts cited in PTO-892 but not used in the current rejection are related to the claimed novelty.
Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraphs, columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Election/Restrictions
Applicant’s election without traverse of Invention I (method of making semiconductor device), reflected in claims 1-9, 13-20 in the reply filed on 03/03/2026 is acknowledged. Claims 10-12 are cancelled.
Priority
This application constitutes a divisional application of the prior application 17/096,697, filed 11/12/2020, PAT 11,728,422.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 13-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zambrano; Raffaele (US 5585287 A, hereinafter Zambrano‘287).
Regarding independent claim 13, Zambrano‘287 teaches, “A method (fig. 1-8; related description)
forming a power MOSFET device (‘power MOS transistor’, fig. 1);
forming, a first body region (5) and a second body region (7), the first body region having a first conductivity type (“P-”), and the second body region (7) having the first conductivity type (“P“);
forming a drain region (1) having a second conductivity type (“N+”) different from the first conductivity type (P) in a portion of a semiconductor body under the first and the second body regions (5 and 7);
forming in the first and the second body regions (5 and 7), a first source region (6) and a second source region (8) having the second conductivity type (“N+”); and
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forming an insulated-gate region (10) facing the first body region (5), the second body region (7), the first source region (6), the second source region (8) and the drain region (1);
forming a first channel region (see annotation) in the first body region (5) between the first source region (6) and the drain region (1);
forming a second channel region (see annotation) the second body region (7) between the second source region (8) and the drain region (1)”.
Regarding claim 14, Ishida‘390 modified with Kono‘443 further teaches, “The method of claim 13 wherein the first body region (5) having a first conductivity value (“P-”), and the second body region (7) having a second conductivity value (P) higher than the first conductivity value”.
Claim 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ishida; Hiroyasu et al. (US 20070262390 A1, hereinafter Ishida‘390).
Regarding independent claim 21, Ishida‘390 teaches, “A method (fig. 1-8; ¶ [0034] - ¶ [0089]), comprising:
forming a first body region (4, fig. 2) of a first doping type (“P”) and a second body region (4) of the first doping type (“P”) in and at a first surface of a semiconductor body (1) of a second doping type (”n-”) different from the first doping type (“P”);
forming a first source region (15) of the second doping type (“n+”) in the first body region (4) defining a first channel region (see annotation) having a first channel length that extends from a first edge of the first body region to the first source region;
forming a second source region (15) of the second doping type (“n+”) in the second body region (4) defining a second channel region (see annotation) having a second channel length that extends from a second edge of the second body region to the second source region (15), wherein the second channel length is different from the first channel length; and
forming a gate region (13) enclosed within an oxide layer (16) on the first surfaced over the semiconductor body (1), the gate region (13) at least partially over the first source region (15) and the second source region (15) and over the first channel region and the second channel region (see annotation)”.
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Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Ishida‘390 as applied to claim 21 above, and further in view of Kono (US 20160276443 A1, hereinafter Kono‘443).
Regarding claim 22, Ishida‘390 teaches all the limitations described in claim 21.
Ishida‘390 further teaches, wherein the method of claim 21, further comprising forming a drain ((metallization)) (20) on a second surface of the semiconductor body (1) opposite to the first surface of the semiconductor body”.
But Ishida‘390 is silent upon the provision of wherein the drain electrode is made of metal.
However, Kono‘443 teaches a similar MOSFET (fig. 1), wherein the drain electrode (28) is made of metal (¶ [0037]).
Ishida‘390 and Kono‘443 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Ishida‘390 with the features of Kono‘443 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Ishida‘390 and Kono‘443 to use metal to form drain according to the teachings of Kono‘443 as this conventional in the semiconductor field.
Regarding claim 23, Ishida‘390 modified with Kono‘443 further teaches, “The method of claim 21, further comprising forming a source metallization (26, fig. 1, Kono‘443) covering the oxide (22), on the first body region (14) along the first surface of the semiconductor body (10), and on the second body region (14) along the first surface of the semiconductor body (10)”.
Allowable Subject Matter
Claims 1-9 are allowed.
Claims 15-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding independent claim 1, the closest prior art Ishida et al. (US 20070262390 A1) teach a MOSFET (fig. 2-3) comprising a source region (15), drain region(1a), body region (4), drift region (1b), wherein a channel length adjacent to a (first) body region is smaller than a channel length adjacent to another (second) body region, but are silent upon the provision of wherein the impurity concentration of the first body region is smaller than the impurity concentration of the second body region. None of the prior arts of record teaches a MOSFET device comprising a larger channel length adjacent to body region of low impurity concentration than a smaller channel length adjacent to body region of high impurity concentration to modify the MOSFET device of Ishida et al.
Regarding dependent claim 15, the closest prior art Zambrano; Raffaele (US 5585287 A, fig. 1) teaches a power MOSFET comprising a source region (8, 6), drain region(1), body region (5, 7), drift region (2), wherein the first body region (5) having a first conductivity value (“P-”), and the second body region (7) having a second conductivity value (P) higher than the first conductivity value”, but is silent upon the provision of wherein the second channel region to have a second channel length along the first direction that is smaller than the first channel length (fig. 1 of Zambrano teaches the opposite). There is no obvious reason to break the device of Zambrano to combine with any other MOSFET device (e.g., Ishida et al.) to teach a larger channel length adjacent to body region of low impurity concentration than a smaller channel length adjacent to body region of high impurity concentration.
Dependent claims 2-9 are allowed as they depend on allowed independent claim 1.
Dependent claims 16-20 are objected as they depend on objected dependent claim 15.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M HOQUE whose telephone number is (571)272-6266 and email address is mohammad.hoque@uspto.gov. The examiner can normally be reached 9AM-7PM EST.
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/MOHAMMAD M HOQUE/Primary Examiner, Art Unit 2817
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