DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I Species I in the reply filed on 12/8/25 is acknowledged. The traversal is on the ground(s) that there is no series burden and that both species contain grinding steps. This is not found persuasive because both species do not contain cutting steps using saw streets (Species II) which is what is claimed in claim 13 for example. Species I does not require a cutting step using saw streets and because of the divergent subject matter requiring a different field of search (e.g. searching different classes/subclasses or electronic resources, or employing different search strategies or search queries) the restriction is considered to be proper. Species I is identified as Claims 1-13, as claims 1-13 do not require a cutting step.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 5, 6, and 12 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Tang et al US 2022/0344796.
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Pertaining to claim 1, Tang teaches a method, comprising:
forming a device mounting layer on an uppermost trace conductor layer on a device side surface of a package substrate, by performing:
forming a device connection conductor layer 452 on the uppermost trace conductor layer 451, the device connection conductor layer having conductors at locations corresponding to post connect locations on a semiconductor die to be mounted to the device side surface of the package substrate see Figure 4A step 405 [0051];
forming a first layer of dielectric material 461 over and surrounding the conductors of the device connection conductor layer Figure 4A step 407 [0052];
grinding the first layer of dielectric material to expose the conductors of the device connection conductor layer Figure 4A step 409 [0053];
patterning device mounting land conductors 453/454 on the first layer of dielectric material 461, the device mounting land conductors directly contacting the conductors 452 of the device connection conductor layer, the device mounting land conductors at locations corresponding to the post connect locations on the semiconductor die to be mounted to the device side surface of the package substrate See Figure 4B step 411 and [0031] Tang teaches flip chip mounting a device to the multilayer package substrate;
depositing a second layer of dielectric material 463 over the device mounting land conductors 453/454; and
grinding the second layer of dielectric material to expose the device mounting land conductors 454 on the device mounting layer see Figure 4B step 417;
wherein the uppermost trace layer 451 of the package substrate has a first conductor pattern density that is the ratio of the area of trace conductors of the uppermost trace layer to the surface area of the package substrate, and the device mounting layer 454 has a second conductor pattern density that is the ratio of the area of the device mounting land conductors to the surface area of the device mounting layer, and the second pattern density is less than the first pattern density (there are less element 454 conductors in the same area as there are element 451 conductors, see Figure 4B step 419.
Pertaining to claim 5, Tang teaches the method of claim 1, wherein the device land conductors in the device land conductor layer are copper, gold, silver, palladium, tungsten, nickel, alloys or combinations thereof. [0046] of Tang
Pertaining to claim 6, Tang teaches the method of claim 1, wherein the conductors in the device land conductor layer are copper or copper alloy. [0046] of Tang
Pertaining to claim 12, Tang teaches the method of claim 1, wherein the first conductor pattern density is greater than 50%. See Figure 4B element 451 the density of the conductor pattern elements is greater than 50% of the area of substrate 471.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tang as applied to claim 1 above, and further in view of Ogawa et al US 2004/0056344.
Pertaining to claim 2, Tang teaches the method of claim 1, including flip chip mounting, but is silent on the flip chip mounting process. Ogawa teaches a flip chip mounting process comprising:
flip chip mounting the semiconductor die 6A/6B having the post connects (element 39 electrically interfaces with the chip’s “post connects”) on the device mounting layer 12 by forming solder joints 39 between the post connects and the device mounting land conductors 37 of the device mounting layer 12 see Figure 16; and
covering the semiconductor die 6A/6B, the device mounting layer 12, and a portion of the package substrate 2 with mold compound 7, the mold compound 7 spaced from the uppermost trace conductor layer 11 of the package substrate by the device mounting layer 12. See Figure 17.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to incorporate the teachings of Ogawa into the method of Tang by encapsulating the flip chip mounted devices. The ordinary artisan would have been motivated to modify Tang in the manner set forth above for at least the purpose of protecting the flip chip mounted devices.
Claim(s) 3, 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tang as applied to claim 1 above, and further in view of Ogawa et al US 2004/0056344 and further in view of Nakajima et al US 2010/0109052.
Pertaining to claim 3, Tang in view of Ogawa teaches the method of claim 2, but is silent with respect to passive components being connected alongside the flip chips. Nakajima teaches a device further comprising:
forming additional conductors in the device connection conductor layer at locations corresponding to the mounting positions of terminals of passive components to be mounted to the uppermost trace layer of the package substrate see Figure 7 marked up below. It would have been obvious to one of ordinary skill in the art at the time the invention was filed to include passive devices with flip chip mounted devices, the ordinary artisan would have looked to incorporate passive devices to expand functionality or as a matter of design necessity (ie the circuit required passive devices such as capacitors resistors and/or inductors for operation)
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Pertaining to claim 4, Tang/Ogawa in view of Nakajima teaches the method of claim 3, and further comprising forming additional land conductors in the device mounting land conductor layer LP201 (Nakakima see Figure 7 marked up above) corresponding to the mounting positions of terminals of passive components to be mounted to the uppermost trace layer of the package substrate.
Claim(s) 7-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tang as applied to claim 1 above, and further in view of Lim et al US 2021/0035961.
Pertaining to claims, 7, 8, 9, 10 and 11, Tang teaches the method of claim 1, but not the specific materials as claimed in claims 7, 8, 9, 10 and 11 such as ABF and a pre-molded leadframe. Lim teaches all of these features as laid out below for each of the claims respectively. It would have been within the scope of one of ordinary skill in the art at the time the invention was filed to combine the teachings of Tang and Lim to enable the substrate and dielectric formation steps of Tang to be performed according to the teachings of Lim because one of ordinary skill in the art at the time the invention was filed would have been motivated to look to alternative suitable methods of performing the disclosed substrate and dielectric formation steps of Tang and art recognized suitability for an intended purpose has been recognized to be motivation to combine. MPEP § 2144.07. Additionally, It would have been obvious to one having ordinary skill in the art at the time the invention was filed to select ABF as a dielectric material, since it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art. In re Leshin, 125 USPQ 416.
Lim teaches:
Pertaining to claim 7, Lim teaches wherein depositing the first layer of dielectric material and depositing the second layer of dielectric material comprises depositing Ajinomoto build-up film (ABF). [0059]
Pertaining to claim 8, Lim teaches wherein the depositing the first layer of dielectric material and depositing the second layer of dielectric material further comprises depositing Ajinomoto build-up film (ABF), acrylonitrile butadiene styrene (ABS), acrylonitrile styrene acrylate (ASA), or epoxy resin. [0059]
Pertaining to claim 9, Lim teaches wherein the package substrate comprises a pre-molded lead frame (PMLF). [0029]
Pertaining to claim 10, Lim teaches the package substrate comprises a pre-molded lead frame (PMLF), a multilayer package substrate formed using additive manufacturing, a molded interconnect substrate (MIS), or a laminate substrate. [0029]
Pertaining to claim 11, Lim teaches the package substrate comprises a multilayer package substrate formed using Ajinomoto build-up film (ABF) as a dielectric. [0059]
Note: reasons to combine are the same for each of claims 7 through 11 and is stated above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS J TOBERGTE whose telephone number is (571)272-6458. The examiner can normally be reached M-F 7:30-4:30.
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/NICHOLAS J TOBERGTE/Primary Examiner, Art Unit 2817