Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Status of the Claims
Applicant’s election, without traverse, of Group II, claims 1-15 in the reply filed on June 16th, 2025 is acknowledged. Non-elected invention of Group I, claims 16-21, have been withdrawn from consideration. Claims 1-21 are pending.
Action on merits of Group II, claims 1-15 as follows.
Priority
Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
The information disclosure statements (IDSs) submitted on June 16, 2023 and August 08t, 2025, have been considered by the examiner.
Drawings
The drawings filed on 06/16/2023 are acceptable.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1-8 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (KR 2021/0086472, hereinafter as Kim ‘472) in view of Wu (US 2017/0243537, hereinafter as Wu ‘537).
Regarding Claim 1, Kim ‘472 teaches a display apparatus, comprising:
a substrate (Fig. 17a, (100); [0031]) including a display area (AA; [0032]), and a non-display area (BA and PD; [0032]) that includes a wiring portion (signal wires; [0036]), a dam portion (106; [0067]) and a gate driving portion (see Fig. 17c; [0018]);
a pixel (PA; [0032]) in the display area, electrically connected to a gate line and a data line crossing the gate line (see para. [0036]), the pixel including a light emitting element (600; [0032]), wherein the light emitting element includes a first electrode (610; [0033]), a light emitting layer (620; [0034]) and a second electrode (630; [0035]);
a first thin film transistor (210; [0037]) configured to provide a driving current to the light emitting element according to a data voltage applied from the data line, the first thin film transistor (210) including a first semiconductor layer (211; [0037]);
a second thin film transistor (220; [0044]) configured to control driving of the first thin film transistor according to a gate voltage applied from the gate line, the second thin film transistor including a second semiconductor layer (221; [0044]);
and a fourth thin film transistor (250; [0082]) in the gate driving portion (gate driver area (GIP); [0082]), configured to apply gate voltages to the second thin film transistor and the third thin film transistor, the fourth thin film transistor including a fourth semiconductor layer (251; [0082]), wherein the fourth semiconductor layer (251) is at a different layer from the second semiconductor layer (221).
Thus, Kim ‘472 is shown to teach all the features of the claim with the exception of explicitly the limitations: “a third thin film transistor configured to sense a threshold voltage of the first thin film transistor to control driving of the first thin film transistor, the third thin film transistor including a third semiconductor layer; and the fourth semiconductor layer is at a different layer from the first semiconductor layer and the third semiconductor layer”.
Wu ‘537 teaches a third thin film transistor (Fig. 1, (T2); [0028]) configured to sense a threshold voltage of the first thin film transistor (T1; [0028]) (e.g. detect and compensate the deviation in the threshold voltage of the first transistor (T1); see para. [0028]) to control driving of the first thin film transistor (T1), the third thin film transistor including a third semiconductor layer (see para. [0072]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Kim ‘472 by having a third thin film transistor configured to sense a threshold voltage of the first thin film transistor to control driving of the first thin film transistor, the third thin film transistor including a third semiconductor layer for the purpose of enhancing the evenness of the display images and improving the display effect of display panels (see para. [0097]) as suggested by Wu ‘537.
Thus, Kim ‘472 and Wu ‘537 are shown to teach all the features of the claim with the exception of explicitly the limitations: “the fourth semiconductor layer is at a different layer from the first semiconductor layer and the third semiconductor layer”.
However, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the fourth semiconductor layer that can be arranged in any order, thus the fourth semiconductor layer is at a different layer from the first semiconductor layer and the third semiconductor layer involves only routine skill in the art. In re Einstein, 8 USPQ 167. A person of ordinary skills in the art is motivated to perform the arrangement of the fourth semiconductor layer such that the fourth semiconductor layer is at a different layer from the first semiconductor layer and the third semiconductor layer when this allows a good flow with the other steps in the fabrication process.
Examiner notes that claim 1 contains functional limitations “configured to provide a driving current to the light emitting element according to a data voltage applied from the data line”; “configured to control driving of the first thin film transistor according to a gate voltage applied from the gate line”; “configured to sense a threshold voltage of the first thin film transistor to control driving of the first thin film transistor” and “configured to apply gate voltages to the second thin film transistor and the third thin film transistor” (emphasis added). According to MPEP 2173(05) g. " the use of functional language in a claim may fail “to provide a clear-cut indication of the scope of the subject matter embraced by the claim” and thus be indefinite. In re Swinehart, 439 F.2d 210, 213 (CCPA 1971). For example, when claims merely recite a description of a problem to be solved or a function or result achieved by the invention, the boundaries of the claim scope may be unclear. Halliburton Energy Servs., Inc. v. M-I LLC, 514 F.3d 1244, 1255 (Fed. Cir. 2008)”. In the instant case, “configured to provide a driving current to the light emitting element according to a data voltage applied from the data line”; “configured to control driving of the first thin film transistor according to a gate voltage applied from the gate line”; “configured to sense a threshold voltage of the first thin film transistor to control driving of the first thin film transistor” and “configured to apply gate voltages to the second thin film transistor and the third thin film transistor” is nothing else than the result achieved by the invention. Functional language in a device claim is directed to the device per se, no matter which of the device’s functions is referred to in the claim. See In re Ludtke and Sloan, 169 USPQ 563 at 567, and In re Swinehart, 169 USPQ 226, both of which make it clear that it is the patentability of the device per se which must be determined in a “functional language” claim and not the patentability of the function, and that an old or obvious device alleged to perform a new function is not patentable as a device, whether claimed in “functional language” terms or not. Note that the above case law makes clear that in such cases applicant has the burden of showing that a prior art device that appears reasonably capable of performing the allegedly novel function is in fact incapable of doing so. See MPEP § 2114. See also In re Schreiber, 44 USPQ2d 1429, 1432 (Fed. Cir. 1997) (Claim to a spout having “taper … such as to by itself jam up the popped popcorn before the end of the cone and permit the dispensing of only a few kernels at a shake,” anticipated by an oil can spout having the same shape as spout Applicant disclosed as being adapted for dispensing said only a few kernels) and In re King, 231 USPQ 136 (Fed. Cir, 1986) ("It did not suffice merely to assert that [the cited prior art] does not inherently achieve [the claimed function], challenging the PTO to prove the contrary by experiment or otherwise. The PTO is not equipped to perform such tasks") for discussions of the roles of examiner and applicant in determining when and how functional limitations distinguish a claim from prior art disclosing the same structure.
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Fig. 17a (Kim ‘472)
Regarding Claim 2, Kim ‘472 teaches a first upper gate electrode (213; [0082]) above the first semiconductor layer (211); a second upper gate electrode (223; [0084]) above the second semiconductor layer (221);
Wu ‘537 teaches a third upper gate electrode (see para. [0101]).
Thus, Kim ‘472 and Wu ‘537 are shown to teach all the features of the claim with the exception of explicitly the limitations: “a third upper gate electrode above the third semiconductor layer”.
However, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the third upper gate electrode that can be arranged in any order, thus a third upper gate electrode above the third semiconductor layer (e.g. the top gate TFT) involves only routine skill in the art. In re Einstein, 8 USPQ 167. A person of ordinary skills in the art is motivated to have third upper gate electrode above the third semiconductor layer when this improves the performance of the display device.
Regarding Claim 3, Kim ‘472 and Wu ‘537 are shown to teach all the features of the claim with the exception of explicitly the limitations: “a distance between the third semiconductor layer and the third upper gate electrode is greater than a distance between the first semiconductor layer and the first upper gate electrode, and wherein a capacitance between the third semiconductor layer and the third upper gate electrode is smaller than a capacitance between the first semiconductor layer and the first upper gate electrode”.
However, it has been held to be within the general skill of a worker in the art to select a distance between the third semiconductor layer and the third upper gate electrode is greater than a distance between the first semiconductor layer and the first upper gate electrode, and wherein a capacitance between the third semiconductor layer and the third upper gate electrode is smaller than a capacitance between the first semiconductor layer and the first upper gate electrode on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. A person of ordinary skills in the art is motivated to have a distance between the third semiconductor layer and the third upper gate electrode is greater than a distance between the first semiconductor layer and the first upper gate electrode, and wherein a capacitance between the third semiconductor layer and the third upper gate electrode is smaller than a capacitance between the first semiconductor layer and the first upper gate electrode when this improves the performance of the display device.
Regarding Claim 4, Kim ‘472 and Wu ‘537 are shown to teach all the features of the claim with the exception of explicitly the limitations: “the third upper gate electrode is at a different layer from the first upper gate electrode”.
However, it has been held to be within the general skill of a worker in the art to select the third upper gate electrode is at a different layer from the first upper gate electrode on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. A person of ordinary skills in the art is motivated to have the third upper gate electrode is at a different layer from the first upper gate electrode when this improves the performance of the display device.
Regarding Claim 5, Kim ‘472 and Wu ‘537 are shown to teach all the features of the claim with the exception of explicitly the limitations: “a distance between the third semiconductor layer and the third upper gate electrode is greater than a distance between the second semiconductor layer and the second upper gate electrode, and wherein a capacitance between the third semiconductor layer and the third upper gate electrode is smaller than a capacitance between the second semiconductor layer and the second upper gate electrode”.
However, it has been held to be within the general skill of a worker in the art to select a distance between the third semiconductor layer and the third upper gate electrode is greater than a distance between the second semiconductor layer and the second upper gate electrode, and wherein a capacitance between the third semiconductor layer and the third upper gate electrode is smaller than a capacitance between the second semiconductor layer and the second upper gate electrode on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. A person of ordinary skills in the art is motivated to have a distance between the third semiconductor layer and the third upper gate electrode is greater than a distance between the second semiconductor layer and the second upper gate electrode, and wherein a capacitance between the third semiconductor layer and the third upper gate electrode is smaller than a capacitance between the second semiconductor layer and the second upper gate electrode when this improves the performance of the display device.
Regarding Claim 6, Kim ‘472 and Wu ‘537 are shown to teach all the features of the claim with the exception of explicitly the limitations: “the third upper gate electrode is at a different layer from the second upper gate electrode”.
However, it has been held to be within the general skill of a worker in the art to select the third upper gate electrode is at a different layer from the second upper gate electrode on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. A person of ordinary skills in the art is motivated to have the third upper gate electrode is at a different layer from the second upper gate electrode when this improves the performance of the display device.
Regarding Claim 7, Kim ‘472 teaches the top surfaces of the first upper gate electrode (213) are covered by the first interlayer insulating film (214; [0088]); and the top surfaces of the second upper gate electrode (223) are covered by the second interlayer insulating film (224; [0091]).
Kim ‘472 and Wu ‘537 are shown to teach all the features of the claim with the exception of explicitly the limitations: “the top surfaces of the first upper gate electrode, second upper gate electrode, and third upper gate electrode are covered by a same material”.
However, it has been held to be within the general skill of a worker in the art to select the top surfaces of the first upper gate electrode, second upper gate electrode, and third upper gate electrode are covered by a same material on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. A person of ordinary skills in the art is motivated to have the top surfaces of the first upper gate electrode, second upper gate electrode, and third upper gate electrode are covered by a same material when this allows a good flow with the other steps in the fabrication process.
Regarding Claim 8, Kim ‘472 teaches bottom surfaces of the first (213) and second (223) upper gate electrodes.
Kim ‘472 and Wu ‘537 are shown to teach all the features of the claim with the exception of explicitly the limitations: “bottom surfaces of the first upper gate electrode, second upper gate electrode, and third upper gate electrode contain different materials”.
However, it has been held to be within the general skill of a worker in the art to select the bottom surfaces of the first upper gate electrode, second upper gate electrode, and third upper gate electrode contain different materials on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. A person of ordinary skills in the art is motivated to have the top surfaces of the bottom surfaces of the first upper gate electrode, second upper gate electrode, and third upper gate electrode contain different materials when this allows a good flow with the other steps in the fabrication process.
Regarding Claim 15, Kim ‘472 teaches an encapsulation portion (700; [0115]) disposed on the light emitting element (600; [0114]), the encapsulation portion including a first encapsulation layer (710), a second encapsulation layer (720) and a third encapsulation layer (730); and a touch portion (811/812; [0117]) on the encapsulation portion (700).
Claims 9-11 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Kim ‘472 and Wu ‘537 as applied to claim 2 above, and further in view of Yan (US 2017/0162606, hereinafter as Yan ‘606).
Regarding Claim 9, Kim ‘472 and Wu ‘537 are shown to teach all the features of the claim with the exception of explicitly the limitations: “a first lower gate electrode below the first semiconductor layer; a second lower gate electrode below the second semiconductor layer; and a third lower gate electrode below the third semiconductor layer”.
Yan ‘606 teaches a first lower gate electrode (Fig. 14, (14); [0032] and [0035]) below the first semiconductor layer (27; [0032]); a second lower gate electrode (Fig. 14, (14); [0032] and [0035]) below the second semiconductor layer (17; [0031]); and a third lower gate electrode (Fig. 14, (14); [0032] and [0035]) below the third semiconductor layer (17; [0032]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Kim ‘472 and Wu ‘537 by having a first lower gate electrode below the first semiconductor layer; a second lower gate electrode below the second semiconductor layer; and a third lower gate electrode below the third semiconductor layer in order to shield the light into the semiconductor layers (e.g. light shielding layer, see para. [0035]) as suggested by Yan ‘606.
Regarding Claim 10, Yan ‘606 teaches a distance between the second semiconductor layer (17) and the second lower gate electrode (14) is greater than a distance between the first semiconductor layer (27) and the first lower gate electrode (14) (see Fig. 14).
Further, it has been held to be within the general skill of a worker in the art to have a distance between the second semiconductor layer and the second lower gate electrode is greater than a distance between the first semiconductor layer and the first lower gate electrode on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. A person of ordinary skills in the art is motivated to have a distance between the second semiconductor layer and the second lower gate electrode is greater than a distance between the first semiconductor layer and the first lower gate electrode when this allows a good flow with the other steps in the fabrication process.
Regarding Claim 11, Yan ‘606 teaches a distance between the third semiconductor layer (17) and the third lower gate electrode (14) is greater than a distance between the first semiconductor layer (27) and the first lower gate electrode (14) (see Fig. 14).
Further, it has been held to be within the general skill of a worker in the art to have a distance between the third semiconductor layer and the third lower gate electrode is greater than a distance between the first semiconductor layer and the first lower gate electrode on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. A person of ordinary skills in the art is motivated to have a distance between the third semiconductor layer and the third lower gate electrode is greater than a distance between the first semiconductor layer and the first lower gate electrode when this allows a good flow with the other steps in the fabrication process.
Regarding Claim 13, Yan ‘606 teaches the first thin film transistor further includes a first source electrode and a first drain electrode (29s/19d; [0027]), wherein the second thin film transistor further includes a second source electrode and a second drain electrode (17s/17d; [0027]), wherein the third thin film transistor further includes a third source electrode and a third drain electrode (29s/19d; [0027]).
Kim ‘472 teaches the source electrode is electrically connected to the lower gate electrode (231; [0052]).
Regarding Claim 14, Kim ‘472 teaches the fourth semiconductor layer (251; [0082]) comprises a polycrystalline semiconductor material (LTPS; [0082]).
Claims 12 is rejected under 35 U.S.C. 103 as being unpatentable over Kim ‘472 and Wu ‘537 as applied to claim 2 above, and further in view of Kim (US 2021/0249491, hereinafter as Kim ‘491).
Regarding Claim 12, Kim ‘472 and Wu ‘537 are shown to teach all the features of the claim with the exception of explicitly the limitations: “the first semiconductor layer and the second semiconductor layer comprise an oxide semiconductor material, and wherein the third semiconductor layer comprises an oxide semiconductor material”.
Kim ‘491 teaches the first semiconductor layer (ACT2; [0112] and [0115]) and the second semiconductor layer (ACT4; [0112] and [0115]) comprise an oxide semiconductor material, and wherein the third semiconductor layer (ACT5; [0235]) comprises an oxide semiconductor material (see para. [0170] and [0235]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Kim ‘472 and Wu ‘537 by having the first semiconductor layer and the second semiconductor layer comprise an oxide semiconductor material, and wherein the third semiconductor layer comprises an oxide semiconductor material in order to provide a display device capable of realizing high resolution by highly integrating semiconductor elements for driving light emitting elements.(see para. [0006]) as suggested by Kim ‘491.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following patents are cited to further show the state of the art with respect to semiconductor devices:
Yun et al. (US 2022/0165806 A1)
Moon et al. (US 2021/0202634 A1)
Zhou et al. (US 2018/0166025 A1)
Hiramatsu et al. (US 2017/0278869 A1)
Maruyama (US 2017/0278916 A1)
For applicant’s benefit portions of the cited reference(s) have been cited to aid in the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DZUNG T TRAN whose telephone number is (571) 270-3911. The examiner can normally be reached on M-F 8 AM-5PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DZUNG TRAN/
Primary Examiner, Art Unit 2893