DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 19-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 10/15/2025.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang et al. (U.S. Publication No. 2021/0336012 A1; hereinafter Huang)
With respect to claim 1, Huang discloses a microelectronic device comprising: a nanosheet transistor (see ¶[0014]) that includes a first source/drain [610] and a second source/drain [610/1702]; a frontside contact [716] connected to the first source/drain and a backside contact [1202/1402] connected to the second source/drain; and a plurality of isolation layers [1302/1502] located beneath the nanosheet transistor, wherein the second source/drain extends through the plurality of isolation layers to connect with the backside contact (see Figure 22B).
With respect to claim 2, Huang discloses wherein one of the plurality of isolation layers is in direct contact with a backside surface of the first source/drain (See Figure 22B).
With respect to claim 3, Huang discloses wherein a backside surface of the first source/drain and a backside surface of the second source/drain are located at different heights (see Figure 22B).
With respect to claim 4, Huang discloses wherein the plurality of isolation layers includes at least a first dielectric layer [1502] and a second dielectric layer [1302] (see Figure 22B).
With respect to claim 5, Huang discloses wherein the first dielectric layer and the second dielectric layer are comprised of the same dielectric material (See ¶[0056] and ¶[0060])
With respect to claim 6, Huang discloses a bonding seam located between the first dielectric layer and the second dielectric layer (see Figure 22B).
With respect to claim 7, Huang discloses wherein the first dielectric layer [1502] is in contact with a backside surface of the first source/drain, and wherein the first dielectric layer is in contact with a sidewall of the second source/drain (See Figure 22B).
With respect to claim 8, Huang discloses wherein the backside contact is in contact with the second dielectric layer (see Figure 22B).
With respect to claim 9, Huang discloses wherein the first dielectric layer and the second dielectric layer are comprised of the different dielectric material (See ¶[0056] and ¶[0060]).
With respect to claim 10, Huang discloses the microelectronic device comprising: a nanosheet transistor (See ¶[0014]) that includes a first source/drain [610] and a second source/drain [610/1702]; a frontside contact [716] connected to the first source/drain and a backside contact [1202/1402] connected to the second source/drain; a plurality of isolation layers [1302/1502] located beneath the nanosheet transistor, wherein the second source/drain extends through the plurality of isolation layers to connect with the backside contact, wherein the backside contact extends into the plurality of isolation layers to connect with the second source/drain (see Figure 22B).
With respect to claim 11, Huang discloses wherein one of the plurality of isolation layers [1502] is in direct contact with the backside surface of the first source/drain (See Figure 22B).
With respect to claim 12, Huang discloses wherein a backside surface of the first source/drain and a backside surface of the second source/drain are located at different heights (see Figure 22B).
With respect to claim 13, Huang discloses wherein the plurality of isolation layers includes at least a first dielectric layer [1502] and a second dielectric layer [1302] (See Figure 22B).
With respect to claim 14, Huang discloses wherein the first dielectric layer and the second dielectric layer are comprised of the same dielectric material (See ¶[0056] and ¶[0060])
With respect to claim 15, Huang discloses a bonding seam located between the first dielectric layer and the second dielectric layer (see Figure 22B).
With respect to claim 16, Huang discloses wherein the first dielectric layer [1502] is in contact with a backside surface of the first source/drain, and wherein the first dielectric layer is in contact with a sidewall of the second source/drain (See Figure 22B).
With respect to claim 17, Huang discloses wherein the backside contact is in contact with the second dielectric layer (See Figure 22B).
With respect to claim 18, Huang discloses wherein the first dielectric layer and the second dielectric layer are comprised of the different dielectric material (See ¶[0056] and ¶[0060]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Dutta et al. (U.S. Publication No. 2024/0114694 A1) discloses a backside via for a gate all around structure
Huang et al. (U.S. Publication No. 2024/0355708 A1) discloses a backside via for a gate all around structure
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/JONATHAN HAN/Primary Examiner, Art Unit 2818
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