Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) based on an application filed in Japan on June 29, 2022, and receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. It should be noted that in order to effectively benefit from the foreign priority date, an English translation of the certified copy (of the foreign application as filed) filed together with a statement that the translation of the certified copy is accurate must be presented.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on June 16, 2023 was filed in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Title
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested:
--NAND-type Storage Device Including A Conductive Layer For Stable Erase Operations--
Specification
The disclosure is objected to because of the following informalities:
On page 37, the statement “the surface of the conductive layer 90 (an upper surface and a lower surface) is electrically separated from the conductive layers 21a and 21b.” isn’t clear as to its intent. For a conductive material (excluding exotic quantum materials) the bulk and surfaces are non-distinguishable for conduction pathing, and thus specifying the surface doesn’t change the nature of conduction being referenced. In this case, the conductive layer 90 is ‘electrically separated’ from the conductive layers 21a and 21b (not truly insulated from), but it is the Examiner’s understanding that this recitation is instead intended to describe the structure as in Fig. 21. Therefore, the Examiner suggests that the line on page 37 referred to above should read
-- the surface of the conductive layer 90 (an upper surface and a lower surface) is physically separated from the conductive layers 21a and 21b by the interlayer 50. --
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 7 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 7, the limitation “a third conductive layer electrically isolating the plurality of the first conductive layers and the plurality of the second conductive layers from each other” is unclear. A conductive layer, by definition, cannot electrically isolate other elements. Examiner notes that, as disclosed in the Specification, the conductive layer 90, is an example of a third conductive layer. However, this conductive layer 90 is not truly electrically isolated from a first conductive layer (21a as an example) or from a second conductive layer (21b as an example), as is inherent to the NAND structure and the erasing operations described in the Specification, see pages 37 and 38: since the conductive layer 90 applies a voltage to the electrode parts, and these parts apply a reverse bias voltage with the first/second conductive layers, they are not electrically isolated.
For the purposes of this Office Action, the limitation of Claim 7 as quoted above shall be read by the Examiner as follows:
--a third conductive layer vertically--
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Takekida (U.S. Pub. 2020/0302974), hereinafter Takekida.
Regarding Claim 1, Takekida teaches a semiconductor storage device ((1); Figs. 1 and 14-16, Paragraph [0027]), comprising:
-a first multi-layered body including a plurality of first conductive layers (wiring layers (22) and (23) below element (41) hereinafter (MLB1); Fig. 16, Paragraphs [0064] and [0129]), the first conductive layers being stacked in layers in a first direction (Z-axis; Fig. 16), the first conductive layers being electrically isolated from each other (via interlayer insulating layers (40); Fig. 16, Paragraph [0085]),
-a second multi-layered body (wiring layers (22) and (23) above element (41), hereinafter (MLB2); Fig. 16), above the first multi-layered body (MLB1), the second multi-layered body including a plurality of second conductive layers (upper (22)s and (23)), the second conductive layers being stacked in layers in the first direction (Z-axis), the second conductive layers being electrically isolated from each other (via interlayer insulating layers (40));
-a first columnar part in the first multi-layered body (‘lower pillar’ (LP); Fig. 16, Paragraph [0066]), the first columnar part extending in the first direction (Z-axis), the first columnar part including a first charge storage film (lower memory film (27) includes a lower charge storage film (29); Figs. 6 and 16, Paragraph [0073]) and a first semiconductor layer (lower (26); Fig. 16, Paragraph [0072]), the first columnar part having an upper end (top of (LP); Fig. 16);
a second columnar part in the second multi-layered body (‘upper pillar’ (UP); Fig. 16, Paragraph [0066])), the second columnar part extending in the first direction (Z-axis) the second columnar part including a second charge storage film (upper charge storage film (29) as part of upper (27)) and a second semiconductor layer (upper (26)), the second columnar part having a lower end (bottom of (UP); Fig. 16);
-an electrode part inside at least one of the upper end of the first columnar part (e.g. (50A); Fig. 16, Paragraph [0131]) and the lower end of the second columnar part (e.g. (50C); Fig. 16, Paragraph [0131]), the electrode part having an end surface (either the bottom of (50A) or the top of (50C), respectively); and
-an impurity-diffusion region protruding from the end surface of the electrode part (as within the regions (DT1) and (DT2); Fig. 16, Paragraphs [0115] and [0137]-[0139]), toward an inside of the first semiconductor layer (either lower or upper (26)) in the first direction (Z-axis).
Regarding Claim 2, Takekida teaches a semiconductor storage device ((1); Figs. 1 and 14-16, Paragraph [0027]) according to Claim 1, wherein:
-the electrode part inside the upper end of the first columnar part (LP) is a first electrode part (50A),
-the electrode part inside the lower end of the second columnar part (UP) is a second electrode part (50C), and
-both the first electrode part (50A) and the second electrode part (50C) are in the semiconductor storage device ((10) as in Fig. 16).
Regarding Claim 3, Takekida teaches a semiconductor storage device ((1); Figs. 1 and 14-16, Paragraph [0027]) according to Claim 2, further comprising:
-an electrode body ((50B); Fig. 16, Paragraph [0131]) electrically connecting the first electrode part (50A) and the second electrode part (50C).
Regarding Claim 4, Takekida teaches a semiconductor storage device ((1); Figs. 1 and 14-16, Paragraph [0027]) according to Claim 2, wherein:
-a position of the lower end of the first electrode part (e.g. at the bottom surface of (50A); Fig. 16) is lower than a position of a first conductive layer (e.g. at the top surface of the lower (23)) located at an uppermost position of the plurality of the first conductive layers (the lower (22)s and (23)), and
-a position of the upper end of the second electrode part (e.g. at the top surface of (50C); Fig. 16) is above a position of a second conductive layer (e.g. at the bottom surface of the upper (23)) located at a lowermost portion of the plurality of the second conductive layers (the upper (22)s and (23)).
Regarding Claim 5, Takekida teaches a semiconductor storage device ((1); Figs. 1 and 14-16, Paragraph [0027]) according to Claim 2, wherein:
-a length of the first electrode part in a second direction (length in the Y-axis of (50A); Fig. 16) crossing (perpendicularly, though limitation strictly doesn’t require it to be) the first direction (Z-axis) is substantially the same as a length of the first semiconductor layer in the second direction (length in the Y-axis of the lower (26); Fig. 16), and a length of the second electrode part in the second direction (length in the Y-axis of (50C), at the top; Fig. 16) is substantially the same as a length of the second semiconductor layer in the second direction (length in the Y-axis of the upper (26); Fig. 16).
Regarding Claim 6, Takekida teaches a semiconductor storage device ((1); Figs. 1 and 14-16, Paragraph [0027]) according to Claim 3, wherein:
-a material used to form the electrode body (50B), a material used to form the first electrode part (50A), and a material used to form the second electrode part (50C) are the same as each other (doped polysilicon; Paragraph [0131]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Takekida in view of Song (U.S. Pub. 2021/0217770), hereinafter Song.
Regarding Claim 7, Takekida teaches a semiconductor storage device ((1); Figs. 1 and 14-16, Paragraph [0027]) according to Claim 3, upon which it depends, but does not teach:
-a third conductive layer vertically between the first multi-layered body and the second multi-layered body, the third conductive layer being electrically connected to the electrode body.
Song teaches a semiconductor storage device ((600); Figs. 3 and 6, Paragraph [0101]) including an electrode body ((610); Fig. 6, Paragraph [0102]) between a first multi-layered body ((322); Figs. 3 and 6, Paragraph [0082]) and a second multi-layered body ((321); Figs. 3 and 6, Paragraph [0082]), further comprising:
-a third conductive layer ((620); Fig. 6, Paragraph [0102]) vertically between the first multi-layered body (322) and the second multi-layered body (321), the third conductive layer (620) being electrically connected to the electrode body (610).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Song into the device of Takekida such that it further comprised a third conductive layer vertically between the first multi-layered body and the second multi-layered body, the third conductive layer being electrically connected to the electrode body. This would be due to the fact that doing so would allow for a bulk erase operation without a deterioration of cell charateristics (Song, Paragraphs [0044]-[0046]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DMITRI MIHALIOV whose telephone number is (571)270-5220. The examiner can normally be reached weekdays 7:30 - 17:30 US Eastern Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.M./ Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/ Supervisory Patent Examiner, Art Unit 2812