DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species I, claims 1-11, in the reply filed on 10/27/25 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2 and 5-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Beyne et al. (US 2018/0145030).
Regarding claim 1, Beyne discloses a semiconductor device, comprising:
a substrate (6, fig. 1 and paragraph 0046) comprising a first region (right side comprising devices with furthest gate strip 1, fig. 1 and paragraph 0046), a second region (middle region comprising devices with middle two gate strips 1, fig. 1 and paragraph 0046), and a third region (input/output routing section on left side, fig. 11 and paragraph 0060);
a first device disposed on a front side of the substrate, in the first region, wherein the first device includes a first active region (5, figs. 1-2), a first gate (1, fig. 1) crossing the first active region, and first source/drain regions on the first active region on both sides of the first gate (2, fig. 1 and paragraph 0046);
a second device disposed on the front side of the substrate, in the second region (middle transistors, fig. 1 and paragraph 0046);
a through-electrode (83, fig. 11 and paragraph 0060) penetrating through the substrate in the third region (6, fig. 11 and paragraph 0060);
a contact plug electrically connected to the first source/drain regions (20, figs. 1-2 and paragraph 0047);
a buried conductive layer (9, figs. 1-2 and paragraphs 0046-0047) connected to the contact plug, and penetrating through a first device isolation layer (7, fig. 2 and paragraphs 0046-0047) defining the first active region in the substrate and extending deeper into the substrate than the first device isolation layer (fig. 2); and
a back side buried interconnection structure disposed adjacent to a back side of the substrate that opposes the front side of the substrate (17/19, fig. 2 and paragraph 0047),
wherein the back side buried interconnection structure includes a back side buried conductive layer disposed on the buried conductive layer in the first region and connected to the buried conductive layer (17/19, figs. 1-2 and paragraph 0047), and
wherein the back side buried interconnection structure is not disposed on the back side of the substrate in the second region (middle section, figs. 1-2).
Regarding claim 2, Beyne further discloses wherein the back side buried interconnection structure further comprises a back side buried insulating layer (55, figs. 6C-D and paragraph 0057) surrounding side surfaces of the back side buried conductive layer (57, fig. 6D and paragraph 0057).
Regarding claim 5, Beyne further discloses wherein an upper surface of the back side buried insulating layer and an upper surface of the back side buried conductive layer are substantially coplanar (top surface, fig. 6D).
Regarding claim 6, Beyne further discloses wherein a lower surface of the back side buried insulating layer is on a level lower than a lower surface of the back side buried conductive layer (57, fig. 6D).
Regarding claim 7, Beyne further discloses wherein an upper portion of the buried conductive layer protrudes onto a lower surface of the back side buried insulating layer (60/61, fig. 7 and paragraph 0058).
Regarding claim 8, Beyne further discloses wherein the active region comprises a first base active region and at least one first active fin, wherein the at least one first active fin protrudes from the first base active region and extends in a first direction (5, figs. 1-2 and paragraph 0046).
Regarding claim 9, Beyne further discloses wherein the first device further comprises a plurality of first channel layers spaced apart from the at least one first active fin, and surrounded by the first gate (1, fig. 1 and paragraph 0046).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Beyne et al. (US 2018/0145030) in view of Sparks et al. (US 5213999).
Regarding claim 3, Beyne discloses the semiconductor device of claim 2, as mentioned above. Beyne further discloses wherein the buried insulating layer is a blanket deposition and does not explicitly disclose wherein the back side buried insulating layer is disposed in a trench recessed from the back side of the substrate toward the front side of the substrate in the first region, wherein the back side buried conductive layer is disposed in the back side buried insulating layer. However, such trench based process was well known at the time of filing and would therefore be deemed obvious to one of ordinary skill in the art at the time of filing. To illustrate the well known teachings of forming a trench into a semiconductor substrate to reach a buried conductive layer, forming an insulating layer in the trench and filling with a conductive contact, see Sparks (figs. 5-8 and Col. 4).
Regarding claim 4, the process of the trench filled dielectric taught above would yeild a step is provided by the trench on the back side of the substrate in the first region, wherein the back side of the substrate is substantially flat in the second region, all things else being equal.
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Beyne et al. (US 2018/0145030).
Regarding claims 10-11, Beyne discloses the semiconductor device of claim 1, as mentioned above. Beyne further discloses wherein the devices are a CMOS layout of finFET transistors (paragraph 0046). Beyne does not explicitly disclose wherein the second device is a static-random-access memory (SRAM) including a second active region, a second gate crossing the second active region, and second source/drain regions disposed on the second active region on both sides of the second gate or wherein the second device is a bipolar junction transistor including a base, an emitter, and a collector. However, Beyne’s invention is directed to buried interconnects with back side access with vias. Beyne explicitly discloses wherein the CMOS layout is just a single case use and is not limited to such (paragraph 0046). Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to use such interconnect structures with an SRAM device or a BJT since such were common in the art.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Patent Application Publication 2018/0175034 discloses a relevant dual side processing device.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS M MENZ whose telephone number is (571)272-1877. The examiner can normally be reached Monday-Friday 8:00am-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DOUGLAS M MENZ/Primary Examiner, Art Unit 2897 2/3/26