DETAILED ACTION
This correspondence is in response to the communications received May 5, 2026. Claims 1-20 are pending. Claims 1, 10 and 19 have been amended.
Response to Arguments
Applicant has perfected the foreign priority by submitting a certified English translation of the foreign document KR10-2022-0077813 on May 5, 2026. This submission antedates the previously applied prior art of Park et al. (US 2024/0032298), which is now no longer available as prior art. Further search for the “gate pad portion” (which is the feature that Park was used to disclose) reveals several available prior art references such as:
1.) Kwon et al. (US 2022/0384477) Fig. 6, element 130A, “gate pad portion 130A which is greater in thickness than another portion of the gate line 130 in the vertical direction (the Z direction)”, ¶ 0081.
2.) Kwon et al. (US 12,089,407) Fig. 6.
3.) Lee et al. (US 2020/0091071) Fig. 2B, shows “gate pad portion 158P”.
4.) Lee et al. (US 10,950,544) Fig. 2B.
5.) Kwon et al. (US 2023/0097021) Fig. 2A, 27p, “gate pad”, ¶ 0037.
6.) (April 5, 2022) Oh et al. (US 2022/0336358) Fig. 1A, where “GP” are gate pads, ¶ 0059. These are merely where the contact via makes electrical contact with the control gate, there is no extra thickness, but the structure is still referred to as a “gate pad”, which satisfies claim 1, which does not specify the thicker aspect, as shown in the disclosure.
7.) Lee et al. (US 2023/0005949) Fig. 2A, where ¶ 0064 discusses gate pads.
8.) Chung et al. (US 2022/0310639) Fig. 2A, ¶ 0055.
9.) Kim (US 2022/0254807) Fig. 2A
10.) (Samsung) Hwang et al. (US 2021/0358933) Figs. 5B and 5C, show the obvious variant nature of flat vs thick gate pads (claim 20 calls them this)
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11.) Kwon et al. (US 2022/0384477) Fig. 6, element 130A, “gate pad portion 130A which is greater in thickness than another portion of the gate line 130 in the vertical direction (the Z direction)”, ¶ 0081. Also Kwon et al. (US 12,089,407) Fig. 6.
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Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 112
Applicant’s amendment to claims 1 and 19 have overcome the 112 rejections, which are hereby withdrawn.
Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 1, the Applicant discloses in Fig. 4-7, a semiconductor device comprising:
a substrate (50) including a memory cell region (MCR) and a connection region (CON);
a plurality of gate electrodes (131, 130, 133) in the memory cell region (MCR) of the substrate and arranged apart from one another in a vertical direction perpendicular to a top surface of the substrate,
the plurality of gate electrodes including at least one ground selection line (GSL 131) and a plurality of word lines (133) arranged at a vertical level which is higher than the at least one ground selection line (133 over 131);
a pair of gate stack separation insulation layers (DLI or WLI) passing through the plurality of gate electrodes (130) and extending in a first horizontal direction in the memory cell region and the connection region of the substrate (along X-direction); and
a pad structure (151, 152) including a plurality of pad layers in the connection region (CON) of the substrate, connected to respective ones of the plurality of gate electrodes (pads are the places where vertical vias connect to the control gates), arranged in a staircase shape in the first horizontal direction (staircase orientation along X-direction), and arranged in a staircase shape in a second horizontal direction perpendicular to the first horizontal direction,
the at least one ground selection line (GSL 131) comprising a plurality of ground selection line cut regions (CR, see Fig. 7), and each of the plurality of ground selection line cut regions being arranged apart from edges of the plurality of pad layers in the second horizontal direction (CR not at 151).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 3 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20210210431) in view of Kim et al. (US 2022/0254792, hereinafter referred to as ‘792).
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Regarding claim 1, the prior art of Kim discloses in Figs. 4, 5 and 9, a semiconductor device (see title, “Semiconductor Device …”) comprising:
a substrate (“substrate 200”, ¶ 0098) including a memory cell region (CELL, ¶ 0073) and a connection region (CNR, ¶ 0050);
a plurality of gate electrodes (“The ground selection lines GSL1 and GSL2 may be used as the gate electrodes of the ground selection transistors GST, the wordlines WL1 through WLn may be used as the gate electrodes of the memory cell transistors MCT, and the string selection lines SSL1 through SSL3 may be used as the gate electrodes of the string selection transistors SST.”, ¶ 0043, hereinafter referred to as ‘PGE’) in the memory cell region of the substrate (at CELL) and arranged apart from one another in a vertical direction perpendicular to a top surface of the substrate (noted PGE are stacked in vertical direction), the plurality of gate electrodes including at least one ground selection line (“GSL”) and a plurality of word lines (“WL”) arranged at a vertical level which is higher than the at least one ground selection line (plural WL are above GSL);
a pair of gate stack separation insulation layers (“he block isolation regions WLC, the cell gate cutting regions CAC, and the extension gate cutting regions CNC may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and a high-k material having a greater dielectric constant than silicon oxide.”, ¶ 0077, hereinafter referred to as ‘SIL’) passing through the plurality of gate electrodes (SIL shown cutting vertically through PGE in Fig. 5) and extending in a first horizontal direction in the memory cell region (SIL in CELL) and the connection region of the substrate (SIL in CNR); and
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a pad structure (in CNR, the regions of the PGE, WL where vertical via contacts 152 make contact thereto) including a plurality of pad layers (plural extension surfaces of PGE/WL which extend beyond the upper neighboring WL so as to be vertically accessible to 152, hereinafter referred to as ‘PL’) in the connection region of the substrate (in CNR), connected to respective ones of the plurality of gate electrodes (connected at least to WL of PGE), arranged in a staircase shape in the first horizontal direction (staircase shape as can be seen in Figs. 4 and 5, along Y-direction), and arranged in a staircase shape in a second horizontal direction perpendicular to the first horizontal direction (and the staircase shape can be seen in Fig. 9’s X-direction at the equivalent pad structure regions, CNR),
the at least one ground selection line (“ground selection line GSL”, ¶ 0031) comprising a plurality of ground selection line cut regions (“The through structures THV may be formed in the through regions THR of the extension region EXT. Each of the through structures THV may include a plurality of second insulating patterns 115 that are spaced apart from one another and are stacked on the first substrate 100.”, ¶ 0085, hereinafter referred to as ‘GCR’), and each of the plurality of ground selection line cut regions being arranged apart from edges of the plurality of pad layers in the second horizontal direction (the GCR are formed away from PL in the Y-direction).
Kim discloses the functional equivalent to the “a pad structure including a plurality of pad layers”, but does not explicitly disclose these elements to be “pads”.
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‘792 discloses in Figs. 1A-1B, a pad structure including a plurality of pad layers (“gate pads 201P”, ¶ 0028).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of “a pad structure including a plurality of pad layers”, as disclosed by ‘792 in the system of Kim, for the purpose of providing a location where a vertical via contact can electrically connect to the plural control gate electrodes, to be able to operate each memory site. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 2, the prior art of Kim et al. disclose the semiconductor device of claim 1, wherein each of the plurality of ground selection line cut regions does not vertically overlap the edges of the plurality of pad layers (GCR are horizontally offset from CNR/PL, thus they do not vertically overlap).
Regarding claim 3, the prior art of Kim et al. disclose the semiconductor device of claim 1, further comprising a plurality of ground selection line insulation layers respectively filling the plurality of ground selection line cut regions of the at least one ground selection line (“The through structures THV may be formed in the through regions THR of the extension region EXT. Each of the through structures THV may include a plurality of second insulating patterns 115 that are spaced apart from one another and are stacked on the first substrate 100.”, ¶ 0085), wherein each of the plurality of ground selection line insulation layers does not vertically overlap the edges of the plurality of pad layers (GCR are horizontally offset from CNR/PL, thus they do not vertically overlap).
Regarding claim 19, the prior art of Kim discloses in Figs. 4, 5 and 9, an electronic system (system of memory devices in CELL and control circuitry in 200 as can be seen in Fig. 5) comprising:
a main substrate (“substrate 200”, ¶ 0097);
a semiconductor device (cell region CELL, ¶ 0073, and a connection region CNR, ¶ 0050) on the main substrate (on 200, see Fig. 5); and
a controller electrically connected to the semiconductor device on the main substrate (“The peripheral circuit elements PT may configure a peripheral circuit (e.g., the peripheral circuit 30 of FIG. 1) that controls operations of memory cells.”, ¶ 0099),
the semiconductor device comprising:
a substrate (“substrate 100”, ¶ 0052) including a memory cell region (cell region CELL, ¶ 0073) and a connection region (connection region CNR, ¶ 0050);
a plurality of gate electrodes (“The ground selection lines GSL1 and GSL2 may be used as the gate electrodes of the ground selection transistors GST, the wordlines WL1 through WLn may be used as the gate electrodes of the memory cell transistors MCT, and the string selection lines SSL1 through SSL3 may be used as the gate electrodes of the string selection transistors SST.”, ¶ 0043, hereinafter referred to as ‘PGE’) in the memory cell region of the substrate (at CELL) and arranged apart from one another in a vertical direction perpendicular to a top surface of the substrate (noted PGE are stacked in vertical direction), the plurality of gate electrodes including at least one ground selection line (“GSL”) and a plurality of word lines (“WL”) arranged at a vertical level which is higher than the at least one ground selection line (plural WL are above GSL);
a pair of gate stack separation insulation layers (“he block isolation regions WLC, the cell gate cutting regions CAC, and the extension gate cutting regions CNC may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and a high-k material having a greater dielectric constant than silicon oxide.”, ¶ 0077, hereinafter referred to as ‘SIL’) passing through the plurality of gate electrodes (SIL shown cutting vertically through PGE in Fig. 5) and extending in a first horizontal direction in the memory cell region (SIL in CELL) and the connection region of the substrate (SIL in CNR); and
a pad structure (in CNR, the regions of the PGE, WL where vertical via contacts 152 make contact thereto) including a plurality of pad layers (plural extension surfaces of PGE/WL which extend beyond the upper neighboring WL so as to be vertically accessible to 152, hereinafter referred to as ‘PL’) in the connection region of the substrate (in CNR), connected to respective ones of the plurality of gate electrodes (connected at least to WL of PGE), arranged in a staircase shape in the first horizontal direction (staircase shape as can be seen in Figs. 4 and 5, along Y-direction), and arranged in a staircase shape in a second horizontal direction perpendicular the first horizontal direction (and the staircase shape can be seen in Fig. 9’s X-direction at the equivalent pad structure regions, CNR),
the at least one ground selection line (GSL) comprising a plurality of ground selection line cut regions (“The through structures THV may be formed in the through regions THR of the extension region EXT. Each of the through structures THV may include a plurality of second insulating patterns 115 that are spaced apart from one another and are stacked on the first substrate 100.”, ¶ 0085, hereinafter referred to as ‘GCR’), and each of the plurality of ground selection line cut regions being arranged apart from edges of the plurality of pad layers in the second horizontal direction (the GCR are formed away from PL in the Y-direction).
Kim discloses the functional equivalent to the “a pad structure including a plurality of pad layers”, but does not explicitly disclose these elements to be “pads”.
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‘792 discloses in Figs. 1A-1B, a pad structure including a plurality of pad layers (“gate pads 201P”, ¶ 0028).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of “a pad structure including a plurality of pad layers”, as disclosed by ‘792 in the system of Kim, for the purpose of thicker contact regions which will improve adhesion and sustain mechanical integrity during the method steps creating the memory device. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of “a pad structure including a plurality of pad layers”, as disclosed by Park in the system of Kim, for the purpose of providing a location where a vertical via contact can electrically connect to the plural control gate electrodes, to be able to operate each memory site. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20210210431) in view of Kim et al. (US 2022/0254792, hereinafter referred to as ‘792) in view of Kwon et al. (US 2022/0384477). It is further noted, that if the 102(b)(2)(C) exception is invoked with regard to the Kwon reference, there are a plurality of other commonly owned references which are available as prior art to teach the thick gate pad portion, and would subsequently be applied in further rejections on this subject matter, see comments in the Response to arguments section.
Regarding claim 7, the prior art of Kim et al. disclose the semiconductor device of claim 1, however Kim et al. do not disclose,
“wherein each of the plurality of gate electrodes has a first thickness in the vertical direction, and each of the plurality of pad layers has a second thickness which is greater than the first thickness in the vertical direction.”
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Kwon discloses in Fig. 6, element 130A, “gate pad portion 130A which is greater in thickness than another portion of the gate line 130 in the vertical direction (the Z direction)”, ¶ 0081.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of “wherein each of the plurality of gate electrodes has a first thickness in the vertical direction, and each of the plurality of pad layers has a second thickness which is greater than the first thickness in the vertical direction.”, as disclosed by Kwon in the system of Kim, for the purpose of thicker contact regions which will improve adhesion and sustain mechanical integrity during the method steps creating the memory device. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
REASONS FOR ALLOWANCE
Claims 11-18 are allowable.
The following is an Examiner's statement of reasons for allowance: The three dimensional memory device as recited in the claims of the instant invention fail to be taught by the prior art cited of interest.
Regarding claim 11, the prior art of Kim et al. (US 20210210431) discloses in Figs. 4, 5 and 9, a three dimensional memory device, but fails to disclose the specific characteristic recited in the claims of the instant invention e.g. the combination of claimed features of a substrate, memory cell region, connection region, gate electrodes, ground selection line, word lines, ground selection line cut regions, gate stack separation insulation layers, channel structures, pad structure, first through third pad layers, ground selection line insulation layers, dummy stack opening portions and their relative orientation with respect to each other.
Claims 4-6, 8-10 and 20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
4. The semiconductor device of claim 3, wherein the plurality of gate electrodes between the pair of gate stack separation insulation layers comprise one block, the at least one ground selection line included in the one block comprises a first ground selection line and a second ground selection line electrically isolated from each other and arranged apart from each other in the second horizontal direction, and the plurality of ground selection line insulation layers are arranged apart from each other between the first ground selection line and the second ground selection line.
5. The semiconductor device of claim 3, wherein each of the plurality of ground selection line insulation layers comprises a recessed top surface bent downward.
6. The semiconductor device of claim 3, wherein a portion of each of the plurality of word lines, at a position vertically overlapping a corresponding ground selection line cut region, comprises a bending portion bent downward, each of the plurality of ground selection line cut regions has a first width in the second horizontal direction, and the bending portion has a second width which is less than the first width in the second horizontal direction.
8. The semiconductor device of claim 1, further comprising a plurality of dummy stack opening portions between the pair of gate stack separation insulation layers to pass through the plurality of gate electrodes and extend in the first horizontal direction, in a plan view, and at least one of the plurality of dummy stack opening portions and a corresponding ground selection line cut region are on a straight line in the first horizontal direction.
9. The semiconductor device of claim 1, wherein the plurality of pad layers comprise:
a first pad layer;
a second pad layer adjacent to the first pad layer in the second horizontal direction and at a vertical level which is lower than the first pad layer; and
a third pad layer adjacent to the second pad layer in the second horizontal direction and at a vertical level which is lower than the second pad layer, and
the second pad layer has a third width in the second horizontal direction, and the third pad layer has a fourth width which is less than the third width in the second horizontal direction.
10. The semiconductor device of claim 9, wherein each of the plurality of ground selection line cut regions is in the second pad layer and each of the plurality of ground selection line cut regions does not to vertically overlap an edge of the second pad layer in a plan view, and the first pad layer does not vertically overlap each of the plurality of ground selection line cut regions. Claim 10 is objected to, due to its dependence upon claim 9.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Eduardo A Rodela whose telephone number is (571)272-8797. The examiner can normally be reached M-F, 8:30-5:00pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara B Green can be reached on (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EDUARDO A RODELA/Primary Examiner, Art Unit 2893
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