DETAILED ACTION
Claims 1-8, 10-15, 17-22 are pending.
Notice of Pre-AIA or AIA Status
This Office Action is sent in response to Applicant’s Communication received on 02/24/2026 for application number 18/336,541.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 11 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Lai et al. (US 2019/0204898 A1) in view of Jayasimha et al. (US 2013/0073878 A1).
Regarding claim 1, Lai teaches a device comprising:
a plurality of chiplets connected via a plurality of interconnects, and one or more of the plurality of chiplets having a cache (“an integrated circuit that includes a plurality of last-level caches, a plurality of processor cores, and an interconnect network… The interconnect network includes a plurality of point-to-point links… The plurality of point-to-point links … to receive access addresses from the plurality of processor cores and to couple… each of the plurality of processor cores to a respective one of the plurality of last-level caches.” Par 0003 and “In a multi-core processing chip, the last-level cache may be implemented by multiple last-level caches (a.k.a. cache slices) that are interconnected, but physically and logically distributed.” Par 0017 and paragraph 20 and Figure 1A); and
wherein both the active power state of the at least one of the plurality of interconnects and the shallow power state of the at least one of the plurality of interconnects allows probe traffic through the at least one of the plurality of interconnects to caches of chiplets connected to the at least one of the plurality of interconnects (“data access operations (e.g., load, stores) and cache operations (e.g., snoops, evictions, flushes, etc.), by a processor 111-114, L2 cache 121 -124, last-level cache 131-135, memory controller 141, and/or IO processor 142 may be exchanged with each other via interconnect links 150 a-150 j.” par 0026 and “The powering up and down of links 150 a-150 j can be done in a manner that is fully consistent with how we power down and wake up the cache slices—e.g., by at least changing the cache hashing function after draining queues and buffers associated with the cache slices 131-134 that are being put to sleep.” Par 0031) [the snoops (probes) are traffic carried by interconnects links that remain functional during both active operation and the draining (shallow) state to facilitate communication with the connected cache slices (chiplet caches)], and the deep power state of the at least one of the plurality of interconnects restricts the probe traffic through the at least one of the plurality of interconnects to the caches of the chiplets connected to the at least one of the plurality of interconnects (“The current cache hash function being used by system 100 may be changed … to reduce power consumption by turning off … one or more of last-level caches 131-134 and by turning off … the links 150 a-150 j that connect to the ‘off’ caches 131-134.” Par 0029 and “the second set of links not providing a path to distribute accesses [including snoops] by the first processor core to the second last-level cache.” Par 0073 and “not attempting to send data to the inactive last-level caches via inactive links.” Par 0018) [in the deep power state, the interconnects themselves are turned off, which restricts probe traffic (snoops) by not providing a functional path to distribute requests to the caches of the connected chiplets].
However, Lai does not explicitly teach a control circuit configured to: detect an activity state of each of the plurality of chiplets; and manage a power state of at least one of the plurality of interconnects by selecting, based on the detected activity states relating to the at least one of the plurality of interconnects, at least one of a deep power state, a shallow power state, or an active power state for the at least one of the plurality of interconnects.
In the analogous art, Jayasimha teaches a control circuit (interconnect power manager 506, Figure 5) configured to:
detect an activity state of each of the plurality of chiplets (“Additionally, the activity of each power domain can be monitored by the logic sending out the domain_active signal (see FIG. 4). This signal indicates if any transaction(s) in that power domain are active in that cycle.” Par 0050 and “ The components of the interconnect network itself and the initiator and target IP cores [chiplets] are distributed among three distinct power domains as shown in FIG. 2 and the table in FIG. 9.” Par 0032); and
manage a power state of at least one of the plurality of interconnects by selecting, based on the detected activity states relating to the at least one of the plurality of interconnects, at least one of a deep power state, a shallow power state, or an active power state for the at least one of the plurality of interconnects (“The interconnect-power-manager can be configured to control transaction activity management within the multiple power domains within the interconnect network by sending one or more signals to either quiesce [shallow power state] or awaken [active power state] the interconnect network components contained within these multiple power domains… The integrated-circuit-system-power-manager turns off power [deep power state] to a given power domain when all of the components within that given power domain in the integrated circuit are quiesced.” Par 0024 and “Additionally, the activity of each power domain can be monitored by the logic sending out the domain_active signal (see FIG. 4). This signal indicates if any transaction(s) in that power domain are active in that cycle. It is the responsibility of the integrated-circuit-system-power-manager to … interpret this cycle-by-cycle activity status and use this information to quiesce a power domain or to continue to keep it awakened.” Par 0050 and paragraphs 5, 95, 98, 108 and Figure 1, 4-7) [the integrated hardware monitored the cycle-by-cycle transaction status (via the domain_active signal) within power domains that contain the interconnect’s internal components, such as routers, arbitration units, etc., see paragraph 54].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Lai and Jayasimha before him before the effective filing date of the claimed invention, to have modified Lai to incorporate the teachings of Jayasimha to integrate separately controlled domains to tune each IP core to minimize energy consumption. This architecture also allows for flexible domain crossing choices and zero performance loss at a crossing. (Jayasimha, paragraph 153)
Regarding claim 11, Lai teaches a system (systems of Figures 1A-2C) comprising:
a physical memory (Figure 1A, memory 145); at least one physical processor (Figure 1A, CPU 111-114) comprising: a host die (Figure 1A, IO die 142 and paragraph 19).
The remainder of claim 11 corresponds to claim 1 and is rejected accordingly.
Regarding claim 18, Lai teaches a method comprising:
detecting a first activity state of a first chiplet of a plurality of chiplets and a second activity state of a second chiplet of the plurality of chiplets that communicates with the first chiplet, wherein the first chiplet has a first cache and the second chiplet has a second cache (“a first processor core [first chiplet] of the plurality of processor cores is more tightly coupled to the first last-level cache [first cache]” par 0060 and “a second processor core [second chiplet] of the plurality of processor cores being more tightly coupled to the second last-level cache [second cache]” par 0063 and “cache slices 131-134 can be dynamically powered down based on utilization [activity state] and power state,” par 0030);
wherein both the active power state of the interconnect and the shallow power state of the interconnect allows probe traffic through the interconnect to caches of chiplets connected to the interconnect (“data access operations (e.g., load, stores) and cache operations (e.g., snoops, evictions, flushes, etc.), by a processor 111-114, L2 cache 121 -124, last-level cache 131-135, memory controller 141, and/or IO processor 142 may be exchanged with each other via interconnect links 150 a-150 j.” par 0026 and “The powering up and down of links 150 a-150 j can be done in a manner that is fully consistent with how we power down and wake up the cache slices—e.g., by at least changing the cache hashing function after draining queues and buffers associated with the cache slices 131-134 that are being put to sleep.” Par 0031) [the snoops (probes) are traffic carried by interconnects links that remain functional during both active operation and the draining (shallow) state to facilitate communication with the connected cache slices (chiplet caches)], and the deep power state of the interconnect restricts the probe traffic through the interconnect to the caches of the chiplets connected to the interconnect (“The current cache hash function being used by system 100 may be changed … to reduce power consumption by turning off … one or more of last-level caches 131-134 and by turning off … the links 150 a-150 j that connect to the ‘off’ caches 131-134.” Par 0029 and “the second set of links not providing a path to distribute accesses [including snoops] by the first processor core to the second last-level cache.” Par 0073 and “not attempting to send data to the inactive last-level caches via inactive links.” Par 0018) [in the deep power state, the interconnects themselves are turned off, which restricts probe traffic (snoops) by not providing a functional path to distribute requests to the caches of the connected chiplets]; and
placing the interconnect into the selected power state (“the links connected to them may be turned off or placed in some other power saving mode.” Par 0037 and “To fully interconnect all of the ‘on’ last-level caches 131-134 and interface 126, all of links 150 a-150 j are active.” Par 0032).
However, Lai does not explicitly teach applying a power management policy that includes an idle power state, a shallow power state, and a deep power state using the detected first activity state and the detected second activity state to select a power state for an interconnect of a plurality of interconnects that corresponds to the first chiplet.
In the analogous art, Jayasimha teaches applying a power management policy that includes an idle power state, a shallow power state, and a deep power state using the detected first activity state and the detected second activity state to select a power state for an interconnect of a plurality of interconnects that corresponds to the first chiplet (“The integrated-circuit-system-power-manager may control power management within the interconnect network by monitoring only status registers located within each of the initiator agents. The status registers indicate a composite of the quiescent state for all interconnect network components including initiator agents, target agents, and routers in each power domain in the interconnect network that have connectivity to that initiator agent.” Par 0028 and “The interconnect-power-manager asserts the down_ok signal and the state machine enters the down state.” Par 0095 and “ responsibility of the integrated-circuit-system-power-manager to use the appropriate low pass filter mechanism to interpret this cycle-by-cycle activity status and use this information to quiesce a power domain or to continue to keep it awakened.” Par 0050 and paragraphs 90-95 and Figure 4) [this describes a power management policy where a state machine selects between active (awake), shallow (quiesce) and deep (down) power states for interconnect domains based on the monitored activity states of the target agents].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Lai and Jayasimha before him before the effective filing date of the claimed invention, to have modified Lai to incorporate the teachings of Jayasimha to integrate separately controlled domains to tune each IP core to minimize energy consumption. This architecture also allows for flexible domain crossing choices and zero performance loss at a crossing. (Jayasimha, paragraph 153)
Claims 2-8, 10, 12-15, 17, 19-22 are rejected under 35 U.S.C. 103 as being unpatentable over Lai and Jayasimha in view of Gough et al. (US 2018/0196488 A1).
Regarding claim 2, Lai and Jayasimha teach the device of claim 1. However, Lai and Jayasimha do not explicitly teach wherein the control circuit is configured to manage the power state of at least one of the plurality of interconnects by reducing a power state of an interconnect when a corresponding chiplet is idle.
In the analogous art, Gough teaches wherein the control circuit is configured to manage the power state of at least one of the plurality of interconnects by reducing a power state of an interconnect when a corresponding chiplet is idle (“A x8 PCIe device may be dynamically configured to only use 4 of the 8 lanes. Link reduction may be performed in order to save power.” Par 0021 and “Entry into the L1 state may be initiated by a downstream device (such as a PCIe device) when the downstream device has been idle for a prescribed amount of time.” Par 0024) [L1 state is a power-saving state; the downstream device, under BRI, may correspond to a chiplet].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Lai, Jayasimha and Gough before him before the effective filing date of the claimed invention, to have modified Lai and Jayasimha to incorporate the teachings of Gough to enable power savings on interconnects via dynamic link width without incurring performance latency of a full active power state. This allows probe traffic to continue during an intermediate power state while reducing power consumption. (Gough paragraph 21)
Regarding claim 3, Lai, Jayasimha and Gough teach the device of claim 2. Gough further teaches wherein the control circuit is configured to increase the power state of the interconnect when the corresponding chiplet becomes active (“In operation 301, the microcontroller 120 may perform exiting of the c-state (such as the package c-state). The microcontroller 120 may take actions associated with transitioning the processor (or platform) from the global idle condition (or state) to an active condition (or state) (waking up at least one of the cores, waking up platform interconnects… The waking up may refer to transitioning a resource from an idle condition to an active condition.” par 0084 and Figure 5) [the microcontroller (control circuit) wake up interconnects (increase power state) when corresponding processor transitions to active condition].
Regarding claim 4, Lai and Jayasimha teach the device of claim 1. However, Lai and Jayasimha do not explicitly teach wherein the control circuit is configured to manage the power state of at least one of the plurality of interconnects by placing an interconnect into the deep power state when a corresponding chiplet and one or more chiplets that communicate with the corresponding chiplet are idle.
In the analogous art, Gough further teaches wherein the control circuit is configured to manage the power state of at least one of the plurality of interconnects by placing an interconnect into the deep power state when a corresponding chiplet and one or more chiplets that communicate with the corresponding chiplet are idle (“The processor (or platform) may make determinations based on global idle conditions or other indicators of platform activity that exist on the processor and/or platform… For example, when a platform is able to enter a c-state (or platform c-state), transactions not being processed by the platform may all be in an inactive state (or inactive condition). ” Par 0029 and “Eventually, if all links from the upstream device enter the L1 state, then the microcontroller (or CPU) may take additional actions to save power (i.e., entering into a deeper c-state).” Par 0033) [the interconnects enter a deep power state when the corresponding chiplet and other communicating chiplet (global idle conditions) are idle].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Lai, Jayasimha and Gough before him before the effective filing date of the claimed invention, to have modified Lai and Jayasimha to incorporate the teachings of Gough to enable power savings on interconnects via dynamic link width without incurring performance latency of a full active power state. This allows probe traffic to continue during an intermediate power state while reducing power consumption. (Gough paragraph 21)
Regarding claim 5, Lai, Jayasimha and Gough teach the device of claim 4. Gough further teaches wherein the control circuit is configured to increase a power state of the interconnect from the deep power state when at least one of the one or more chiplets that communicate with the corresponding chiplet becomes active (“In operation 301, the microcontroller 120 may perform exiting of the c-state (such as the package c-state). The microcontroller 120 may take actions associated with transitioning the processor (or platform) from the global idle condition (or state) to an active condition (or state) (waking up at least one of the cores, waking up platform interconnects… The waking up may refer to transitioning a resource from an idle condition to an active condition.” par 0084 and Figure 5) [the microcontroller (control circuit) wake up interconnects (increase power state) from a deep power state (shown by transitioning from global idle condition which allows entry into a deeper c-state) when corresponding chiplet or communicating chiplets become active].
Regarding claim 6, Lai and Jayasimha teach the device of claim 1. However, Lai and Jayasimha do not explicitly teach wherein the control circuit is configured to manage the power state of at least one of the plurality of interconnects by placing a first interconnect into the shallow power state when a corresponding first chiplet is idle and a second chiplet that communicates with the corresponding first chiplet is active, and the control circuit is configured to place a second interconnect corresponding to the second chiplet into the active power state.
In the analogous art, Gough teaches wherein the control circuit is configured to manage the power state of at least one of the plurality of interconnects by placing a first interconnect into the shallow power state when a corresponding first chiplet is idle and a second chiplet that communicates with the corresponding first chiplet is active, and the control circuit is configured to place a second interconnect corresponding to the second chiplet into the active power state (“A x8 PCIe device may be dynamically configured to only use 4 of the 8 lanes. Link reduction may be performed in order to save power.” Par 0021 and “FIG. 1 also shows that the PCI link may be in an idle state (or idle condition) at different time points (such as time periods 22, 24 and 26) while the processor is in the active state (such as at the time period 21).” Par 0040 and “FIG. 2 shows that while the processor is active (such as during the time periods 21 and 41), the L1 state requests are denied and the respective PCIe link remains at the L0 state.” Par 0049) [the link reduction corresponds to the shallow power state; Figure 1 shows specific condition of an idle interconnect while its communicating processor is active (the PCI link corresponds to the first interconnect) being in an idle (shallow) power state when the corresponding chiplet (downstream device on link that initiates L1 entry due to idleness) is idle while second chiplet that communicates with the first (the processor) is active; Figure 2 shows when the processor (second chiplet) becomes active, the corresponding interconnect (respective PCIe link) is placed/kept in active state (L0) by denying request for deeper power state (L1)].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Lai, Jayasimha and Gough before him before the effective filing date of the claimed invention, to have modified Lai and Jayasimha to incorporate the teachings of Gough to enable power savings on interconnects via dynamic link width without incurring performance latency of a full active power state. This allows probe traffic to continue during an intermediate power state while reducing power consumption. (Gough paragraph 21)
Regarding claim 7, Lai and Jayasimha teach the device of claim 1. However, Lai and Jayasimha do not explicitly teach wherein the device further comprises a second plurality of chiplets connected via a second plurality of interconnects and the control circuit is further configured to manage power states of the second plurality of interconnects based on activity states of the second plurality of chiplets.
In the analogous art, Gough teaches wherein the device further comprises a second plurality of chiplets connected via a second plurality of interconnects and the control circuit is further configured to manage power states of the second plurality of interconnects based on activity states of the second plurality of chiplets (“The microcontroller may operate by monitoring the global idle conditions (or other indicators of platform activity) and negotiating c-states, such as with other processors as well as a platform controller hub (PCH) and/or chipset.” Par 0033 and [paragraphs 50-53 and Figure 3A]) [Figure 3A shows a system with multiple chiplets/devices with their respective sets of interconnects (130, 190 and 165 may correspond to three different sets of interconnects connecting processors and devices)] [the microcontroller (control circuit) managed power states of the interconnects based on activity states (global idle conditions) of the connected chiplets/devices].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Lai, Jayasimha and Gough before him before the effective filing date of the claimed invention, to have modified Lai and Jayasimha to incorporate the teachings of Gough to enable power savings on interconnects via dynamic link width without incurring performance latency of a full active power state. This allows probe traffic to continue during an intermediate power state while reducing power consumption. (Gough paragraph 21)
Regarding claim 8, Lai, Jayasimha and Gough teach the device of claim 7. Gough further teaches wherein the control circuit manages the power states of the second plurality of interconnects independently from activity states of the plurality of chiplets (“FIG. 1 also shows that the L1 state entry of the PCI link may be independent of the processor activity.” Par 0041 and Figure 3B) [each set of interconnects are managed independently].
Regarding claim 10, Lai and Jayasimha teach the device of claim 1. However, Lai and Jayasimha do not explicitly teach wherein the control circuit is configured to manage the power state of each of the plurality of interconnects based on a power management policy relating to activity states of corresponding chiplets.
In the analogous art, Gough teaches wherein the control circuit is configured to manage the power state of each of the plurality of interconnects based on a power management policy relating to activity states of corresponding chiplets (“Microcode (or CPU microcode) hardware, circuitry and/or logic may be provided within the platform (or processor) for coordinating when the L1 state can be used (or not used) based on global idle conditions or other indicators of platform activity (or processor activity).” Par 0033) [managing the power states of interconnected by coordinating their use is based on a power management policy, which is determined by the activity states (global idle conditions or other indicators) of the chiplets; the determination may correspond to a policy under BRI].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Lai, Jayasimha and Gough before him before the effective filing date of the claimed invention, to have modified Lai and Jayasimha to incorporate the teachings of Gough to enable power savings on interconnects via dynamic link width without incurring performance latency of a full active power state. This allows probe traffic to continue during an intermediate power state while reducing power consumption. (Gough paragraph 21)
Claim 12 corresponds to claims 2 and 3 and is rejected accordingly.
Claim 13 corresponds to claims 4 and 5 and is rejected accordingly.
Claims 14 and 19 corresponds to claim 6 and is rejected accordingly.
Claim 15 corresponds to claims 7 and 8 and is rejected accordingly.
Claim 17 corresponds to claim 10 and is rejected accordingly.
Regarding claim 20, Lai and Jayasimha teach the method of claim 18. However, Lai and Jayasimha does not explicitly teach wherein the power management policy includes selecting the deep power state when the first chiplet and one or more chiplets that communicate with the chiplet are idle.
In the analogous art, Gough teaches wherein the power management policy includes selecting a deep power state when the first chiplet and one or more chiplets that communicate with the chiplet are idle (“Microcode (or CPU microcode) hardware, circuitry and/or logic may be provided within the platform (or processor) for coordinating when the L1 state can be used (or not used) based on global idle conditions or other indicators of platform activity (or processor activity)… Eventually, if all links from the upstream device enter the L1 state, then the microcontroller (or CPU) may take additional actions to save power (i.e., entering into a deeper c-state).” Par 0033 and “The L1 state may be activated on the PCIe link when there are no outstanding requests or pending transactions.” Par 0023) [the power management policy (coordinating L1 state use based on global idle conditions) leads to entering a deep power state when the chiplet and communicating chiplets are idle; the L1 state corresponds to an “off”/deep power state].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Lai, Jayasimha and Gough before him before the effective filing date of the claimed invention, to have modified Lai and Jayasimha to incorporate the teachings of Gough to enable power savings on interconnects via dynamic link width without incurring performance latency of a full active power state. This allows probe traffic to continue during an intermediate power state while reducing power consumption. (Gough paragraph 21)
Regarding claim 21, Lai and Jayasimha teach the device of claim 1. However, Lai and Jayasimha do not explicitly teach wherein managing the power state of the at least one of the plurality of interconnects includes asymmetrically selecting power states for interconnects with respect to activity states of corresponding chiplets.
In the analogous art, Gough teaches wherein managing the power state of the at least one of the plurality of interconnects includes asymmetrically selecting power states for interconnects with respect to activity states of corresponding chiplets (“FIG. 1 also shows that the PCI link may be in an idle state (or idle condition) at different time points (such as time periods 22, 24 and 26) while the processor is in the active state (such as at the time period 21).” Par 0040) [the PCI link (interconnect) enters an idle state (reduce power sate) even while the processor (corresponding chiplet) is active; this shows a non-uniform (asymmetrical) power management where interconnect’s state is distinct from, but still responsive to, the activity of its connected component].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Lai, Jayasimha and Gough before him before the effective filing date of the claimed invention, to have modified Lai and Jayasimha to incorporate the teachings of Gough to enable power savings on interconnects via dynamic link width without incurring performance latency of a full active power state. This allows probe traffic to continue during an intermediate power state while reducing power consumption. (Gough paragraph 21)
Claim 22 repeats the same limitations as claim 21 and is rejected accordingly.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 11 and 18 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
No additional arguments were presented as to the remaining claims. As such, the rejection is maintained.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AYMAN FATIMA whose telephone number is (571)270-0830. The examiner can normally be reached M to Fri between 8am and 4pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached on (571)270-1640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/AYMAN FATIMA/Examiner, Art Unit 2176
/JAWEED A ABBASZADEH/Supervisory Patent Examiner, Art Unit 2176
Prosecution Insights