CTNF 18/336,656 CTNF 71715 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-20 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by J. Zhang et al. [“Protected Quantum Computing: Interleaving Gate Operations with Dynamical Decoupling Sequences”] . Taking claim 1 as exemplary of claims 1 and 16 [a system is inherent to experimentally demonstrate or implement the following], a method for generating a control sequence for implementing a unitary operation and dynamically decoupling a qubit [Abstract general scheme], the method comprising: obtaining data specifying a target unitary operation [page 2, left column target operation is a unitary gate] and data specifying a dynamical decoupling control sequence [page 2, left column the DD sequence, as a specific example XY – 4 and XY – 8 were chosen]; modifying single qubit gates [page 1, left column DD does not require additional qubits] included in the dynamical decoupling control sequence to generate an adjusted dynamical decoupling control sequence that [page 1, left column DD relies on a sequence of control operations, DD sequences can be designed], when applied to a qubit, dynamically decouples the qubit and implements the target unitary operation [page 1, right column modify general logic gate operations in such a way, for any gate operation at least to first order, with any type of quantum gate operation], wherein modifying the single qubit gates comprises: factoring the target unitary operation as a product of multiple sub-unitary operations [page 2 equations (2), (3), and (5), right column split them up into segments]; interleaving, using commutation relations of the sub-unitary operations and the single qubit gates included in the dynamical decoupling control sequence, one or more of the sub-unitary operations through the dynamical decoupling control sequence [page 1, right column modify general logic gate operations in such a way that they can be interleaved with the DD sequences, page 2, left column first order protection of any operation interlaced with a suitable DD sequence, right column that can be interleaved with the DD sequences]; and adjusting one or more single qubit gates included in the dynamical decoupling control sequence to include the interleaved sub-unitary operations [page 2, right column, FIG. 2 shows the resulting sequence, combining the gate operation and the DD cycle, page 4, right column interleaving process requires that segments of the gate operations be modified in such a way that the DD pulses effectively transform them into operations required by the algorithm]; and providing the adjusted dynamical decoupling control sequence for application to one or more qubits in a quantum computer [page 4, right column (ii) implementing quantum computing, many quantum algorithms require the application of single-qubit gate operations, demonstrated that protected gates retain high fidelity]. 2. The method of claim 1, wherein interleaving one or more of the sub-unity operations through the dynamical decoupling control sequence comprises evenly distributing the one or more sub-unitary operations throughout the dynamical decoupling control sequence [FIGS. 1 and 2 depict even distribution]. 3. The method of claim 1, wherein the dynamical decoupling control sequence comprises a first number n of single qubit gates and the multiple sub-unitary operations comprises n unitary operations [n is 4 for XY – 4, n is 8 for XY – 8, equations (2) and(3) represent the unitary gate of the target operation in increments/segments for the Hamiltonian]. 4. The method of claim 3, wherein the target unitary operation comprises a target phase gate that implements a single qubit rotation a and each sub-unitary operation of the multiple sub-unitary operations implements a single qubit rotation a/n [page 2, left column equation (3) the required control Hamiltonian, this approach guarantees first order protection of any operation interlaced with a suitable DD sequence]. 5. The method of claim 4, wherein adjusting one or more single qubit gates included in the dynamical decoupling control sequence to include the interleaved sub-unitary operations comprises adjusting phases of the one or more single qubit gates to include respective phases of the interleaved sub-unitary operations [page 2, right column transformation changes the phases]. 6. The method of claim 4, wherein the single qubit rotation comprises a single qubit rotation about the Z axis [FIG. 1 rotation axes x and y are about the z axis, as indicated by FIG. 3]. 7. The method of claim 1, wherein adjusting one or more single qubit gates included in the dynamical decoupling control sequence to include the interleaved sub-unitary operations comprises adjusting a proper subset of the single qubit gates included in the dynamical decoupling control sequence to include the interleaved sub-unitary operations [page 1, left column DD sequences can be designed, page 1, right column modify general logic gate operations in such a way, for any gate operation at least to first order, with any type of quantum gate operation, page 4, right column interleaving process requires that segments of the gate operations be modified in such a way that the DD pulses effectively transform them into operations required by the algorithm]. 8. The method of claim 7, wherein the proper subset comprises single qubit gates of a same type [Abstract nitrogen]. 9. The method of claim 1, wherein the target unitary operation comprises a coherent single qubit gate [page 1, left column DD does not require additional qubits]. 10. The method of claim 1, wherein application of the dynamical decoupling control sequence to a qubit is equivalent to an application of an identity operation to the qubit [page 2, right column no operation, i.e. identity]. 11. The method of claim 1, wherein the dynamical decoupling control sequence comprises X gates and Y gates [page 2, left column we choose the XY – 4 and XY – 8]. 12. The method of claim 1, wherein the dynamical decoupling control sequence comprises an n Pi pulse dynamical decoupling scheme, a 2n Pi pulse dynamical decoupling scheme, or a 2n + 1 Pi pulse dynamical decoupling scheme [page 4, right column the DD pulses effectively transform them into operations required by the algorithm, FIG. 1, equation (5), FIG. 2]. 13. The method of claim 1, wherein providing the adjusted dynamical decoupling control sequence for application to one or more qubits in a quantum computer comprises, during execution of a quantum computation by the quantum computer: determining that one or more qubits require dynamical decoupling and application of the target unitary operation [page 4, right column for protecting quantum logical gate operations against environmental noise]; and in response to determining that the one or more qubits require dynamical decoupling and application of the target unitary operation, generating a control signal to apply the adjusted dynamical decoupling control sequence to the one or more qubits [page 4, right column we have implemented a scheme, by segmenting the gate operations and interleaving them with a pulse cycle for DD, the DD pulses effectively transform them into operations required by the algorithm]. 14. The method of claim 13, further comprising applying the generated control signal to the one or more qubits [Abstract Implementing precise operations on quantum systems, page 1, left column relies on a sequence of control operations applied to the system]. 15. The method of claim 1, wherein providing the adjusted dynamical decoupling control sequence for application to one or more qubits in a quantum computer comprises storing the adjusted dynamical decoupling control sequence in a control electronics memory of the quantum computer [storing is inherent to the process]. Taking claim 17 as exemplary of claims 17 and 20 [a system is inherent to experimentally demonstrate or implement the following], a method for dynamically decoupling [Abstract dynamical decoupling, DD throughout] and performing a target unitary operation to a qubit [page 2, left column target operation is a unitary gate], the method comprising: generating a control signal that implements a dynamical decoupling control sequence [Abstract, general scheme, page 1, left column DD relies on a sequence of control operations]; and applying the control signal to the qubit to dynamically decouple the qubit and perform the target unitary operation on the qubit [Abstract general scheme for combining DD with quantum logical gate operations, page 4, right column (ii) implementing quantum computing, many quantum algorithms require the application of single-qubit gate operations, demonstrated that protected gates retain high fidelity], wherein: the target unitary operation comprises a product of multiple sub-unitary operations [page 2 equations (2), (3), and (5), right column split them up into segments]; and the dynamical decoupling control sequence comprises a plurality of single qubit gates [page 1, left column DD does not require additional qubits, right column modify general logic gate operations in such a way, for any gate operation at least to first order, with any type of quantum gate operation, page 4, right column single-qubit gates], wherein one or more of the single qubit gates comprise a single qubit gate that implements one or more of sub-unitary operations of the multiple sub-unitary operations [page 1, right column DD sequences can be designed, modify general logic gate operations in such a way, for any gate operation at least to first order, with any type of quantum gate operation, page 2, left column as a specific example XY – 4 and XY – 8 were chosen, page 4, right column interleaving process requires that segments of the gate operations be modified in such a way that the DD pulses effectively transform them into operations required by the algorithm]. 18. The method of claim 17, wherein: the target unitary operation comprises a target rotation operation [FIG. 1 indicates rotation axes]; and each single qubit gate that implements one or more of sub-unitary operations of the multiple sub-unitary operations comprises a single qubit gate with an initial phase or initial pulse amplitude that is modified using a phase or pulse amplitude of the one or more of sub-unitary operations [page 2, right column, Fig. 2 shows the resulting sequence, page 3, left column For the experimental test… our method of interleaving gate operations with DD sequences works and avoids destructive interference]. 19. The method of claim 17, wherein the initial phase or initial pulse amplitude comprise a phase or pulse amplitude specified by an initial dynamical decoupling control sequence [page 3, left column initializes the state |0>, prepare states as input states, page 4, right column the DD pulses effectively transform them into operations required by the algorithm], optionally wherein the initial dynamical decoupling control sequence comprises an n Pi pulse dynamical decoupling scheme, a 2n Pi pulse dynamical decoupling scheme, or a 2n + 1 Pi pulse dynamical decoupling scheme [optionally FIG. 1, equation (5), FIG. 2] . 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. H. K. Ng et al. [“Combining dynamical decoupling with fault-tolerant quantum computation”] disclose concatenated pulse sequences (entire document). B. Li et al. disclose “Designing arbitrary single-axis rotations robust against perpendicular time-dependent noise” (entire document). F. Wang et al. ["Experimental realization of robust dynamical decoupling with bounded controls in a solid-state spin system"] disclose long soft pulses (entire document). P. Goiporia et al. disclose “Suppressing errors with dynamical decoupling using pulse control on Amazon Braket” (entire document). Laurer et al. [US 2021/0258079 A1] disclose target qubit decoupling (entire document). KIM et al. [US 2019/0020345 A1] disclose shifting phase (entire document). Patomaki et al. [US 2023/0153673 A1] disclose controlling one qubit (Abstract, FIG. 9] . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to LEIGH M GARBOWSKI whose telephone number is (571)272-1893. The examiner can normally be reached M-F 9-5 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /LEIGH M GARBOWSKI/ Primary Examiner, Art Unit 2851 Application/Control Number: 18/336,656 Page 2 Art Unit: 2851 Application/Control Number: 18/336,656 Page 3 Art Unit: 2851 Application/Control Number: 18/336,656 Page 4 Art Unit: 2851 Application/Control Number: 18/336,656 Page 5 Art Unit: 2851 Application/Control Number: 18/336,656 Page 6 Art Unit: 2851 Application/Control Number: 18/336,656 Page 7 Art Unit: 2851 Application/Control Number: 18/336,656 Page 8 Art Unit: 2851
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