Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 6/2/2026 has been entered.
Acknowledgment of Amendment
Acknowledgment is made of applicant's amendment, filed on 10 Dec 2014. The changes and remarks disclosed therein have been considered. Claim 4 has been cancelled by the amendment. Claims 1, 11, 17 have been amended. New Claim 21 has been added. Therefore, claims 1-3, 5-21 remain pending in the application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu PG PUB 20230306181 (hereinafter Liu), in view of BISWAS PG PUB 20200074042 (hereinafter BISWAS).
Regarding independent claim 1, Liu teaches a device (figure 14), comprising:
memory (520 plus circuit responsible for store program instruction in 510 in figure 14) that is configured to store program instructions; and
processing circuitry (circuit responsible for execute program instruction 510 in figure 14), coupled to the memory, and configured to execute the program instructions to perform a process to limit current leakage, wherein in performing the process, the processing circuitry is configured to:
receive an input of an initial layout (LO1 in figure 14 and [0108], “…In response to the expected boundary leakages exceeds a tolerance range, the processor 510 will adjust the initial layout LO1 (e.g., re-arrange the abutments or locations of cells in the layout) into an adjusted layout LO2, in order to reduce the boundary leakages…”) of a semiconductor structure comprising a plurality of cells (CL1/CL2/CL3 in figure 1);
identify (S210 in figure 2, S410 in figure 13) a plurality of edge source/drain regions (“EGma” or “EGmb” indicated in [0039], “…the cell edge EGma is utilized as a source terminal (S) in the cell CLm; the cell edge EGmb is utilized as a drain terminal (D) in the cell CLm; the cell edge EGmc is utilized as a drain terminal (D) in the cell CLm; and the cell edge EGmd is utilized as a source terminal (S) in the cell CLm …”) in respective ones of the plurality of cells;
determine respective electrical configurations (“cell edges”, “filler depth” indicated in [0046], “…operation S230, the method 200 is utilized to identify cell abutment cases corresponding to each of the boundaries based on the attributes associated with the cell edges of the abutted cells… the cell edges of the abutted cells can be different terminal types and/or have different filler depths, such that there are various combinations of cell abutment cases related to different cell edges of the abutted cells…”) for the plurality of edge source/drain regions;
compute respective values (S240 in figures 2/6, S440 in figure 13) associated with current leakage for adjacent cells of the plurality of cells in the initial layout (LO1 in figure 14) and in a plurality of alternative layouts (LO2 in [0108], “…In response to the expected boundary leakages exceeds a tolerance range, the processor 510 will adjust the initial layout LO1 (e.g., re-arrange the abutments or locations of cells in the layout) into an adjusted layout LO2, in order to reduce the boundary leakages…”) of the semiconductor structure based at least in part on the respective electrical configurations for the plurality of edge source/drain regions; and
identify at least one alternative layout of the plurality of alternative layouts to the initial layout by computing one or more cost functions ([0071], “…the method is performed to calculate expected boundary leakages between the abutted cells according to a sum of products between the leakage current values and the leakage probabilities…”, the term “cost function” describes a result of computation (leakage value). Under BRI, a “cost function” broadly reads on any computed value used for evaluation/optimization. Liu’s “expected boundary leakage” is functionally equivalent to applicant’s “cost function”) and determining the at least one alternative layout based on the computed one or more cost functions (Liu teaches modifying layout based on leakage evaluation, [0075], “…an optimization tool can avoid cell abutment with more leakage probability and displace cell abutment to other location for reducing the expected boundary leakages…”, [0106], “…operation S460 is executed to adjust the layout of the semiconductor device 100 based on at least the expected boundary leakages…”), wherein the at least one alternative layout results in at least a reduction of total current leakage from the initial layout ([0075], “…an optimization tool can … reducing the expected boundary leakages...”, [0108], “…In response to the expected boundary leakages exceeds a tolerance range, the processor 510 will adjust the initial layout LO1 (e.g., re-arrange the abutments or locations of cells in the layout) into an adjusted layout LO2, in order to reduce the boundary leakages…”)
But Liu does not teach wherein the identifying of the at least one alternative layout further comprises generating a data structure abstracting the electrical configurations of the respective edge source/drain regions of a plurality of pairs of the adjacent cells, wherein the data structure generating further comprises assigning attribute symbols respectively representing different types of edge source/drain regions for the plurality of pairs of the adjacent cells and assigning cost function values respectively corresponding to the plurality of pairs of the adjacent cells, wherein the assigned attribute symbols and the cost function values provide a simplified representation of the plurality of alternative
layouts from which the at least one alternative layout is identified.
Biswas teaches abstracting transistor-level edge relationship into symbolic quadrant-edge pair (QEP) representations used for layout optimization (figure 3C-3X, Table 1, [0043]-[0056]). These symbolic QWP representations constitute a data structure that abstracts the underlying electrical configurations of adjacent cell edges.
Biswas assigns symbolic QEP types (e.g., S/D/D, S/D/FC, S/S, etc) representing different electrical edge relationships (table 1, [0040]-[0048]). Biswas assign predetermined leakage values to each symbolic QEP type (Table 1, [0129]-[0132]), which are subsequently multiplied and summed to determine figure of merit (FOMs). These predetermined leakage values correspond to the claimed cost function values.
Biswas further teaches using the symbolic QEP classifications together with their assigned leakage values/FOMs to efficiently evaluate multiple candidate layouts and select layouts having reduced aggregate leakage (figure 6B, 6C, 6D, [0121]-[0138]). Accordingly, Biswas teaches a simplified symbolic representation used to compare alternative layout.
It would have been obvious to one of ordinary skill in the art at the time of effective filing to modify the leakage-analysis and layout optimization process of Liu with the symbolic abstraction technique of Biswas because Biswas teaches representing detailed electrical edge configurations using symbolic data structures having assigned leakage values, thereby reducing computational complexity and improving the efficiency of evaluating multiple candidate layouts while achieving the same objective of reducing leakage. Applying Biswas’s symbolic representation within Liu’s leakage-analysis framework would have predictably simplified layout evaluation without changing Liu’s underlying leakage calculation.
Regarding claim 2, the combination of Liu and Biswas teaches the device of claim 1, wherein the respective electrical configurations for the plurality of edge source/drain regions comprise at least one of a power connection (power for boundary gates TG1p of Liu, TG1n indicated in [0034] of Liu), a signal connection and a floating configuration ([0035]/[0036] of Liu, “…the above cell abutment cases include determinations of whether the boundary between abutted cells is a source-source boundary, a source-drain boundary, or a drain-drain boundary, different depths of filler cells, different voltage thresholds… For example, between the different abutment conditions, a Source-to-Drain (S-D) abutment generally experiences more boundary leakage than a Source-to-Source (S-S) abutment. [0036] Because these different attributes of the transistors, the cell edges, the cell abutment cases (e.g., abutment type, voltage thresholds, MOS type, or the like) contribute to differences in the amount of leakage at different boundaries between adjacent cells…”)
Regarding claim 3, the combination of Liu and Biswas teaches the device of claim 1, wherein, in computing the respective values associated with the current leakage for the adjacent cells, the processing circuitry is configured to identify electrical configurations of respective edge source/drain regions of the plurality of pairs of the adjacent cells (S430 in figure 13 of Liu), wherein the respective values associated with current leakage for the adjacent cells are computed based on the electrical configurations of the respective edge source/drain regions of the plurality of pairs of the adjacent cells (figure 13 of Liu).
Regarding claim 5, the combination of Liu and Biswas teaches the device of claim 3, wherein the respective values associated with the current leakage for the adjacent cells vary based on a type and a combination of the electrical configurations of the respective edge source/drain regions of the plurality of pairs of the adjacent cells ([0035]/[0036] of Liu, “…the above cell abutment cases include determinations of whether the boundary between abutted cells is a source-source boundary, a source-drain boundary, or a drain-drain boundary, different depths of filler cells, different voltage thresholds… For example, between the different abutment conditions, a Source-to-Drain (S-D) abutment generally experiences more boundary leakage than a Source-to-Source (S-S) abutment. [0036] Because these different attributes of the transistors, the cell edges, the cell abutment cases (e.g., abutment type, voltage thresholds, MOS type, or the like) contribute to differences in the amount of leakage at different boundaries between adjacent cells…”)
Regarding claim 6, the combination of Liu and Biswas teaches the device of claim 3, wherein, in computing the respective values associated with the current leakage for the adjacent cells, the processing circuitry is configured to identify a plurality of gate tie-down structures (“boundary gate” indicated in [0032] of Liu, “…a boundary gate TG1p is implemented at the boundary BD1 between P-channel portions CL1p and CL2p of the cells CL1 and CL2, and the boundary gate TG1p is electrically coupled to a system voltage rail RVDD. The system voltage rail RVDD is configured to provide a high system voltage VDD to the boundary gate TG1p. The boundary gate TG1p coupled with the high system voltage VDD is configured to limit (or block) a leakage current between the P-channel portion CL1p of the cell CL1 and the P-channel portion CL2p of the cell CL2. Another boundary gate TG1n is implemented at the boundary BD1 between N-channel portions CL1n and CL2n, and the boundary gate TG1n is electrically coupled to another system voltage rail RVSS. The system voltage rail RVSS is configured to provide a low system voltage VSS to the boundary gate TG1n. The boundary gate TG1n coupled with the low system voltage VSS is configured to limit (or block) a leakage current between the N-channel portion CL1n of the cell CL1 and the N-channel portion CL2n of the cell CL2. Effectively, the boundary gates TG1p and TG1n are configured to isolate the cells CL1 and CL2…”) in the initial layout and in the plurality of alternative layouts, and wherein the plurality of edge source/drain regions correspond to at least a subset of the plurality of gate tie-down structures.
Regarding claim 7, the combination of Liu and Biswas teaches the device of claim 1, wherein, in identifying the at least one alternative layout of the plurality of alternative layouts to the initial layout, the processing circuitry is configured to further base the identification of the at least one alternative layout on one or more parameters in addition to the reduction of the total current leakage (S460 in figure 13, Biswas teaches optimizing layouts using figures of merit (FOM) that evaluate aggregate leakage and selecting layouts by changing orientation or cell placement (figure 6B-6D, [0121]-[0143]). The layout selection therefore considers optimization parameters beyond merely the calculated leakage values itself).
Regarding claim 8, the combination of Liu and Biswas teaches the device of claim 7, wherein the one or more parameters comprise at least one of wire length, frequency and area of one or more devices in the semiconductor structure (figure 12 of Liu and [0035] of Liu teaches leakage current can be affected by voltage thresholds, threshold of transistors is related to wire length of gate, Biswas teaches that changing orientation may shorten routing length and improve propagation delay, electromigration, capacitance and related layout characteristics ([0110]-[0113]. These are recognized layout optimization parameters closely related to wire length and circuit area).
Regarding claim 9, the combination of Liu and Biswas teaches the device of claim 1, wherein the processing circuitry is further configured to compute a total current leakage of the at least one alternative layout (“expected boundary leakage” in S440 in figure 130 of Liu), wherein the computing of the total current leakage of the at least one alternative layout comprises: identifying a plurality of gate tie-down structures (“TG1p, TG1n, TG2p and TG2n” in [0034] of Liu) in the at least one alternative layout; identifying respective ones of the plurality of edge source/drain regions corresponding to at least a subset of the plurality of gate tie-down structures (S410/S420 in figure 13 of Liu); identifying electrical configurations of the respective ones of the plurality of edge source/drain regions of a plurality of pairs of adjacent cells in the at least one alternative layout (S430 in figure 13 of Liu); computing leakage values for the respective ones of the plurality of pairs of the adjacent cells in the at least one alternative layout based at least in part on the electrical configurations of the respective ones of the plurality of edge source/drain regions (S440 in figure 13 of Liu); and adding the leakage values for the respective ones of the plurality of pairs of the adjacent cells in the at least one alternative layout (S450/S460 in figure 13 of Liu).
Regarding claim 10, the combination of Liu and Biswas teaches the device of claim 1, wherein the processing circuitry is configured to apply the at least one alternative layout to a semiconductor manufacturing system adapted to fabricate the semiconductor structure based at least in part on the at least one alternative layout ([0106] of Liu, “…After the expected boundary leakages (and/or the maximal/minimal boundary leakages) of the semiconductor device 100 are calculated, operation S460 is executed to adjust the layout of the semiconductor device 100 based on at least the expected boundary leakages…”, Biswas teaches generating the revised layout for fabrication, including fabrication masks, photolithographic exposure, semiconductor manufacturing, see figure 5, 7, 8 of Biswas, it would have been obvious to fabricate the optimized layout generated by Liu using Biswas’ manufacturing flow).
Claims 11-20 largely mirror claims 1-10 but are defined as system and computer program product claims.
Claim 11 recites the system counterpart of claim 1.
Liu teaches a processor configured to detect abutted cell boundaries, identify cell edge attributes, identify cell abutment conditions, calculate expected boundary leakages using leakage current values and leakage probabilities, and adjust the semiconductor layout based on the expected boundary leakages (figure 13-14, [0106]-[0108]).
Liu further teaches a processor and library (LUT1A/LUT1B, LUT2) for performing the claimed leakage analysis.
Liu, however, does not teach:
Generating a data structure abstracting the electrical configurations by assigning attribute symbols and assigning cost function values providing a simplified representation of alternative layouts.
Biswas teaches representing adjacent cell relationship using predetermined leakage values/FOM representations that abstract the electrical characteristics of adjacent cells for layout optimization (Table 1, figure 3C-3Y, figure 6B, [0042]-[0056], [0121]-[0132]).
It would have been obvious to incorporate Biswas’s abstract representation into Liu’s leakage analysis framework to simplify and improve computational efficiency during layout optimization.
Therefore, claim 11 is unpatentable over Liu in view of Biswas.
Regarding Claim 12, Liu teaches electrical configurations including: power rails (RVDD/RVSS), source/drain terminals, filler cells, filler breaks, which correspond to power connections, signal connections, and floating configurations (figure 1, [0029]-[0053]).
Regarding claim 13, claim 13 corresponds to claim 3.
Liu teaches identifying electrical configurations of adjacent cell edges, identifying cell abutment conditions, commutating leakage values based on those configurations (figure 13, figure 9, [0038]-[0053]).
Regarding claim 14, claim 14 corresponds to claim 6.
Liu teaches identifying boundary gates TG1/TG2 positioned along the boundary and electrically coupled to supply rails, corresponding to gate tie-down structures associated with the edge source/drain regions (figure 1, [0032]-[0034]).
Regarding claim 15, claim 15 corresponds to claim 9.
Liu teaches identifying gate tie-down structures, identifying edge source/drain regions, identifying electrical configurations, computing leakage values, summing leakage values to obtain expected leakage (figure 13-14, [0105]-[0108]).
Regarding claim 16, claim 16 recites fabrication using the optimized layout.
Biswas teaches generating layout, fabricating semiconductor masks, photolithographic exposure, semiconductor fabrication (figure 5, 7,8, [0114]-[0163]).
It would have been obvious to fabricate the optimized layout generated by Liu using Biswas’s manufacturing flow.
Regarding independent claim 17, claim 17 is the computer-program-product counterpart of claim 1.
For the same reason discussed for claim 11, Liu teaches all limitations except the abstract data structure employing assigned attribute symbols and cost function values.
Biswas teaches the abstract leakage representations (predetermined leakage values/FOM representations) used to simplify layout optimization.
It would have been obvious to incorporate Biswas’ abstraction into Liu’s software implementation.
Regarding claim 18, claim 18 corresponds to claim 2, therefore, is rejected by same reasons for claim 2.
Regarding claim 19, claim 19 corresponds to claim 3, therefore, is rejected by same reasons for claim 3.
Regarding claim 20, claim 20 corresponds to claim 6, therefore, is rejected by same reasons for claim 6.
Regarding claim 21, the combination of Liu and Biswas teaches the computer program product of claim 17, further comprising program instructions to cause a semiconductor manufacturing system to fabricate the semiconductor structure based at least in part on the at least one alternative layout (Liu teaches a computer program product having program instructions configured to perform leakage analysis, calculate expected boundary leakage, generate or adjust a semiconductor layout, and output the adjusted layout (figure 13, 14, [0106]-[0108]), Liu, however, does not teach that computer program product further comprise program instructions to cause a semiconductor manufacturing system to fabricate the semiconductor structure based at least in part on the identified alternative layout. Biswas teaches the missing limitation, Biswas teach that, after generating an optimized layout diagram, the layout is used to fabricate semiconductor devices. Specifically, Biswas teaches generating the layout diagram and then, based on the layout diagram, performing one or more photolithographic exposures, fabricating one or more masks, or fabricating one or more components in a semiconductor integrated circuit (figure 5, 8, [0114]-[0117], [0156]-[0163]). Biswas further teaches an integrated manufacturing flow including design house, mask house, fabrication facility, and IC device fabrication using the generated layout (figure 8). It would have been obvious to modify Liu’s computer program product to further include instructions for causing a semiconductor manufacturing system to fabricate the semiconductor structure based on the identified alternative layout, as taught by Biswas, because integrating layout optimization with downstream semiconductor manufacturing provides an end-to-end EDA workflow that automatically implements the optimized layout in fabrication, thereby reducing manufacturing errors and improving design efficiency).
Response To Arguments
In regard to amendment of the independent claims 1, 11, and 17, applicant arguments have been fully considered but they are not persuasive. Applicant has amended the independent claims with additional limitation(s): " wherein the identifying of the at least one alternative layout further comprises generating a data structure abstracting the electrical configurations of the respective edge source/drain regions of a plurality of pairs of the adjacent cells, wherein the data structure generating further comprises assigning attribute symbols respectively representing different types of edge source/drain regions for the plurality of pairs of the adjacent cells and assigning cost function values respectively corresponding to the plurality of pairs of the adjacent cells, wherein the assigned attribute symbols
and the cost function values provide a simplified representation of the plurality of alternative layouts from which the at least one alternative layout is identified." The Applicant argues that the prior arts of record do not specifically teach this limitation. However, the independent claims 1, 11, 17 are now rejected as being unpatentable over Liu in view of Biswas. The Examiner respectfully submits that Liu teaches all features recited in the independent claim 1, except the newly added limitation. However, Biswas teaches abstracting transistor-level edge relationship into symbolic quadrant-edge pair (QEP) representations used for layout optimization (figure 3C-3X, Table 1, [0043]-[0056]). These symbolic QWP representations constitute a data structure that abstracts the underlying electrical configurations of adjacent cell edges. The claims do not recite any particular implementation of the recited “data structure”. Under BRI, any stored symbolic representation used to abstract electrical configurations for evaluating candidate layouts satisfies the claimed data structure. Biswas assigns symbolic QEP types (e.g., S/D/D, S/D/FC, S/S, etc) representing different electrical edge relationships (table 1, [0040]-[0048]). Biswas assign predetermined leakage values to each symbolic QEP type (Table 1, [0129]-[0132]), which are subsequently multiplied and summed to determine figure of merit (FOMs). These predetermined leakage values correspond to the claimed cost function values. Biswas further teaches using the symbolic QEP classifications together with their assigned leakage values/FOMs to efficiently evaluate multiple candidate layouts and select layouts having reduced aggregate leakage (figure 6B, 6C, 6D, [0121]-[0138]). Accordingly, Biswas teaches a simplified symbolic representation used to compare alternative layout.
The Examiner respectfully submits that Liu in view of Biswas teach all limitations recited in claim 1 including the newly added limitation.
Accordingly, the Examiner maintains the position previously set forth.
Conclusion
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/XIAOCHUN L CHEN/Examiner, Art Unit 2824
program product of claim 17, further comprising program
instructions to cause a semiconductor manufacturing system to fabricate the
structure based at least in part on the at least one alternative layout.
Prosecution Insights