Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment of Amendment
Acknowledgment is made of applicant's amendment, filed on 2/23/2026. The changes and remarks disclosed therein have been considered. Claims 1, 11, 17 have been amended. Therefore, claims 1-20 remain pending in the application.
Response To Arguments
The Applicant' arguments (REMARKS, filed 02/23/2026) have been fully considered.
Applicant argues: “unless a reference discloses … all of the limitations arranged or combined in the same way… it cannot anticipate...”
Applicant’s statement regarding anticipation is acknowledged; however, the present rejection is based on obviousness under 35 U.S.C. 103.
Specifically, Liu teaches a single integrated method including:
Detecting boundaries between adjacent cells ([0037]);
Identifying edge attributes including source/drain ([0038]-[0040], S/D/FC/FB);
Determining abutment configurations (S-S, S-D, etc);
Calculating leakage based on such configuration (figure 13, S440).
In regard to amendment of the independent claims 1, 11, and 17. Applicant arguments have been fully considered but they are not persuasive. Applicant has amended the independent claims with additional limitation(s): "identify at least one alternative layout of the plurality of alternative layouts to the initial layout by computing one or more cost functions and determining the at least one alternative layout based on the computed one or more cost functions," The Applicant argues that the prior arts of record do not specifically teach this limitation.
Applicant argument Is not persuasive because the alleged “cost function” is merely a mathematical representation of leakage values, leakage values is explicitly taught by Liu.
Liu teaches:
leakage current values via lookup table LUT1 ([0058]-[0060], figure 10A/10B);
leakage probabilities (LUT2) ([0063], figure 11);
expected leakage values combining both ([0071], [0098], figure 9)
These are numerical values assigned based on edge S/D configurations, functionally equivalent to applicant “cost function”.
The term “cost function” is a label, describing a result of computation (leakage value). Under BRI, a “cost function” broadly reads on any computed value used for evaluation/optimization. Liu’s “expected boundary leakage” is functionally equivalent to applicant’s “cost function”.
Liu explicitly uses leakage values for layout optimization. Liu teaches in figure 13, S460 “adjust the layout…based on expected boundary leakages” ([0106], “…operation S460 is executed to adjust the layout of the semiconductor device 100 based on at least the expected boundary leakages…”)
Applicant’s numeric example (0, 0.5, 1) do not distinguish. Applicant argues: “cost function can be 0, 0.5, 1…”, however, Liu already provides: continuous numerical leakage values; probabilistic weighting. A person with ordinarily skill in the art would recognize assigning normalized values (0, 0.5, 1) is obvious scaling/representation. Liu’s computation of expected boundary leakage meets the claims “cost function” under BRI.
Applicant argues: “Liu does not disclose generating an abstract view…”
This argument is not persuasive for at least the following reasons:
the claims “abstract view” does not impose specific structural or functional limitations, broadly encompasses representation such as classification of edge types and look up table, merely represents presentation or organization of information.
Liu inherently represents edge configurations, Liu discloses classification of edge types (S, D, FC, FB); classification of abutment typers (S-D, S-S). These classifications inherently form an abstract representation of electrical configuration
Tables and LUTs are abstract representations, Liu provides: LUT1, LUT2
Applicant’s arguments do not overcome Liu because (1) Liu discloses all elements in a single method; (2) “cost function” is fully met by expected leakage computation; (3) layout optimization is explicitly taught; (4) “abstract view” is broadly encompasses representations such as classification and look up table, which are taught by Liu.
Accordingly, the Examiner maintains the position previously set forth.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu PG PUB 20230306181 (hereinafter Liu).
Regarding independent claim 1, Liu teaches a device (figure 14), comprising:
memory (520 plus circuit responsible for store program instruction in 510 in figure 14) that is configured to store program instructions; and
processing circuitry (circuit responsible for execute program instruction 510 in figure 14), coupled to the memory, and configured to execute the program instructions to perform a process to limit current leakage, wherein in performing the process, the processing circuitry is configured to: receive an input of an initial layout (LO1 in figure 14 and [0108], “…In response to the expected boundary leakages exceeds a tolerance range, the processor 510 will adjust the initial layout LO1 (e.g., re-arrange the abutments or locations of cells in the layout) into an adjusted layout LO2, in order to reduce the boundary leakages…”) of a semiconductor structure comprising a plurality of cells (CL1/CL2/CL3 in figure 1);
identify (S210 in figure 2, S410 in figure 13) a plurality of edge source/drain regions (“EGma” or “EGmb” indicated in [0039], “…the cell edge EGma is utilized as a source terminal (S) in the cell CLm; the cell edge EGmb is utilized as a drain terminal (D) in the cell CLm; the cell edge EGmc is utilized as a drain terminal (D) in the cell CLm; and the cell edge EGmd is utilized as a source terminal (S) in the cell CLm …”) in respective ones of the plurality of cells;
determine respective electrical configurations (“cell edges”, “filler depth” indicated in [0046], “…operation S230, the method 200 is utilized to identify cell abutment cases corresponding to each of the boundaries based on the attributes associated with the cell edges of the abutted cells… the cell edges of the abutted cells can be different terminal types and/or have different filler depths, such that there are various combinations of cell abutment cases related to different cell edges of the abutted cells…”) for the plurality of edge source/drain regions;
compute respective values (S240 in figures 2/6, S440 in figure 13) associated with current leakage for adjacent cells of the plurality of cells in the initial layout (LO1 in figure 14) and in a plurality of alternative layouts (LO2 in [0108], “…In response to the expected boundary leakages exceeds a tolerance range, the processor 510 will adjust the initial layout LO1 (e.g., re-arrange the abutments or locations of cells in the layout) into an adjusted layout LO2, in order to reduce the boundary leakages…”) of the semiconductor structure based at least in part on the respective electrical configurations for the plurality of edge source/drain regions; and
identify at least one alternative layout of the plurality of alternative layouts to the initial layout by computing one or more cost functions ([0071], “…the method is performed to calculate expected boundary leakages between the abutted cells according to a sum of products between the leakage current values and the leakage probabilities…”, the term “cost function” describes a result of computation (leakage value). Under BRI, a “cost function” broadly reads on any computed value used for evaluation/optimization. Liu’s “expected boundary leakage” is functionally equivalent to applicant’s “cost function”) and determining the at least one alternative layout based on the computed one or more cost functions (Liu teaches modifying layout based on leakage evaluation, [0075], “…an optimization tool can avoid cell abutment with more leakage probability and displace cell abutment to other location for reducing the expected boundary leakages…”, [0106], “…operation S460 is executed to adjust the layout of the semiconductor device 100 based on at least the expected boundary leakages…”), wherein the at least one alternative layout results in at least a reduction of total current leakage from the initial layout ([0075], “…an optimization tool can … reducing the expected boundary leakages...”, [0108], “…In response to the expected boundary leakages exceeds a tolerance range, the processor 510 will adjust the initial layout LO1 (e.g., re-arrange the abutments or locations of cells in the layout) into an adjusted layout LO2, in order to reduce the boundary leakages…”)
Alternatively, Liu does not explicitly describe “cost function”, however, it is well known in semiconductor design and optimization to represent evaluation metrics (e.g., leakage, power, delay) as cost functions to guide layout optimization, it would have been obvious to a person of ordinary skill in the art to express Liu’s computed “expected boundary leakage” as a cost function, because cost function are routinely used in electronic design automation (EDA) tools to evaluate and optimize layout parameters such as leakage, power and delay. Doing so would have provided a predictable benefit of enabling systematic comparison and optimization of alternative layout.
Regarding claim 2, Liu teaches the device of claim 1, wherein the respective electrical configurations for the plurality of edge source/drain regions comprise at least one of a power connection (power for boundary gates TG1p, TG1n indicated in [0034]), a signal connection and a floating configuration ([0035]/[0036], “…the above cell abutment cases include determinations of whether the boundary between abutted cells is a source-source boundary, a source-drain boundary, or a drain-drain boundary, different depths of filler cells, different voltage thresholds… For example, between the different abutment conditions, a Source-to-Drain (S-D) abutment generally experiences more boundary leakage than a Source-to-Source (S-S) abutment. [0036] Because these different attributes of the transistors, the cell edges, the cell abutment cases (e.g., abutment type, voltage thresholds, MOS type, or the like) contribute to differences in the amount of leakage at different boundaries between adjacent cells…”)
Regarding claim 3, Liu teaches the device of claim 1, wherein, in computing the respective values associated with the current leakage for the adjacent cells, the processing circuitry is configured to identify electrical configurations of respective edge source/drain regions of a plurality of pairs of the adjacent cells (S430 in figure 13), wherein the respective values associated with current leakage for the adjacent cells are computed based on the electrical configurations of the respective edge source/drain regions of the plurality of pairs of the adjacent cells (figure 13).
Regarding claim 4, Liu teaches the device of claim 3, wherein, in computing the respective values associated with the current leakage for the adjacent cells, the processing circuitry is configured to generate an abstract view of the electrical configurations of the respective edge source/drain regions of the plurality of pairs of the adjacent cells (figure 13).
Regarding claim 5, Liu teaches the device of claim 3, wherein the respective values associated with the current leakage for the adjacent cells vary based on a type and a combination of the electrical configurations of the respective edge source/drain regions of the plurality of pairs of the adjacent cells ([0035]/[0036], “…the above cell abutment cases include determinations of whether the boundary between abutted cells is a source-source boundary, a source-drain boundary, or a drain-drain boundary, different depths of filler cells, different voltage thresholds… For example, between the different abutment conditions, a Source-to-Drain (S-D) abutment generally experiences more boundary leakage than a Source-to-Source (S-S) abutment. [0036] Because these different attributes of the transistors, the cell edges, the cell abutment cases (e.g., abutment type, voltage thresholds, MOS type, or the like) contribute to differences in the amount of leakage at different boundaries between adjacent cells…”)
Regarding claim 6, Liu teaches the device of claim 3, wherein, in computing the respective values associated with the current leakage for the adjacent cells, the processing circuitry is configured to identify a plurality of gate tie-down structures (“boundary gate” indicated in [0032], “…a boundary gate TG1p is implemented at the boundary BD1 between P-channel portions CL1p and CL2p of the cells CL1 and CL2, and the boundary gate TG1p is electrically coupled to a system voltage rail RVDD. The system voltage rail RVDD is configured to provide a high system voltage VDD to the boundary gate TG1p. The boundary gate TG1p coupled with the high system voltage VDD is configured to limit (or block) a leakage current between the P-channel portion CL1p of the cell CL1 and the P-channel portion CL2p of the cell CL2. Another boundary gate TG1n is implemented at the boundary BD1 between N-channel portions CL1n and CL2n, and the boundary gate TG1n is electrically coupled to another system voltage rail RVSS. The system voltage rail RVSS is configured to provide a low system voltage VSS to the boundary gate TG1n. The boundary gate TG1n coupled with the low system voltage VSS is configured to limit (or block) a leakage current between the N-channel portion CL1n of the cell CL1 and the N-channel portion CL2n of the cell CL2. Effectively, the boundary gates TG1p and TG1n are configured to isolate the cells CL1 and CL2…”) in the initial layout and in the plurality of alternative layouts, and wherein the plurality of edge source/drain regions correspond to at least a subset of the plurality of gate tie-down structures.
Regarding claim 7, Liu teaches the device of claim 1, wherein, in identifying the at least one alternative layout of the plurality of alternative layouts to the initial layout, the processing circuitry is configured to further base the identification of the at least one alternative layout on one or more parameters in addition to the reduction of the total current leakage (S460 in figure 13).
Regarding claim 8, Liu teaches the device of claim 7, wherein the one or more parameters comprise at least one of wire length, frequency and area of one or more devices in the semiconductor structure (figure 12 and [0035] teaches leakage current can be affected by voltage thresholds, threshold of transistors is related to wire length of gate).
Regarding claim 9, Liu teaches the device of claim 1, wherein the processing circuitry is further configured to compute a total current leakage of the at least one alternative layout (“expected boundary leakage” in S440 in figure 130), wherein the computing of the total current leakage of the at least one alternative layout comprises: identifying a plurality of gate tie-down structures (“TG1p, TG1n, TG2p and TG2n” in [0034]) in the at least one alternative layout; identifying respective ones of the plurality of edge source/drain regions corresponding to at least a subset of the plurality of gate tie-down structures (S410/S420 in figure 13); identifying electrical configurations of the respective ones of the plurality of edge source/drain regions of a plurality of pairs of adjacent cells in the at least one alternative layout (S430 in figure 13); computing leakage values for the respective ones of the plurality of pairs of the adjacent cells in the at least one alternative layout based at least in part on the electrical configurations of the respective ones of the plurality of edge source/drain regions (S440 in figure 13); and adding the leakage values for the respective ones of the plurality of pairs of the adjacent cells in the at least one alternative layout (S450/S460 in figure 13).
Regarding claim 10, Liu teaches the device of claim 1, wherein the processing circuitry is configured to apply the at least one alternative layout to a semiconductor manufacturing system adapted to fabricate the semiconductor structure based at least in part on the at least one alternative layout ([0106], “…After the expected boundary leakages (and/or the maximal/minimal boundary leakages) of the semiconductor device 100 are calculated, operation S460 is executed to adjust the layout of the semiconductor device 100 based on at least the expected boundary leakages…”)
Regarding independent claim 11, Liu teaches a system (figure 14), comprising: a computing system (figure 14), wherein the computing system comprises memory (520 plus circuit responsible for store program instruction in 510 in figure 14) that is configured to store program instructions, and processing circuitry (circuit responsible for execute program instruction 510 in figure 14), coupled to the memory, and configured to execute the program instructions to perform a process to limit current leakage, wherein in performing the process, the processing circuitry is configured to:
receive an input of an initial layout (LO1 in figure 14 and [0108], “…In response to the expected boundary leakages exceeds a tolerance range, the processor 510 will adjust the initial layout LO1 (e.g., re-arrange the abutments or locations of cells in the layout) into an adjusted layout LO2, in order to reduce the boundary leakages…”) of a semiconductor structure comprising a plurality of cells;
identify (S210 in figure 2, S410 in figure 13) a plurality of edge source/drain regions (“EGma” or “EGmb” indicated in [0039], “…the cell edge EGma is utilized as a source terminal (S) in the cell CLm; the cell edge EGmb is utilized as a drain terminal (D) in the cell CLm; the cell edge EGmc is utilized as a drain terminal (D) in the cell CLm; and the cell edge EGmd is utilized as a source terminal (S) in the cell CLm …”) in respective ones of the plurality of cells;
compute (S240 in figures 2/6, S440 in figure 13) respective values associated with current leakage for adjacent cells of the plurality of cells in the initial layout (LO1 in figure 14) and in a plurality of alternative layouts (LO2 in [0108], “…In response to the expected boundary leakages exceeds a tolerance range, the processor 510 will adjust the initial layout LO1 (e.g., re-arrange the abutments or locations of cells in the layout) into an adjusted layout LO2, in order to reduce the boundary leakages…”) of the semiconductor structure based at least in part on the respective electrical configurations (“cell edges”, “filler depth”, threshold, terminal types indicated in [0046], “…operation S230, the method 200 is utilized to identify cell abutment cases corresponding to each of the boundaries based on the attributes associated with the cell edges of the abutted cells… the cell edges of the abutted cells can be different terminal types and/or have different filler depths, such that there are various combinations of cell abutment cases related to different cell edges of the abutted cells…”) for the plurality of edge source/drain regions; and
identify at least one alternative layout of the plurality of alternative layouts to the initial layout by computing one or more cost functions ([0071], “…the method is performed to calculate expected boundary leakages between the abutted cells according to a sum of products between the leakage current values and the leakage probabilities…”, the term “cost function” describes a result of computation (leakage value). Under BRI, a “cost function” broadly reads on any computed value used for evaluation/optimization. Liu’s “expected boundary leakage” is functionally identical to applicant’s “cost function”) and determining the at least one alternative layout based on the computed one or more cost functions (Liu teaches modifying layout based on leakage evaluation, [0075], “…an optimization tool can avoid cell abutment with more leakage probability and displace cell abutment to other location for reducing the expected boundary leakages…”, [0106], “…operation S460 is executed to adjust the layout of the semiconductor device 100 based on at least the expected boundary leakages…”), wherein the at least one alternative layout results in at least a reduction of total current leakage from the initial layout ([0075], “…an optimization tool can … reducing the expected boundary leakages...”, [0108], “…In response to the expected boundary leakages exceeds a tolerance range, the processor 510 will adjust the initial layout LO1 (e.g., re-arrange the abutments or locations of cells in the layout) into an adjusted layout LO2, in order to reduce the boundary leakages…”)
Regarding claim 12, Liu teaches the system of claim 11, wherein the respective electrical configurations for the plurality of edge source/drain regions comprise at least one of a power connection (power for boundary gates TG1p, TG1n indicated in [0034]), a signal connection and a floating configuration ([0035]/[0036], “…the above cell abutment cases include determinations of whether the boundary between abutted cells is a source-source boundary, a source-drain boundary, or a drain-drain boundary, different depths of filler cells, different voltage thresholds… For example, between the different abutment conditions, a Source-to-Drain (S-D) abutment generally experiences more boundary leakage than a Source-to-Source (S-S) abutment. [0036] Because these different attributes of the transistors, the cell edges, the cell abutment cases (e.g., abutment type, voltage thresholds, MOS type, or the like) contribute to differences in the amount of leakage at different boundaries between adjacent cells…”)
Regarding claim 13, Liu teaches the system of claim 11, wherein, in computing the respective values associated with the current leakage for the adjacent cells, the processing circuitry is configured to identify electrical configurations of respective edge source/drain regions of a plurality of pairs of the adjacent cells (S430 in figure 13), wherein the respective values associated with current leakage for the adjacent cells are computed based on the electrical configurations of the respective edge source/drain regions of the plurality of pairs of the adjacent cells (figure 13).
Regarding claim 14, Liu teaches the system of claim 13, wherein, in computing the respective values associated with the current leakage for the adjacent cells, the processing circuitry is configured to identify a plurality of gate tie-down structures (“boundary gate” indicated in [0032], “…a boundary gate TG1p is implemented at the boundary BD1 between P-channel portions CL1p and CL2p of the cells CL1 and CL2, and the boundary gate TG1p is electrically coupled to a system voltage rail RVDD. The system voltage rail RVDD is configured to provide a high system voltage VDD to the boundary gate TG1p. The boundary gate TG1p coupled with the high system voltage VDD is configured to limit (or block) a leakage current between the P-channel portion CL1p of the cell CL1 and the P-channel portion CL2p of the cell CL2. Another boundary gate TG1n is implemented at the boundary BD1 between N-channel portions CL1n and CL2n, and the boundary gate TG1n is electrically coupled to another system voltage rail RVSS. The system voltage rail RVSS is configured to provide a low system voltage VSS to the boundary gate TG1n. The boundary gate TG1n coupled with the low system voltage VSS is configured to limit (or block) a leakage current between the N-channel portion CL1n of the cell CL1 and the N-channel portion CL2n of the cell CL2. Effectively, the boundary gates TG1p and TG1n are configured to isolate the cells CL1 and CL2…”) in the initial layout and in the plurality of alternative layouts, and wherein the plurality of edge source/drain regions correspond to at least a subset of the plurality of gate tie-down structures.
Regarding claim 15, Liu teaches the system of claim 11, wherein the processing circuitry is further configured to compute a total current leakage of the at least one alternative layout (“expected boundary leakage” in S440 in figure 130), wherein the computing of the total current leakage of the at least one alternative layout comprises: identifying a plurality of gate tie-down structures in the at least one alternative layout (“TG1p, TG1n, TG2p and TG2n” in [0034]); identifying respective ones of the plurality of edge source/drain regions corresponding to at least a subset of the plurality of gate tie-down structures (S410 in figure 13); identifying electrical configurations of the respective ones of the plurality of edge source/drain regions of a plurality of pairs of adjacent cells in the at least one alternative layout (S430 in figure 13); computing leakage values for the respective ones of the plurality of pairs of the adjacent cells in the at least one alternative layout based at least in part on the electrical configurations of the respective ones of the plurality of edge source/drain regions (S440 in figure 13); and adding the leakage values for the respective ones of the plurality of pairs of the adjacent cells in the at least one alternative layout (S450/S460 in figure 13).
Regarding claim 16, Liu teaches the system of claim 11, further comprising a semiconductor manufacturing system adapted to fabricate the semiconductor structure based at least in part on the at least one alternative layout ([0106], “…After the expected boundary leakages (and/or the maximal/minimal boundary leakages) of the semiconductor device 100 are calculated, operation S460 is executed to adjust the layout of the semiconductor device 100 based on at least the expected boundary leakages…”)
Regarding independent claim 17, Liu teaches a computer program product (figure 14) for performing a process to limit current leakage, the computer program product comprising: one or more computer readable storage media (520 plus circuit responsible for store program instruction in 510 in figure 14), and program instructions collectively stored on the one or more computer readable storage media, the program instructions comprising: program instructions to receive an input of an initial layout (LO1 in figure 14 and [0108], “…In response to the expected boundary leakages exceeds a tolerance range, the processor 510 will adjust the initial layout LO1 (e.g., re-arrange the abutments or locations of cells in the layout) into an adjusted layout LO2, in order to reduce the boundary leakages…”) of a semiconductor structure comprising a plurality of cells (CL1/CL2/CL3 in figure 1);
program instructions to identify (S210 in figure 2, S410 in figure 13) a plurality of edge source/drain regions (“EGma” or “EGmb” indicated in [0039], “…the cell edge EGma is utilized as a source terminal (S) in the cell CLm; the cell edge EGmb is utilized as a drain terminal (D) in the cell CLm; the cell edge EGmc is utilized as a drain terminal (D) in the cell CLm; and the cell edge EGmd is utilized as a source terminal (S) in the cell CLm …”) in respective ones of the plurality of cells; program instructions to determine (S420/S430 in figure 13) respective electrical configurations (“cell edges”, “filler depth”, threshold, terminal types indicated in [0046], “…operation S230, the method 200 is utilized to identify cell abutment cases corresponding to each of the boundaries based on the attributes associated with the cell edges of the abutted cells… the cell edges of the abutted cells can be different terminal types and/or have different filler depths, such that there are various combinations of cell abutment cases related to different cell edges of the abutted cells…”) for the plurality of edge source/drain regions; program instructions to compute (S440 in figure 13) respective values associated with current leakage for adjacent cells of the plurality of cells in the initial layout and in a plurality of alternative layouts of the semiconductor structure based at least in part on the respective electrical configurations for the plurality of edge source/drain regions; and
program instructions (S460 in figure 13) to identify at least one alternative layout of the plurality of alternative layouts to the initial layout by computing one or more cost functions ([0071], “…the method is performed to calculate expected boundary leakages between the abutted cells according to a sum of products between the leakage current values and the leakage probabilities…”, the term “cost function” describes a result of computation (leakage value). Under BRI, a “cost function” broadly reads on any computed value used for evaluation/optimization. Liu’s “expected boundary leakage” is functionally identical to applicant’s “cost function”) and determining the at least one alternative layout based on the computed one or more cost functions (Liu teaches modifying layout based on leakage evaluation, [0075], “…an optimization tool can avoid cell abutment with more leakage probability and displace cell abutment to other location for reducing the expected boundary leakages…”, [0106], “…operation S460 is executed to adjust the layout of the semiconductor device 100 based on at least the expected boundary leakages…”), wherein the at least one alternative layout results in at least a reduction of total current leakage from the initial layout ([0075], “…an optimization tool can … reducing the expected boundary leakages...”, [0108], “…In response to the expected boundary leakages exceeds a tolerance range, the processor 510 will adjust the initial layout LO1 (e.g., re-arrange the abutments or locations of cells in the layout) into an adjusted layout LO2, in order to reduce the boundary leakages…”)
Regarding claim 18, Liu teaches the computer program product of claim 17, wherein the respective electrical configurations for the plurality of edge source/drain regions comprise at least one of a power connection (power for boundary gates TG1p, TG1n indicated in [0034]), a signal connection and a floating configuration ([0035]/[0036], “…the above cell abutment cases include determinations of whether the boundary between abutted cells is a source-source boundary, a source-drain boundary, or a drain-drain boundary, different depths of filler cells, different voltage thresholds… For example, between the different abutment conditions, a Source-to-Drain (S-D) abutment generally experiences more boundary leakage than a Source-to-Source (S-S) abutment. [0036] Because these different attributes of the transistors, the cell edges, the cell abutment cases (e.g., abutment type, voltage thresholds, MOS type, or the like) contribute to differences in the amount of leakage at different boundaries between adjacent cells…”)
Regarding claim 19, Liu teaches the computer program product of claim 17, wherein the program instructions to compute (S440 in figure 13) the respective values associated with the current leakage for the adjacent cells comprise program instructions to identify electrical configurations (“cell edges”, “filler depth”, threshold, terminal types indicated in [0046], “…operation S230, the method 200 is utilized to identify cell abutment cases corresponding to each of the boundaries based on the attributes associated with the cell edges of the abutted cells… the cell edges of the abutted cells can be different terminal types and/or have different filler depths, such that there are various combinations of cell abutment cases related to different cell edges of the abutted cells…”) of respective edge source/drain regions of a plurality of pairs of the adjacent cells, wherein the respective values associated with current leakage for the adjacent cells are computed based on the electrical configurations of the respective edge source/drain regions of the plurality of pairs of the adjacent cells (figure 13).
Regarding claim 20, Liu teaches the computer program product of claim 19, wherein the program instructions to compute the respective values associated with the current leakage for the adjacent cells comprise program instructions to identify a plurality of gate tie-down structures (“boundary gate” indicated in [0032], “…a boundary gate TG1p is implemented at the boundary BD1 between P-channel portions CL1p and CL2p of the cells CL1 and CL2, and the boundary gate TG1p is electrically coupled to a system voltage rail RVDD. The system voltage rail RVDD is configured to provide a high system voltage VDD to the boundary gate TG1p. The boundary gate TG1p coupled with the high system voltage VDD is configured to limit (or block) a leakage current between the P-channel portion CL1p of the cell CL1 and the P-channel portion CL2p of the cell CL2. Another boundary gate TG1n is implemented at the boundary BD1 between N-channel portions CL1n and CL2n, and the boundary gate TG1n is electrically coupled to another system voltage rail RVSS. The system voltage rail RVSS is configured to provide a low system voltage VSS to the boundary gate TG1n. The boundary gate TG1n coupled with the low system voltage VSS is configured to limit (or block) a leakage current between the N-channel portion CL1n of the cell CL1 and the N-channel portion CL2n of the cell CL2. Effectively, the boundary gates TG1p and TG1n are configured to isolate the cells CL1 and CL2…”) in the initial layout and in the plurality of alternative layouts, and wherein the plurality of edge source/drain regions correspond to at least a subset of the plurality of gate tie-down structures.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/XIAOCHUN L CHEN/ Primary Examiner, Art Unit 2824