DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim and Specification Status
The Examiner acknowledges the amendments to claim 11 in the Applicant’s response dated 3 June 2026 in lieu of the 35 U.S.C. 112(a) rejection presented in the previous office action. The 35 U.S.C. 112(a) rejection has therefore been withdrawn.
The Examiner acknowledges the addition of new claim 21 in the Applicant’s response dated 3 June 2026. The new claim has been addressed below.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 22 May 2026 has been considered by the examiner and made of record in the application file.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 7-8 and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kiyoshi Arita et al. (US 2020/0381367 A1; hereinafter “Arita”).
Regarding Claim 1, Arita teaches a manufacturing method of a semiconductor apparatus, comprising:
forming a mark by forming an upper surface mark on an upper surface of a semiconductor substrate (R1, Fig. 7A, para [0072] describes forming a first region R1 wherein the first region is a trench type mark provided on an upper surface of the semiconductor substrate 10) and a lower surface mark on a lower surface of the semiconductor substrate (15, Fig. 7A, para [0072] describes forming alignment marks 15 on a lower surface 10X of a semiconductor substrate 10);
detecting a position by detecting positional deviation of the upper surface mark and the lower surface mark, by acquiring an upper surface image obtained by observing the upper surface mark from above the upper surface of the semiconductor substrate and a lower surface image obtained by observing the lower surface mark through the semiconductor substrate from above the upper surface of the semiconductor substrate (300, Fig. 9, para [0079] describes wherein an infrared image 300 captures an image of alignment mark 15 from above an upper surface of the semiconductor substrate 10 through the semiconductor substrate 10 by observing the lower surface mark 15 through the upper surface mark R1 wherein the captured image is used to calculate a shape and position for a subsequent processing step);
and forming an element by forming a semiconductor element in the semiconductor substrate (200, Fig. 11, para [0086] describes wherein a subsequent processing step removes portions of a semiconductor layer 11 along a second region R2 and divided into a plurality of element chips 200), wherein
in a top view in which the upper surface mark and the lower surface mark are projected onto a plane parallel to the upper surface (15 and R1, Fig. 7B depicts a top view in which the upper surface mark R1 and lower surface mark 15 are projected onto a plane parallel to an upper surface of semiconductor substrate 10), one of the upper surface mark and the lower surface mark is larger than an other, and the one entirely covers the other (R1, Fig. 7B, para [0072] describes wherein upper surface mark R1 surrounds lower surface mark 15 wherein Fig. 7B depicts upper surface mark R1 being larger than lower surface mark 15 and entirely covering lower surface mark 15).
Regarding Claim 7, Arita teaches the manufacturing method of a semiconductor apparatus according to claim 1, wherein
in the top view, a distance between an end portion of the lower surface mark and an end portion of the upper surface mark is 20 μm or more (16 and 11, Fig. 7A, para [0040] describes wherein the semiconductor substrate 10 is formed of a metal film layer 16 and semiconductor layer 11 wherein an end portion of the upper surface mark R1 is comprised at an upper surface of metal film layer 16 and para [0040] describes wherein metal film layer may be in a range of 50 nm or more and 100 μm or less wherein a metal film layer of 20 μm or more would result in a distance of an end portion of the lower surface mark 15 comprised in semiconductor layer 11 and an end portion of an upper surface mark R1 being 20 μm or more).
Regarding Claim 8, Arita teaches the manufacturing method of a semiconductor apparatus according to claim 1, wherein
in the detecting the position, a wavelength of a light to be irradiated to the semiconductor substrate (para [0078] describes wherein a laser irradiator is used in combination with the infrared camera 300 to detect the position and shape of the alignment mark 15 through the first region R1) in a case where the upper surface image is acquired is a same as a wavelength of a light irradiated to the semiconductor substrate in a case where the lower surface image is acquired (para [0078] describes the use of a laser irradiator to in conjunction with the infrared camera 300 to detect the position and shape of the alignment mark 15 through the first region R1 wherein para [0061] describes using a laser beam of a single wavelength when irradiating a wavelength to the semiconductor substrate 10).
Regarding Claim 21, Arita teaches the manufacturing method of a semiconductor apparatus according to claim 1, wherein the positional deviation of the upper surface mark and the lower surface mark (300, R1 and 15, Fig. 7B and Fig. 9, para [0078] describes wherein a processing unit processes an image captured by a camera 300 to detect the position and the shape, etc. of the lower surface mark 15 through the upper surface mark R1 viewed from above an upper surface of a substrate 22) is detected based on positions of the upper surface mark and the lower surface mark identified from the upper surface image and the lower surface image (R1 and 15, Fig. 7B and Fig. 9, para [0078] and para [0079] describes wherein the positional deviation calculated by the image processing unit is detected by using a camera 300 to capture an image of the lower surface mark 15 through the upper surface mark R1 wherein the image captured will include an image of the upper surface mark R1, such as described in para [0059] wherein the upper surface mark R1 includes a circumscribed circle 100 μm in diameter and the field of view of the camera 300 is 300 μm square such that the camera image detects a position of the upper surface mark R1 circumscribed circle in an upper surface image and further captures a lower surface image of the lower surface mark 15 viewed through the circumscribed circle of the upper surface mark R1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-5 are rejected under 35 U.S.C. 103 as being unpatentable over Kiyoshi Arita et al. (US 2020/0381367 A1; hereinafter “Arita”) in view of Naoko Kodama (US 2019/0206803 A1; hereinafter “Kodama”).
Regarding Claim 2, Arita discloses all the limitations of claim 1.
Arita fails to explicitly disclose the manufacturing method of a semiconductor apparatus according to claim 1, wherein in the forming the mark, a cover portion for covering the lower surface mark is formed of a material having a reflectance rate higher than the lower surface mark.
However, Kodama teaches a similar manufacturing method of a semiconductor apparatus wherein
in the forming the mark, a cover portion for covering the lower surface mark is formed of a material having a reflectance rate higher than the lower surface mark (3 and 52, Fig. 14 and Fig. 15para [0067] describes wherein a back alignment mark 3 may be formed of a stacked film comprising a field oxide film, polysilicon film, and an insulating film and para [0090] describes a cover portion 52 comprised of a metal film such as aluminum wherein an aluminum film would have a higher reflectance rate than a stacked film as described and further wherein para [0094] and Fig. 14 describe wherein cover portion 52 reflects all of the infrared light and Fig. 15 depicts wherein some of the infrared light may pass through back alignment mark 3).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Arita with Kodama to further disclose a manufacturing method of a semiconductor apparatus which comprises a cover portion of a higher reflectance than a back alignment mark to provide the advantage of improving detection accuracy of a back alignment mark by a reflected infrared light and enabling a semiconductor substrate thickness to be further increased (Kodama, para [0095]).
Regarding Claim 3, the combination of Arita and Kodama teach the manufacturing method of a semiconductor apparatus according to claim 2, wherein
in the top view, the upper surface mark is larger than the lower surface mark (Arita, R1, Fig. 7B, para [0072] describes wherein upper surface mark R1 surrounds lower surface mark 15 wherein Fig. 7B depicts upper surface mark R1 being larger than lower surface mark 15 and entirely covering lower surface mark 15).
Regarding Claim 4, the combination of Arita and Kodama disclose all the limitations of claim 3.
The combination of Arita and Kodama fail to explicitly disclose the manufacturing method of a semiconductor apparatus according to claim 3, wherein in the top view, the cover portion is larger than the lower surface mark and is smaller than the upper surface mark.
However, Arita discloses wherein an upper surface mark (R1) surrounds a lower surface mark (15) resulting in an upper surface mark (R1) which is larger than a lower surface mark (15). Kodama discloses a cover portion (52) that may have at least a same size width and length as a lower surface mark (51) or greater thus resulting in a cover portion that may be at least 1 μm larger than a lower surface mark (Kodama, para [0089]).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to try different size upper surface marks (R1) and cover portions (52) resulting in a cover portion that is larger than a lower surface mark and smaller than an upper surface mark, in order to provide the advantage of providing a manufacturing apparatus which provides a cover portion which improves detection accuracy of a back alignment mark (Kodama, para [0092]) and an upper surface mark that is larger than the cover portion so that it enables the improved reflected light to be able to reach the infrared receiver which calculates shape and position (Arita, para [0079]) see MPEP 2144.04 (IV)(A), and MPEP 2144.05 (II)(A)(B).
Regarding Claim 5, the combination of Arita and Kodama teach the manufacturing method of a semiconductor apparatus according to claim 4,
wherein in the top view, a distance between an end portion of the cover portion and an end portion of the lower surface mark (Kodama, Fig. 14, para [0088] describes wherein an end portion of cover portion 52 shares a same end portion of a lower surface mark 51 provided on a surface 1a of the semiconductor substrate 1 wherein a resulting distance would be essentially zero) is smaller than a distance between the end portion of the cover portion and an end portion of the upper surface mark (Upon combining Arita with Kodama, an end portion of the cover portion 52 of Kodama would be separated from an end portion of the upper surface mark R1 of Arita by at least a semiconductor substrate (10 of Arita and 1 of Kodama) wherein Arita describes in para [0033] a thickness of a semiconductor substrate 10 may be 50 mm or more which is greater than a distance of an end portion of the cover portion 52 and the lower surface mark (51 of Kodama and 15 of Arita)).
Claims 9, 12 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Kiyoshi Arita et al. (US 2020/0381367 A1; hereinafter “Arita”) in view of Yu-Wei Cheng et al. (US 2020/0219821 A1; hereinafter “Cheng”).
Regarding Claim 9, Arita discloses all the limitations of claim 1.
Arita fails to explicitly disclose the manufacturing method of a semiconductor apparatus according to claim 1, wherein the upper surface mark is a concave portion arranged on the upper surface of the semiconductor substrate.
However, Cheng teaches a similar manufacturing method of a semiconductor apparatus, wherein the upper surface mark is a concave portion arranged on the upper surface of the semiconductor substrate (S1, Fig. 2, para [0018] describes upper surface marks S1(P2) on an upper surface of semiconductor layer 31 wherein upper surface marks S1(P2) may be concave).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Arita with Cheng to further disclose a manufacturing method of a semiconductor apparatus which comprises an upper surface mark which is a concave portion on an upper surface of a semiconductor substrate in order to provide the well-known advantage of providing a shape of an upper surface mark which promotes reflectivity of light inside of a cavity leading to a lower surface alignment mark further improving detection accuracy of a lower surface mark providing a more precise subsequent wafer processing step.
Regarding Claim 12, the combination of Arita and Cheng teaches the manufacturing method of a semiconductor apparatus according to claim 9, wherein
the lower surface mark has two or more straight portions with their respective longitudinal directions crossing each other, in the top view (Arita, 15, Fig. 7B, para [0038] describes wherein a shape of the lower surface mark 15 may be a combination of straight lines, such as a cross shape wherein a cross shape of more than one line would comprise two or more straight portions with their respective longitudinal direction crossing each other, as shown in the top view of Fig. 7B).
Regarding Claim 18, Arita discloses all the limitations of claim 7.
Arita fails to explicitly disclose the manufacturing method of a semiconductor apparatus according to claim 7, wherein the upper surface mark is a concave portion arranged on the upper surface of the semiconductor substrate.
However, Cheng teaches a similar manufacturing method of a semiconductor apparatus, wherein the upper surface mark is a concave portion arranged on the upper surface of the semiconductor substrate (S1, Fig. 2, para [0018] describes upper surface marks S1(P2) on an upper surface of semiconductor layer 31 wherein upper surface marks S1(P2) may be concave).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Arita with Cheng to further disclose a manufacturing method of a semiconductor apparatus which comprises an upper surface mark which is a concave portion on an upper surface of a semiconductor substrate in order to provide the well-known advantage of providing a shape of an upper surface mark which promotes reflectivity of light inside of a cavity leading to a lower surface alignment mark further improving detection accuracy of a lower surface mark providing a more precise subsequent wafer processing step.
Regarding Claim 19, Arita discloses all the limitations of claim 8.
Arita fails to explicitly disclose the manufacturing method of a semiconductor apparatus according to claim 8, wherein the upper surface mark is a concave portion arranged on the upper surface of the semiconductor substrate.
However, Cheng teaches a similar manufacturing method of a semiconductor apparatus, wherein the upper surface mark is a concave portion arranged on the upper surface of the semiconductor substrate (S1, Fig. 2, para [0018] describes upper surface marks S1(P2) on an upper surface of semiconductor layer 31 wherein upper surface marks S1(P2) may be concave).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Arita with Cheng to further disclose a manufacturing method of a semiconductor apparatus which comprises an upper surface mark which is a concave portion on an upper surface of a semiconductor substrate in order to provide the well-known advantage of providing a shape of an upper surface mark which promotes reflectivity of light inside of a cavity leading to a lower surface alignment mark further improving detection accuracy of a lower surface mark providing a more precise subsequent wafer processing step.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Kiyoshi Arita et al. (US 2020/0381367 A1; hereinafter “Arita”) in view of Yu-Wei Cheng et al. (US 2020/0219821 A1; hereinafter “Cheng”) and in further view of Naoko Kodama (US 2019/0206803 A1; hereinafter “Kodama”).
Regarding Claim 11, the combination of Arita and Cheng discloses all the limitations of claim 9.
The combination of Arita and Cheng fails to explicitly disclose the manufacturing method of a semiconductor apparatus according to claim 9, wherein in the top view, a region provided with no concave or convex extends continuously from an end portion of the upper surface mark toward an outside for a distance of at least 20 μm.
However, Kodama teaches a similar manufacturing method of a semiconductor apparatus wherein
in the top view, a region provided with no concave or convex extends continuously from an end portion of the upper surface mark toward an outside for a distance of at least 20 μm (1, Fig. 12 and Fig. 13, para [0121] describes a width of a slicing line 6 as being larger than a width of the back alignment mark which may be 70 μm wherein a back alignment mark may have approximately a same width as an upper surface mark as shown in at least Fig. 11 and Fig. 13 wherein said width of slicing line is a portion of a semiconductor substrate not being concave or convex as shown in Fig. 12 surrounding back alignment mark 40b wherein upon combining Arita and Cheng with Kodama, a resulting portion of an upper surface of a substrate not being concave or convex comprising cutting lines would be at a minimum or a range of at least 20 μm).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Arita and Cheng with Kodama to further disclose a manufacturing method of a semiconductor apparatus which comprises a region with no concave or convex portions extending continuously from an end portion of an upper surface mark toward an outside for a distance of at least 20 μm in order to provide the advantage of providing cutting lines on a substrate wide enough for a dicing saw to cut portions of the substrate into individual chips in subsequent processing steps (Kodama, para [0104] and para [0109]).
Claims 13-16 are rejected under 35 U.S.C. 103 as being unpatentable over Kiyoshi Arita et al. (US 2020/0381367 A1; hereinafter “Arita”) in view of Naoko Kodama (US 2019/0206803 A1; hereinafter “Kodama”) and in further view of Yu-Wei Cheng et al. (US 2020/0219821 A1; hereinafter “Cheng”).
Regarding Claim 13, the combination of Arita and Kodama discloses all the limitations of claim 2.
The combination of Arita and Kodama fails to explicitly disclose the manufacturing method of a semiconductor apparatus according to claim 2, wherein the upper surface mark is a concave portion arranged on the upper surface of the semiconductor substrate.
However, Cheng teaches a similar manufacturing method of a semiconductor apparatus, wherein the upper surface mark is a concave portion arranged on the upper surface of the semiconductor substrate (S1, Fig. 2, para [0018] describes upper surface marks S1(P2) on an upper surface of semiconductor layer 31 wherein upper surface marks S1(P2) may be concave).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Arita and Kodama with Cheng to further disclose a manufacturing method of a semiconductor apparatus which comprises an upper surface mark which is a concave portion on an upper surface of a semiconductor substrate in order to provide the well-known advantage of providing a shape of an upper surface mark which promotes reflectivity of light inside of a cavity leading to a lower surface alignment mark further improving detection accuracy of a lower surface mark providing a more precise subsequent wafer processing step.
Regarding Claim 14, the combination of Arita and Kodama discloses all the limitations of claim 3.
The combination of Arita and Kodama fails to explicitly disclose the manufacturing method of a semiconductor apparatus according to claim 3, wherein the upper surface mark is a concave portion arranged on the upper surface of the semiconductor substrate.
However, Cheng teaches a similar manufacturing method of a semiconductor apparatus, wherein the upper surface mark is a concave portion arranged on the upper surface of the semiconductor substrate (S1, Fig. 2, para [0018] describes upper surface marks S1(P2) on an upper surface of semiconductor layer 31 wherein upper surface marks S1(P2) may be concave).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Arita and Kodama with Cheng to further disclose a manufacturing method of a semiconductor apparatus which comprises an upper surface mark which is a concave portion on an upper surface of a semiconductor substrate in order to provide the well-known advantage of providing a shape of an upper surface mark which promotes reflectivity of light inside of a cavity leading to a lower surface alignment mark further improving detection accuracy of a lower surface mark providing a more precise subsequent wafer processing step.
Regarding Claim 15, the combination of Arita and Kodama discloses all the limitations of claim 4.
The combination of Arita and Kodama fails to explicitly disclose the manufacturing method of a semiconductor apparatus according to claim 4, wherein the upper surface mark is a concave portion arranged on the upper surface of the semiconductor substrate.
However, Cheng teaches a similar manufacturing method of a semiconductor apparatus, wherein the upper surface mark is a concave portion arranged on the upper surface of the semiconductor substrate (S1, Fig. 2, para [0018] describes upper surface marks S1(P2) on an upper surface of semiconductor layer 31 wherein upper surface marks S1(P2) may be concave).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Arita and Kodama with Cheng to further disclose a manufacturing method of a semiconductor apparatus which comprises an upper surface mark which is a concave portion on an upper surface of a semiconductor substrate in order to provide the well-known advantage of providing a shape of an upper surface mark which promotes reflectivity of light inside of a cavity leading to a lower surface alignment mark further improving detection accuracy of a lower surface mark providing a more precise subsequent wafer processing step.
Regarding Claim 16, the combination of Arita and Kodama discloses all the limitations of claim 5.
The combination of Arita and Kodama fails to explicitly disclose the manufacturing method of a semiconductor apparatus according to claim 5, wherein the upper surface mark is a concave portion arranged on the upper surface of the semiconductor substrate.
However, Cheng teaches a similar manufacturing method of a semiconductor apparatus, wherein the upper surface mark is a concave portion arranged on the upper surface of the semiconductor substrate (S1, Fig. 2, para [0018] describes upper surface marks S1(P2) on an upper surface of semiconductor layer 31 wherein upper surface marks S1(P2) may be concave).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Arita and Kodama with Cheng to further disclose a manufacturing method of a semiconductor apparatus which comprises an upper surface mark which is a concave portion on an upper surface of a semiconductor substrate in order to provide the well-known advantage of providing a shape of an upper surface mark which promotes reflectivity of light inside of a cavity leading to a lower surface alignment mark further improving detection accuracy of a lower surface mark providing a more precise subsequent wafer processing step.
Response to Arguments
Applicant's arguments filed 3 June 2026 have been fully considered but they are not persuasive.
The Applicant argues on page 8, lines 25-27 and page 9, lines 1-19 of the Applicant’s remarks that the prior art of record, Arita, fails to anticipate or render obvious the subject matter recited in claim 1 specifically that Arita fails to disclose “detecting a position by detecting positional deviation of the upper surface mark and the lower surface mark” by acquiring “an upper surface image obtained by observing the upper surface mark” and “a lower surface image obtained by observing the lower surface mark through the semiconductor substrate”. The Examiner respectfully disagrees. The prior art of record, Arita, teaches in para [0023] detecting an alignment mark from a metal film side through a semiconductor layer and then further describes wherein the detected alignment mark is used to calculate the exact position of the dicing region wherein the detected alignment mark is detected by capturing an image of an upper surface mark and lower surface mark as shown in Fig. 9 and described in para [0059] and para [0079] of Arita. Arita further teaches in para [0059] wherein a camera used in a calculation step has a field of view of 300 μm square and the diameter of the upper circular alignment mark is 100 μm, therefore, when the camera used in the calculation step of Arita takes an image to send to an image processing unit as described in para [0067], it will acquire an upper surface image in its field of view by observing the upper surface mark (R1) and a lower surface image by observing the lower surface mark (15) through the semiconductor substrate from above the upper surface of the semiconductor substrate as described in claim 1 of the instant application. As shown in Fig. 7B and Fig. 9 of Arita, an upper surface image and a lower surface image may be acquired from a camera above an upper surface of a substrate, wherein such an image is not excluded from being a same image which includes an image of the entire diameter of the upper surface mark and an image of the lower surface mark through the opening of the upper surface mark. Additionally, because the lower surface mark only comes into view of the camera when viewed through the opening of the upper surface mark, the upper surface mark of Arita must therefore be used a positional reference used in calculating a positional deviation as images are sent from the camera to the image processing unit.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER M MILLER whose telephone number is (571)272-6051. The examiner can normally be reached Monday - Friday 8:00 am - 4:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571(272)-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ALEXANDER MICHAEL MILLER/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
Prosecution Insights