DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions & Claims’ Status
Applicant’s election without traverse of Invention I (Claims 1-11 and 20) in the reply filed on 2/9/2026 is acknowledged.
Claims 12-19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 2/9/2026.
Claims 1-20 are currently pending. Claims 1, 3-5, 12-14, 16, and 18-20 have been amended. No claims have been cancelled or newly added. Claims 1-11 and 20 are being examined, as Claims 12-19 were nonelected without traverse.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liu et al (US 2021/0376071 A1, hereafter Liu).
Re Claim 1, Liu discloses a semiconductor structure (FIG. 31, with reference to FIG. 23B; [0057]) comprising:
a first source/drain region (260, second from left in FIG. 31; [0035]) electrically connected to a backside power rail (284; [0056]) through a backside contact (282; [0056]);
a second source/drain region (260, first from left in FIG. 31; [0035]) electrically connected to a back end of line (BEOL) interconnect (within 277; [0044]-[0045]) through a frontside contact (275; [0044]-[0045]); and
a placeholder structure (274, “etch stop”, see FIG. Z1 below; [0048]-[0049]) on a surface of the second source/drain region (260, first from left in FIG. 31; [0048]-[0049]), wherein:
the placeholder structure (274, “etch stop”) is laterally adjacent to the backside contact (282; [0049]); and
the placeholder structure (274, “etch stop”) comprises an etch stop layer (“etch stop”; [0048], see FIG. 23B for etch stop characteristic) and a sidewall spacer (274; [0049]), the sidewall spacer (274) formed between a backside interlayer dielectric (276; [0049]) and the etch stop layer (“etch stop”; [0049]).
PNG
media_image1.png
254
269
media_image1.png
Greyscale
FIG. Z1: Annotated version of FIG. 31 of Liu
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Liu, as applied to Claim 1, in view of Huang et al (US 2021/0202385 A1, of record, hereafter Huang 1).
Re Claim 6, Liu discloses the structure according to Claim 1, but does not explicitly disclose the structure further comprises a backside power delivery network contacting the backside power rail (284).
However, Huang 1 teaches a semiconductor structure (FIG. 19; [0065]), comprising a backside power delivery network (“corresponding power lines”; [0015]) contacting the backside power rail (118; [0015]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure according to Claim 1 with the limitations taught by Huang 1 to include a power delivery network (Huang 1: “corresponding power lines”) contacting the backside power rail (Liu: 284) to allow for appropriate routing of the power lines as taught by Huang 1 ([0015]).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Liu, as applied to Claim 1, in view of Ju et al (US 2021/0351303 A1, of record, hereafter Ju).
Re Claim 7, Liu discloses the semiconductor structure according to Claim 1, but does not explicitly disclose the structure further comprising a carrier wafer (370) contacting the BEOL interconnect (within 277).
However, Ju teaches a semiconductor structure (FIG. 20) comprising a carrier wafer (240; [0060]) contacting the BEOL interconnect (114; [0060]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure as discussed for Claim 1 with the limitations taught by Ju to utilize a carrier wafer (Ju: 240) contacting the BEOL interconnect (Liu: within 277) to provide a supportive platform for handling the structure as taught by Ju ([0060]).
Claims 8-9 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Liu, as applied to Claim 1, in view of Chu et al (US 2021/0399099 A1, of record, hereafter Chu).
Re Claim 8, Liu discloses the semiconductor structure according to Claim 1, but does not explicitly disclose the structure further comprising a gate region (350) electrically connected to the BEOL interconnect (within 277) through a second frontside contact.
However, Chu teaches a semiconductor structure (FIG. 16; [0021]-[0036]) comprising a gate region (220; [0021]) electrically connected to the BEOL interconnect (240, 242; [0021]) through a second frontside contact (238; [0021]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure as discussed for Claim 1 with the limitations taught by Chu to connect a gate region (Chu: 220) to the BEOL interconnect (Liu: within 277) with an additional frontside contact (Chu: 238) to extend electrical interconnection functions for the device as taught by Chu ([0021]).
Re Claim 9, Liu and Chu teach the semiconductor structure according to Claim 8, while Liu further teaches wherein the gate region (350; [0041]) wraps around a nanosheet stack of semiconductor channel material layers (215; [0041]).
Re Claim 11, Liu and Chu teach the semiconductor structure according to Claim 9, while Liu further teaches wherein an inner spacer layer (255; [0031]) contacts a nanosheet (215) of the nanosheet stack of semiconductor channel material layers (215; [0031]).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Huang et al (US 2022/0130759 A1, hereafter Huang 2).
Re Claim 20, Huang 2 discloses in a first embodiment a semiconductor structure (FIG. 4; [0039]) comprising:
a first source/drain region (260(P); [0038]) and a second source/drain region (260(N); [0038]);
a placeholder structure (239; [0039]) on a surface of the second source/drain region (260(N); [0039]) on a backside of the second source/drain region (260(N), closer to “backside” shown in FIG. 4; [0039]) opposite of a frontside (260(N), closer to “frontside” shown in FIG. 4; [0039]); and
a second contact (282; [0039]) contacting the first source/drain region (260(P); [0039]), the second contact (282) laterally adjacent to the placeholder structure (239; [0039]), wherein a backside interlayer dielectric layer (230; [0023]) completely separates the second contact (282) from the placeholder structure (239; [0039]).
Huang 2 does not explicitly disclose in the first embodiment (FIG. 4) wherein the frontside (260(N), closer to “frontside” shown in FIG. 4) is contacting a first contact.
However, Huang 2 teaches in a related embodiment (FIG. 2D; [0023]) wherein the frontside (260, closer to “frontside” shown in FIG. 2D) is contacting a first contact (275; [0023]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the limitations taught by the first embodiment of Huang 2 with the limitations taught by the related embodiment of Huang 2 to explicitly use first contacts (Huang 2: 275) to allow for electrical contact to the S/D regions (Huang 2: 260) through the frontside of the device as taught by Huang 2 ([0023]).
Allowable Subject Matter
Claims 2-5 and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Re Claim 2, the prior art cannot anticipate, or render obvious, the limitations of: wherein the placeholder structure comprises a silicon buffer layer adjacent to the second source/drain region, in combination with the additionally claimed features of Claim 2.
In Re Claims 3-5 and 10, they are objected to due to being dependent on Claim 2.
Response to Arguments
Applicant’s arguments, see Remarks pg. 3, para. 2 to pg. 5, para. 2, filed 2/9/2026, with respect to the rejection(s) of Claims 1 and 20 under 35 U.S.C. 102(a)(1) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Liu under 35 U.S.C. 102(a)(1) for Claim 1 and in view of Huang 2 under 35 U.S.C. 103 for Claim 20. Applicant’s arguments have been reconsidered in light of the new rejections but are moot because the new ground of rejection(s) does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLIN RUSSELL MCCUTCHEON whose telephone number is (703)756-1897. The examiner can normally be reached Monday-Friday, 12:30-9:30 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DREW N RICHARDS can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/COLIN RUSSELL MCCUTCHEON/Examiner, Art Unit 2892
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892