DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species C (corresponding to embodiment of Figure 5 and which “is encompassed by at least claims 1 to 5 and 7 to 11) in the reply filed on 1/6/2026 is acknowledged. The traversal is on the ground(s) that “for a restriction to be proper, there must be a patentable difference between the species as claimed”. This argument is not persuasive. The restriction requirement of 12/2/2025 specifically stated “Should applicant traverse on the ground that the species, or groupings of patentably indistinct species from which election is required, are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing them to be obvious variants or clearly admit on the record that this is the case” (see page 4, 2nd last paragraph of the restriction requirement). However, applicant has not done the above and in fact specifically states “No statement is made regarding the patentable distinctness of the species” (see page 2, especially 2nd paragraph of applicant’s response). Applicant has also not shown why there is no “serious burden” (as argued on page 2, 3rd paragraph of applicant’s response) given that the species are patentably distinct and not obvious variants of each other. The requirement is still deemed proper and is therefore made FINAL.
Whereas applicant has not elected claim 6, applicant has elected claims 7 and 8 that depend directly or indirectly from claim 6. It appears that at least one of the limitation of claim 6; i.e. “semiconductor region being a semiconductor island” does not read on Figure 5, and as such, claim 6 will be examined as the current scope (i.e. first option only) does read on Figure 5 and is adequate to meet requirements of claim 6. This also enables examination of dependent claims 7 and 8.
As applicant has elected Species C (corresponding to embodiment of Figure 5), claim 6 should be amended to recite features of Figure 5 and any other claim amendments in applicant’s response must read on the elected species of Figure 5.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-5 and 7-11 (see note about withdrawn claim 6 under restriction requirement) are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “a semiconductor region coated with at least one heterogeneous dielectric region” and also recites “one or more transistors at least partially formed in a semiconductor region of said substrate” (emphasis added). It is not clear if the two recitations of “a semiconductor region” (emphasized above by underlined text) refer to the same semiconductor region or different semiconductor regions. For the purposes of this office action, it will be assumed that the above recitations apply to either the same semiconductor region or to two different semiconductor regions. It is suggested that the above recitations be replace by “a first semiconductor region” and “a second semiconductor region” and specifically stating if the two can be same or different.
Claim 10, which depends from claim 1, recites “said semiconductor region”. However, in claim 1, there are two instances of “a semiconductor region” (as also explained above for claim 1) and it is not clear which of these is being referred to by “said semiconductor region”. For the purposes of this office action, the recitation “said semiconductor region” will be considered to be referring to any one of the two “a semiconductor region” recited in claim 1.
A broad range or limitation together with a narrow range or limitation that falls within the broad range or limitation (in the same claim) may be considered indefinite if the resulting claim does not clearly set forth the metes and bounds of the patent protection desired. See MPEP § 2173.05(c). In the present instance, claim 1 recites the broad recitation “one or more electronic components”, and the claim also recites “in particular one or more transistors…” which is the narrower statement of the range/limitation. Similarly, claim 7 recites the broad recitation “at least one RF component”, and the claim also recites “such as an antenna or an inductance or a waveguide, said RF component” which is the narrower statement of the range/limitation. The claims are considered indefinite because there is a question or doubt as to whether the feature introduced by such narrower language is (a) merely exemplary of the remainder of the claim, and therefore not required, or (b) a required feature of the claims. For the purposes of this office action, the recitation “one or more electronic components, in particular one or more transistors…” of claim 1 will be considered equivalent of “one or more electronic components, and the recitation “at least one RF component such as an antenna or an inductance or a waveguide, said RF component” of claim 7 will be considered equivalent of “includes a charge trapping region,
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-5 and 7-11 (see note about withdrawn claim 6 under restriction requirement) are rejected under 35 U.S.C. 103 as being unpatentable over Englekirk (US 20180337043), hereinafter Englekirk, in view of Cheng (US 20200098791), hereinafter Cheng.
Regarding claim 1, Englekirk (US 20180337043) (refer to Figure 6B) teaches a microelectronic device comprising:
a structure for an RF device {i.e. comprising 612, , described as "RF circuitry 612 " in para 88} provided with a substrate {600, described as "SOI wafer 600" in para 83}, the substrate being provided with a semiconductor region {402 and 404, described as "high resistivity substrate 402 typically include very lightly doped silicon" and “trap rich layer 404” in para 83; also see para 17} coated with at least one dielectric region {406, described as "BOX insulator layer 406" in para 84},
one or more electronic components, in particular one or more transistors {410, described as "FETs 410" in para 86} at least partially formed in a semiconductor region {408, described as "active layer 408" in para 86} of said substrate,
at least one RF component {i.e. comprising 612, described as "RF circuitry 612 " in para 88} such as an antenna or an inductance or a waveguide, said RF component being arranged opposite to (best seen in Figure 6B) said dielectric region {406}.
Englekirk does not teach that the at least one dielectric region is a “heterogeneous” dielectric region, such that “said heterogeneous dielectric region including, in at least one first given direction dl parallel to a main plane of the substrate, an alternation of first areas made of a first dielectric material with positive fixed charges and of second dielectric areas made of a second dielectric material with negative fixed charges”.
Cheng (US 20200098791) (refer to Figure 1) teaches a microelectronic device comprising a substrate provided with a semiconductor region coated with at least one dielectric region {20 and 120 – see para 24 that describes each having “fixed charge”, wherein one is “positively charged” and other is “negatively charged”}, wherein the at least one dielectric region is a “heterogeneous” dielectric region such that said heterogeneous dielectric region including, in at least one first given direction dl (left to right direction in Figure 1) parallel to a main plane of the substrate, an alternation of first areas made of a first dielectric material with positive fixed charges (one of 20 and 120- see para 24} , and of second dielectric areas made of a second dielectric material (the other one of 20 and 120 – see para 24} with negative fixed charges (note that para 25 discloses material of 20 may be “silicon nitride” and that of 120 may be “aluminum oxide”), such that the first dielectric area is in contact with second dielectric area (i.e. 20 and 120 are adjacent and contact each other – see Figure 1).
It would have been obvious to one of ordinary skills in the art at the time of the effective filing of the claimed invention to modify Englekirk so that the at least one dielectric region is a “heterogeneous” dielectric region, such that “said heterogeneous dielectric region including, in at least one first given direction dl parallel to a main plane of the substrate, an alternation of first areas made of a first dielectric material with positive fixed charges and of second dielectric areas made of a second dielectric material with negative fixed charges”; and to use known dielectric materials (such as “silicon nitride” and “aluminum oxide” as noted above, which are also recited in claims 3-4) for the first areas and the second dielectric areas, such that the first dielectric area is in contact with second dielectric area. The ordinary artisan would have been motivated to modify Englekirk for at least the purpose of using known dielectric materials combination with fixed charges for creating a device configuration having FDSOI transistors with different voltage thresholds by using different dielectric materials below the FDSOI channel (see para 21 of Cheng; also see para 5 and 7 of Cheng).
Regarding claim 2, Englekirk (as modified for claim 1 in view of Cheng) teaches the device according to claim 1, said first (20) and second (120) dielectric areas being distributed periodically (i.e. for every two transistors) in said first direction (i.e. left to right direction in Figure 1 of Cheng, as explained in rejection of claim 1)
Regarding claim 3, Englekirk (as modified for claim 1 in view of Cheng) teaches the device according to claim 1, wherein said dielectric region includes, in at least one second direction (such as direction into plane of paper in orientation of Figure 1 of Cheng) making a non-zero angle (i.e. 90 degree angle) with the first direction (i.e. left to right direction in Figure 1 of Cheng, as explained in rejection of claim 1) and parallel to a main plane of the insulating layer (20, 120), an alternation of areas based on the first dielectric material (20) and dielectric areas based on the second dielectric material (120). This follows because 20 and 30 are 3-dimensional structures and as such, also extend in the direction of plane of paper in orientation of Figure 1 of Cheng.
Regarding claim 4, Englekirk (as modified for claim 1 in view of Cheng) teaches the device according to claim 1, wherein the first dielectric material with positive fixed charges {i.e. 20 of Cheng, as explained for claim 1} is selected from the following materials: silicon oxide, silicon nitride, silicon oxycarbide (as noted for claim 1, para 25 discloses material of 20 may be “silicon nitride”).
Regarding claim 5, Englekirk (as modified for claim 1 in view of Cheng) teaches the device according to claim 1, wherein the second dielectric material with negative fixed charges {i.e. 120 of Cheng, as explained for claim 1} is selected from the following materials: alumina, hafnium oxide (as noted for claim 1, para 25 discloses material of 120 may be “aluminum oxide”; i.e. alumina).
Regarding claim 6 (to the extent it reads on Figure 5 - see note about withdrawn claim 6 under restriction requirement), Englekirk teaches the device according to claim 1, wherein said substrate is: a semiconductor bulk substrate or, a semiconductor-on-insulator type substrate {see “SOI wafer 600” in para 83 of Englekirk; note that Cheng discloses "semiconductor-on-insulator" in para 52, especially last sentence}, said semiconductor region being a surface semiconductor layer disposed on an insulating layer {406 of Figure 6B of Englekirk} of the substrate {600 of Figure 6B of Englekirk}, said insulating layer being arranged on a semiconductor support layer {402 and 404 of Figure 6B of Englekirk; see para 83} of the substrate, or {i.e. remainder of the claim limitations are optional and not required – also see comment under “Election/Restrictions” heading}a hybrid substrate, said semiconductor region being a semiconductor island arranged on a first region of a semiconductor support layer of the hybrid substrate, the semiconductor support layer including a second region on which an insulating layer itself coated with a surface semiconductor layer are disposed.
Regarding claim 7, Englekirk teaches the device according to claim 6, wherein the substrate {600 of Figure 6B of Englekirk} is of the semiconductor-on-insulator type {see “SOI wafer 600” in para 83 of Englekirk} and wherein the semiconductor support layer {402 and 404 of Figure 6B of Englekirk} includes a charge trapping region {404, described as " trap rich layer 404" in para 83 of Englekirk; also see para 16-17}, in particular a region rich in crystalline defects, such as a polysilicon layer.
Regarding claim 9, Englekirk teaches the device according to claim 7, wherein the semiconductor support layer {comprising 404} is a polysilicon layer {para 17 describes “trap rich layer 404 is typically formed as a layer of amorphous or polycrystalline silicon"}.
Regarding claim 10, Englekirk teaches the device according to claim 1, wherein the dielectric region {406} is arranged on and in contact with said semiconductor region {either 402 and 404; or 408 – also see 35 USC 112, 2nd paragraph rejection above}.
Regarding claim 11, Englekirk (as modified for claim 1 in view of Cheng) teaches the device according to claim 1, wherein the first dielectric areas made of dielectric material with positive fixed charges and the dielectric areas made of dielectric material with negative fixed charges {20 and 120 of Figure 1 of Cheng, as explained for claim 1} are in contact with {best seen in Figure 1 of Cheng and as also addressed in claim 1} each other.
Claims 8 rejected under 35 U.S.C. 103 as being unpatentable over Englekirk and Cheng, as applied to claim 7 above, and further in view of Ito (US 20240063224), hereinafter Ito.
Regarding claim 8, Englekirk teaches the device according to claim 7, wherein the semiconductor support layer {402 and 404 – see Figure 6B of Englekirk} is a region that is trap rich {layer 404 is described as “trap rich layer 404” in para 83}. Whereas Englekirk teaches that the semiconductor support layer is trap rich (as noted above), Englekirk does not specifically state that trap rich layer is due to being “rich in crystalline defects”.
Ito (US 20240063224) teaches a microelectronic device further teaching that it is known in the art that crystal defects act as trap sites (para 9) and that it is known for charge trap layer to be designed with higher crystal defect density (para 38). It would have been obvious to one of ordinary skills in the art at the time of the effective filing of the claimed invention to modify Englekirk so t that trap rich layer is due to being rich in crystalline defects. The ordinary artisan would have been motivated to modify Englekirk for at least the purpose of using a known method of increasing charge trap site density by increasing crystal defects (para 9 of Ito).
Conclusion
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/AJAY ARORA/Primary Examiner, Art Unit 2892
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