CTNF 18/337,601 CTNF 100840 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions 08-06 AIA Claim s 28 and 30-33 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species (B) and Modifications (C2 and C3) , there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 23 December 2025 . 08-25-01 AIA Applicant’s election without traverse of Species A, Modification C1 in the reply filed on 23 December 2025 is acknowledged. Priority 02-26 AIA Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) submitted on 20 June 2023 has been considered by the examiner and made of record in the application file. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claim 21 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 21 recites the limitation "the first connecting signal line" in line 14 of the claim. There is insufficient antecedent basis for this limitation in the claim. Line 13 of claim 21 recited “a plurality of first connecting signal lines” but fails to distinctly point out which of the plurality of first connecting signal lines comprises “the first connecting signal line”. For the purpose of examination, the Examiner will interpret “the first connecting signal line” as “a first connecting signal line of the plurality of connecting signal lines”. Claims 22-27, 29 and 34-35 are rejected due to their dependence on claim 21. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15 AIA Claim s 21, 29 and 34-35 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Fuyang Zhang (CN 110288943 A relying upon US 20210408145 A1 for English translation; hereinafter “Zhang”) . Regarding Claim 21 , Zhang teaches an array substrate (Fig. 1 and Fig. 4, para [0053] describes a display panel 10 including a substrate upon which active regions comprising pixel units are disposed in an array shape) comprising a hole region (13, Fig. 1, para [0044] describes a non-display area 13 in the shape of a circle comprising a hole region) and a display region (11 and 12, Fig. 1, para [0043] describes display areas 11 and 12), wherein the display region comprises a winding display region (12, Fig. 1, para [0043] describes a second display area 12) and a main display region (11, Fig. 1, para [0043] describes a first display area 11), the winding display region is located between the hole region and the main display region (12, Fig. 1, para [0045] describes wherein the winding display region 12 surrounds the hole region 13 and the main display area 11 surrounds the winding display region 12), and the winding display region surrounds the hole region (12, Fig. 1, para [0045] describes wherein the winding display region 12 surrounds the hole region 13); wherein the array substrate comprises: a plurality of first pixel circuits distributed in an array in the winding display region (15, Fig. 2, para [0043] describes a second pixel unit 15, herein first pixel unit, distributed in an array in the winding display region 12); a plurality of second pixel circuits distributed in an array in the main display region (14, Fig. 2, para [0043] describes a first pixel unit 14, herein second pixel unit, distributed in an array in the main display region 11); a plurality of first signal lines (17, Fig. 2, para [0049] describes data lines 17 facilitating electrical signals), wherein each of the first signal lines is electrically connected to the first pixel circuit and the second pixel circuit (17, Fig. 3, para [0051] describes wherein the first signal lines 17 are connected to a second source of the first pixel unit 15 and para [0052] describes wherein a circuit structure of the second pixel unit 14 may be the same as the first pixel unit 15 wherein a resulting same structure would put first signal lines 17 and second pixel unit 14 in electrical connection) and extends along a first direction (17, Fig. 2, para [0050] describes wherein first signal lines 17 extend along a first direction F1), the plurality of first signal lines comprise a plurality of first type signal lines (FTSL, annotated Fig. 2 depicts first type signal lines FTSL which do not intersect the winding display region 12) and a plurality of second type signal lines (STSL, annotated Fig. 2 depicts second type signal lines STSL which do intersect the winding display region 12), and each of the second type signal lines comprises a first segment (FG, annotated Fig. 2 depicts a first segment FG on a first side of the hole region 13) and a second segment separated by the hole region (SG, annotated Fig. 2 depicts a second segment SG separated from the first segment FG by the hole region 13); a plurality of first connecting signal lines (16, Fig. 2, para [0047] describes a plurality of scan signal lines 16), wherein at least a part of the first connecting signal lines are located in the winding display region (16, Fig. 2, para [0048] describes scan signal lines 16 being disposed in the winding display region 12), the first connecting signal line (16) comprises a first connecting segment (FCS, annotated Fig. 2 II depicts a first connecting segment FCS), a second connecting segment (SCS, annotated Fig. 2 II depicts a second connecting segment SCS) and a third connecting segment connected with each other (TCS, annotated Fig. 2 II depicts a third connecting segment TCS wherein the first connecting segment FCS, second connecting segment SCS and third connecting segment TCS are connected with each other), the first connecting segment is electrically connected to the first segment (FCS and FG, annotated Fig. 2, annotated Fig. 2 II and Fig. 3, para [0052] describes wherein the first signal lines 17 comprising the first segment FG and first connecting signal lines 16 comprising first connecting segment FCS are electrically connected through a first transistor T1, second transistor T2 and capacitor structure of the pixel units), the third connecting segment is electrically connected to the second segment (SCS and SG, annotated Fig. 2, annotated Fig. 2 II and Fig. 3, para [0052] describes wherein the first signal lines 17 comprising the second segment SG and first connecting signal lines 16 comprising third connecting segment TCS are electrically connected through a first transistor T1, second transistor T2 and capacitor structure of the pixel units), and the second connecting segment is connected between the first connecting segment and the third connecting segment (SCS, annotated Fig. 2 II depicts the second connecting segment connected between the first connecting segment FCS and third connecting segment TCS), wherein the first connecting segment and the third connecting segment extend in a second direction (FCS and TCS, annotated Fig. 2 II depicts wherein first connecting segment FCS and third connecting segment TCS extend in a second direction F2), and the second connecting segment extends in the first direction (SCS, annotated Fig. 2 II depicts wherein second connecting segment SCS extends in the first direction F1 and second direction F2); wherein an area of an orthographic projection of the first pixel circuit on a plane where the array substrate is located is smaller than an area of an orthographic projection of the second pixel circuit on the plane where the array substrate is located (14 and 15, Fig. 2, para [0043] describes wherein an area of the first pixel circuit 15 is less than an area of the second pixel unit 14 wherein said area is an orthographic projection on the plane where the array substrate is located as shown in Fig. 2), and an orthographic projection of the first connecting signal line on the plane where the array substrate is located does not overlap with the orthographic projection of the first pixel circuit on the plane where the array substrate is located (16 and 15, annotated Fig. 2 II and Fig. 3 depicts wherein first connecting signal line 16 does not overlap with the orthographic projection of the first pixel circuit on the plane of the array substrate as shown in Fig. 2 and Fig. 3 further depicts wherein first connecting signal line 16 does not overlap with the first pixel unit circuitry). PNG media_image1.png 632 630 media_image1.png Greyscale PNG media_image2.png 592 739 media_image2.png Greyscale Regarding Claim 29 , Zhang teaches the array substrate according to claim 21, wherein the first direction is a column direction (F1, Fig. 2 depicts the first direction F1 running vertically in a column direction), the second direction is a row direction (F2, Fig. 2 depicts the second direction F2 running horizontally in a row direction), and the first signal line is a data signal line (17, Fig. 2, para [0047] describes wherein first signal lines 17 are data signal lines). Regarding Claim 34 , Zhang teaches the display panel comprising the array substrate according to claim 21 (10, Fig. 1 and Fig. 2, para [0047] describes a display panel 10 comprising the array substrate comprising pixel units disposed in an array on the substrate as described in para [0053]). Regarding Claim 35 , Zhang teaches the display device comprising the display panel according to claim 34 (para [0041] describes wherein the display panel 10 of the present application can be applied in various display devices) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Fuyang Zhang (CN 110288943 A relying upon US 20210408145 A1 for English translation; hereinafter “Zhang”) in view of Ya-na Gao et al. (CN 109713024 A; hereinafter “Gao”) . Regarding Claim 22 , Zhang discloses all the limitations of claim 21. Zhang discloses the array substrate according to claim 21, wherein a circuit structure of the first pixel circuit is the same as a circuit structure of the second pixel circuit (para [0052] describes wherein a circuit structure of the first pixel unit 15 may be a same circuit structure as the second pixel unit 14), and the first pixel circuit and the second pixel circuit each comprise at least one transistor (T1 and T2, Fig. 3, para [0051] describes wherein the circuit structure of the first pixel structure 15 and second pixel structure 14 may comprise transistors T1 and T2). Zhang fails to explicitly disclose the array substrate according to claim 21, wherein a size of the at least one transistor in the first pixel circuit is smaller than a size of the at least one transistor, at a same connecting position as the at least one transistor in the first pixel circuit, in the second pixel circuit. However, Gao teaches a similar array substrate, wherein a size of the at least one transistor in the first pixel circuit (PX1, Fig. 2, page 5 of the PE2E English machine translation describes a first pixel circuit PX1 in a winding display region D1) is smaller than a size of the at least one transistor, at a same connecting position as the at least one transistor in the first pixel circuit, in the second pixel circuit (PX2, Fig. 2, page 5 of the PE2E English machine translation describes a second pixel circuit PX2 in a second display area D2, wherein the first pixel circuit PX1 comprises a first switching transistor T1 in a same location of a second switching transistor T2 of the second pixel circuit PX2 as shown in Fig. 3, wherein page 5 of the PE2E English machine translation describes the channel area of the first transistor T1 is smaller than a channel region of the second transistor T2). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Zhang with Gao to further disclose an array substrate wherein a first pixel circuit comprises a first transistor smaller than a transistor of the a second pixel circuit comprising a second transistor in a same location of the first transistor in the circuit design in order to provide the advantage of reducing a transistor size in a pixel circuit that requires a smaller pixel circuit total area increasing the likelihood of success of producing a smaller first pixel unit in a winding display region than a second pixel unit in a surrounding main display region as required by the design features of the invention (Gao, page 4 and page 5 of the PE2E English machine translation). Regarding Claim 23 , the combination of Zhang and Gao discloses all the limitations of claim 22. The combination of Zhang and Gao discloses the array substrate according to claim 22, wherein a spacing between two adjacent ones of the first signal lines in the winding display region is smaller than a spacing between two adjacent ones of the first signal lines in the main display region (17, Fig. 2, para [0049] describes wherein an arrangement distance of the plurality of first signal lines in the winding display region 12 is less than an arrangement distance of the plurality of first signal lines in the main display region 11). The combination of Zhang and Gao fails to explicitly disclose the array substrate according to claim 22, wherein a line width of the first signal line in the winding display region is smaller than a line width of the first signal line in the main display region. However, Zhang does disclose wherein the first signal line in the winding display region has a smaller distance between adjacent first signal lines than first signal lines in the main display region (para [0049). Additionally, Zhang discloses wherein the first pixel circuits in the winding display region have a smaller area than the second pixel circuits in the main display region in order to increase the display ratio of the display panel by ensuring full utilization at a boundary between the winding display region and the hole region and the winding display region and main display region (para [0043]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to apply a known technique to a known device, such as reducing a width of a first signal line in a winding display region resulting in a width of a first signal line in a winding display region being smaller than a line width of the first signal line a main display region, to yield the predictable result of aid in increasing the distance between first signal lines in the winding display region and further enable first pixel circuits to comprise a smaller area in the winding display region providing the advantage of ensuring full utilization at a boundary between the winding display region and the hole region and the winding display region and main display region (Zhang, para [0043], see MPEP 2143(D)) . 07-21-aia AIA Claim s 24-26 are rejected under 35 U.S.C. 103 as being unpatentable over Fuyang Zhang (CN 110288943 A relying upon US 20210408145 A1 for English translation; hereinafter “Zhang”) in view of Zhao-Tai Sun et al. (CN 109541867 A; hereinafter “Sun”) . Regarding Claim 24 , Zhang discloses all the limitations of claim 21. Zhang fails to explicitly disclose the array substrate according to claim 21, wherein the hole region has a center line in the second direction, the smaller a vertical distance in the second direction between the second type signal line and the center line, the smaller a vertical distance in the second direction between the center line and the second connecting segment electrically connected to the second type signal line; and the smaller the vertical distance in the second direction between the second type signal line and the center line, the smaller two vertical distances in the second direction respectively between the center line and the first connecting segment electrically connected to the second type signal line and between the center line and the third connecting segment electrically connected to the second type signal line. However, Sun teaches a similar array substrate, wherein the hole region (b, Fig. 2, page 4 of the PE2E English machine translation describes a hole region b) has a center line in the second direction (C, annotated Fig. 2 depicts a center line C in a second Y direction), the smaller a vertical distance in the second direction between the second type signal line (2322, Fig. 2, page 4 of the PE2E English machine translation describes a second data line 2322) and the center line, the smaller a vertical distance in the second direction between the center line and the second connecting segment (242, Fig. 2, page 5 of the PE2E English machine translation describes a second data line connecting segment 242) electrically connected to the second type signal line (annotated Fig. 2 depicts wherein as a vertical distance in the second Y direction is decreased between a second type signal 2322 and the center line C, a resulting vertical distance between the center line C and second connecting segment 242 electrically connected to the type signal line 2322 is decreased); and the smaller the vertical distance in the second direction (Y) between the second type signal line (2322) and the center line (C), the smaller two vertical distances in the second direction respectively between the center line (C) and the first connecting segment electrically connected to the second type signal line (241, Fig. 2, page 5 of the PE2E machine translation describes a first data line connecting part 241 electrically connected to the second type signal line 2322) and between the center line and the third connecting segment electrically connected to the second type signal line (243, Fig. 2, page 5 of the PE2E machine translation describes a third data line connecting part 243 electrically connected to the second type signal line 2322 wherein as a vertical distance in the second Y direction is decreased between a second type signal 2322 and the center line C, a vertical distance between the first connecting segments 241 and the center line C in a second Y direction and a vertical distance between the third connecting segments 243 and the center line C in a second Y direction are decreased). PNG media_image3.png 648 563 media_image3.png Greyscale Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Zhang with Sun to further disclose an array substrate wherein a hole region comprises a center line in a second direction and as a vertical distance from the center line in the second direction decreases from a second type signal line so does a resulting first, second and third connecting segments in order to provide the advantage of providing adequate and equal spacing between signal lines in a device in order to reduce the mutual interference between the signals and improve the display stability of the display panel (Sun, page 4 and page 5 of the PE2E English machine translation). Regarding Claim 25 , the combination of Zhang and Sun disclose all the limitations of claim 24. Zhang discloses the array substrate according to claim 24, wherein the first pixel circuits arranged along the second direction in an interval between every two adjacent ones of the second connecting segments on a same side of the hole region have the same number (Zhang, annotated Fig. 2 II depicts wherein the first pixel circuits 15 arranged along the second direction F2 in an interval between every two adjacent ones of the second connecting segments SCS on a same side of the hole region 13 have a same number as the grid of pixel units is symmetric in the winding display region 12), and the number of the first pixel circuits arranged along the first direction in an interval between two adjacent ones of the first connecting segments is equal to the number of the first pixel circuits arranged along the first direction in an interval between two adjacent ones of the third connecting segments (Zhang, annotated Fig. 2 II depicts wherein the first pixel circuits 15 arranged along the first direction F1 in an interval between every two adjacent ones of the first connecting segments FCS is equal to the number of first pixel circuits 15 arranged along the first direction F1 in an interval between every two adjacent ones of the third connecting segments TCS as the grid of pixel units is symmetric in the winding display region 12). Zhang fails to disclose wherein on a same side of the hole region, the number of the first pixel circuits arranged along the second direction in the interval between two adjacent ones of the second connecting segments is equal to twice the number of the first pixel circuits arranged along the first direction in the interval between two adjacent ones of the first connecting segments. However, the combination of Zhang and Sun discloses wherein on a same side of the hole region (Sun, b, Fig. 2, page 4 of the PE2E English machine translation describes a hole region b), the number of the first pixel circuits arranged along the second direction in the interval between two adjacent ones of the second connecting segments (Sun, 242, Fig. 2, page 5 of the PE2E English machine translation describes a second data line connecting segment 242 wherein Sun fails to explicitly disclose pixel units disposed in each of the grids of signal lines, however upon combining Zhang with Sun a first pixel circuit 15 as found in Zhang, would be disposed between the grids of signal lines 23 and 24 resulting in a number of first pixel circuits arranged along a second direction X between second two adjacent ones of the second connecting segments 242) is equal to twice the number of the first pixel circuits arranged along the first direction in the interval between two adjacent ones of the first connecting segments (FP6 and FP3, annotated Fig. 2 II from Sun depicts wherein upon combining the first pixel units of Zhang with Sun, a number of first pixel circuits FP6 between adjacent second connecting segments 242 on a same side of a hole region b may be double the number of first pixel circuits FP3 between adjacent first connecting segments 241). PNG media_image4.png 639 749 media_image4.png Greyscale Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Zhang with Sun to further disclose an array substrate wherein a number of first pixel circuits between adjacent second connecting segments is double a number of first pixel circuits among adjacent first connecting segments in order to provide the well-known advantage of producing a symmetric display region with equal coverage of display units in a first direction and a second direction avoiding gaps in display which would result in a lower quality and less efficient display panel. Regarding Claim 26 , the combination of Zhang and Sun disclose the array substrate according to claim 25, wherein the first pixel circuits arranged along the second direction in the interval between two adjacent ones of the second connecting segments are adjacent to each other (Zhang, 15 and SCS, annotated Fig. 2 II depicts wherein first pixel circuits 15 arranged along the second direction F2 in the interval between two adjacent one of the second connecting segments SCS are adjacent to each other) . 07-21-aia AIA Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over Fuyang Zhang (CN 110288943 A relying upon US 20210408145 A1 for English translation; hereinafter “Zhang”) in view of Yang-zhao Ma. (CN 109637372 A; hereinafter “Ma”) . Regarding Claim 27 , Zhang discloses all the limitations of claim 21. Zhang fails to explicitly disclose the array substrate according to claim 21, wherein the second connecting segment and the first signal line are disposed in a same layer and of a same material, and the first connecting segment is located in a film layer different from the first signal line, and the third connecting segment is located in a film layer different from the first signal line. However, Ma teaches a similar array substrate, wherein the second connecting segment (72, Fig. 2, page 4 of the PE2E English machine translation describes a plurality of data lines 70 wherein a portion of a second data line has a connecting segment in a winding display region 21 that extends in a first direction wherein said segment comprises a second connecting segment in the winding display region 21) and the first signal line (71, Fig. 2, page 4 of the PE2E English machine translation describes a plurality of data lines 70 wherein a first data line 71 extends in a first direction) are disposed in a same layer and of a same material (71 and 72, page 4 and page 5 of the PE2E English machine translation describes wherein portions of the first signal line 71 and second signal line 72 extending along a same first direction, wherein the second connecting segment is the portion of the second signal line 72 extending along the same first direction as the first signal line 71, may be formed in the same process and the same film layer resulting in a first signal line 71 and second connecting portion 72 disposed in a same layer and of a same material), and the first connecting segment (72, Fig. 2, page 4 of the PE2E English machine translation describes a plurality of data lines 70 wherein a portion of a second data line has a first connecting segment in a winding display region 21 that extends in a second direction wherein said segment comprises a first connecting segment in the winding display region 21) is located in a film layer different from the first signal line (71 and 72, page 4 and page 5 of the PE2E English machine translation describes wherein portions of the first signal line 71 and second signal line 72 extending along different directions, wherein the first connecting segment is a portion of the second signal line 72 extending along the second direction different from the first direction of the first signal line 71, may be formed in different film layers), and the third connecting segment (72, Fig. 2, page 4 of the PE2E English machine translation describes a plurality of data lines 70 wherein a portion of a second data line has a second connecting segment in a winding display region 21 that extends in a second direction wherein said segment comprises a third connecting segment in the winding display region 21) is located in a film layer different from the first signal line (71 and 72, page 4 and page 5 of the PE2E English machine translation describes wherein portions of the first signal line 71 and second signal line 72 extending along different directions, wherein the third connecting segment is a portion of the second signal line 72 extending along the second direction different from the first direction of the first signal line 71, may be formed in different film layers). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Zhang with Ma to further disclose an array substrate wherein a portion of a second connecting segment and first signal line extending along a same first direction may be formed in a same layer and of a same material and further wherein a first connecting and third connecting segment extending in a second direction different from a first signal line direction may be formed in a different film layer in order to provide the advantage of forming similar direction signal lines in a single process improving production efficiency and cost savings in a production process of a display panel (Ma, page 5 of the PE2E English machine translation). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER M MILLER whose telephone number is (571)272-6051. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ALEXANDER MICHAEL MILLER/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898 Application/Control Number: 18/337,601 Page 2 Art Unit: 2898 Application/Control Number: 18/337,601 Page 3 Art Unit: 2898 Application/Control Number: 18/337,601 Page 4 Art Unit: 2898 Application/Control Number: 18/337,601 Page 5 Art Unit: 2898 Application/Control Number: 18/337,601 Page 6 Art Unit: 2898 Application/Control Number: 18/337,601 Page 7 Art Unit: 2898 Application/Control Number: 18/337,601 Page 8 Art Unit: 2898 Application/Control Number: 18/337,601 Page 9 Art Unit: 2898 Application/Control Number: 18/337,601 Page 10 Art Unit: 2898 Application/Control Number: 18/337,601 Page 11 Art Unit: 2898 Application/Control Number: 18/337,601 Page 12 Art Unit: 2898 Application/Control Number: 18/337,601 Page 13 Art Unit: 2898 Application/Control Number: 18/337,601 Page 14 Art Unit: 2898 Application/Control Number: 18/337,601 Page 15 Art Unit: 2898