DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 10-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cho (US 6,153,928).
With respect to claim 1, Cho discloses, Figs.2A-6, a method comprising: attaching a first semiconductor die (30) to a first die pad (20) of a first leadframe (42); attaching a second semiconductor die (31) to a second die pad (20) of a second leadframe (42); attaching the first leadframe (42) to the second leadframe (42) by way of a non-conductive adhesive (10) such that leads of a first plurality of leads (12a) of the first leadframe are interleaved/(merge together and bend away outside encapsulant) with leads of a second plurality of leads (12b) of the second leadframe (42) (see col.5 lines 65-67 and col.6 lines 1-10 wherein for connecting each of the corresponding first and second conductive lines 12a, 12b, 14a, 14b, through-holes are formed in the upper and lower second insulating layers 10b, 10c, so that the first upper and lower conductive lines 12a, 12b are exposed; the through-holes are filled with a conductive metal 42 (such as aluminum, lead, copper or tungsten), which electrically connects the first conductive lines 12a, 12b with the corresponding second conductive lines 14a, 14b, respectively; see col.4 lines 1-40 wherein bonding layer of the insulator 10 is formed of a ceramic or a plastic insulating material); and encapsulating (50) with an encapsulant the first (30) and second (31) semiconductor die and portions of the first and second leadframes (42) (see col.6 lines 55-67 wherein epoxy moldings 50 for sealing the upper and lower semiconductor chips 30, 31, the third conductive lines 40 and the first upper and lower conductive lines 12a, 12b).
With respect to claim 2, Cho discloses, Figs.2A-6, the method, further comprising before encapsulating with the encapsulant: attaching a first end of a first bond wire (40) to a first bond pad of the first semiconductor die (30) and a second end of the first bond wire (40) to a first lead of the first plurality of leads (12a); and attaching a first end of a second bond wire (40) to a second bond pad of the second semiconductor die (31) and a second end of the second bond wire (40) to a second lead of the second plurality of leads (12b) (see col.6 lines 40-60 wherein as shown in FIG. 4C, using a third conductive line 40 as a medium, the pads (not shown) of the upper and lower semiconductor chips 30, 31 and the corresponding ones of the first upper and lower conductive lines 12a, 12b are electrically connected, respectively).
With respect to claim 3, Cho discloses, Figs.2A-6, the method, wherein the first lead of the first plurality of leads (12a) and the second lead of the second plurality of leads (12b) are electrically isolated from one another (see col.5 lines 65-67 and col.6 lines 1-10 wherein for connecting each of the corresponding first and second conductive lines 12a, 12b, 14a, 14b, through-holes are formed in the upper and lower second insulating layers 10b, 10c, so that the first upper and lower conductive lines 12a, 12b are exposed; the through-holes are filled with a conductive metal 42 (such as aluminum, lead, copper or tungsten), which electrically connects the first conductive lines 12a, 12b with the corresponding second conductive lines 14a, 14b, respectively; see col.4 lines 1-40 wherein bonding layer of the insulator 10 is formed of a ceramic or a plastic insulating material).
With respect to claim 4, Cho discloses, Figs.2A-6, the method, wherein attaching the first leadframe (42) to the second leadframe (42) by way of the non-conductive adhesive (10) further includes attaching a backside of the first die pad (20) of the first leadframe (42) to a backside of the second die pad (20) of the second leadframe (42) by way of the non-conductive adhesive (10) (see col.5 lines 65-67 and col.6 lines 1-10 wherein for connecting each of the corresponding first and second conductive lines 12a, 12b, 14a, 14b, through-holes are formed in the upper and lower second insulating layers 10b, 10c, so that the first upper and lower conductive lines 12a, 12b are exposed; the through-holes are filled with a conductive metal 42 (such as aluminum, lead, copper or tungsten), which electrically connects the first conductive lines 12a, 12b with the corresponding second conductive lines 14a, 14b, respectively; see col.4 lines 1-40 wherein bonding layer of the insulator 10 is formed of a ceramic or a plastic insulating material).
With respect to claim 5, Cho discloses, Figs.2A-6, the method, wherein attaching the first leadframe (42) to the second leadframe (42) by way of the non-conductive adhesive (10) further includes attaching a backside of the first die pad (20) of the first leadframe (42) to a backside of the second die pad of the second leadframe by way of the non-conductive adhesive (10) (see col.5 lines 65-67 and col.6 lines 1-10 wherein for connecting each of the corresponding first and second conductive lines 12a, 12b, 14a, 14b, through-holes are formed in the upper and lower second insulating layers 10b, 10c, so that the first upper and lower conductive lines 12a, 12b are exposed; the through-holes are filled with a conductive metal 42 (such as aluminum, lead, copper or tungsten), which electrically connects the first conductive lines 12a, 12b with the corresponding second conductive lines 14a, 14b, respectively; see col.4 lines 1-40 wherein bonding layer of the insulator 10 is formed of a ceramic or a plastic insulating material).
With respect to claim 6, Cho discloses, Figs.2A-6, the method, wherein the non-conductive adhesive (10) is characterized as a non-conductive die attach film (DAF) (see col.5 lines 65-67 and col.6 lines 1-10 wherein for connecting each of the corresponding first and second conductive lines 12a, 12b, 14a, 14b, through-holes are formed in the upper and lower second insulating layers 10b, 10c, so that the first upper and lower conductive lines 12a, 12b are exposed; the through-holes are filled with a conductive metal 42 (such as aluminum, lead, copper or tungsten), which electrically connects the first conductive lines 12a, 12b with the corresponding second conductive lines 14a, 14b, respectively; see col.4 lines 1-40 wherein bonding layer of the insulator 10 is formed of a ceramic or a plastic insulating material).
With respect to claim 10, Cho discloses, Figs.2A-6, a semiconductor device comprising: a first leadframe (14a) including a first die pad (20) and a first plurality of leads (14a); a first semiconductor die (30) attached to the first die pad (20) of the first leadframe (14a); a second leadframe (14b) including a second die pad (20) and a second plurality of leads (14b), the first leadframe (14a) attached to the second leadframe (14b) by way of a non-conductive adhesive (10) such that leads of the first plurality of leads (14a) are interleaved with leads of the second plurality of leads (14b); a second semiconductor die (31) attached to the second die pad (20) of the second leadframe (14b); and an encapsulant (50) encapsulating the first (30) and second (31) semiconductor die and portions of the first (14a) and second (14b) leadframes (see col.5 lines 65-67 and col.6 lines 1-10 wherein for connecting each of the corresponding first and second conductive lines 12a, 12b, 14a, 14b, through-holes are formed in the upper and lower second insulating layers 10b, 10c, so that the first upper and lower conductive lines 12a, 12b are exposed; the through-holes are filled with a conductive metal 42 (such as aluminum, lead, copper or tungsten), which electrically connects the first conductive lines 12a, 12b with the corresponding second conductive lines 14a, 14b, respectively; see col.4 lines 1-40 wherein bonding layer of the insulator 10 is formed of a ceramic or a plastic insulating material); and encapsulating (50) with an encapsulant the first (30) and second (31) semiconductor die and portions of the first and second leadframes (42) (see col.6 lines 55-67 wherein epoxy moldings 50 for sealing the upper and lower semiconductor chips 30, 31, the third conductive lines 40 and the first upper and lower conductive lines 12a, 12b).
With respect to claim 11, Cho discloses, Figs.2A-6, the semiconductor device, further comprising: a first bond wire (40) having a first end attached to a first bond pad of the first semiconductor die (30) and a second end attached to a first lead of the first plurality of leads (14a); and a second bond wire (40) having a first end attached to a second bond pad of the second semiconductor die (31) and a second end attached to a second lead of the second plurality of leads (14b) (see col.6 lines 40-60 wherein as shown in FIG. 4C, using a third conductive line 40 as a medium, the pads (not shown) of the upper and lower semiconductor chips 30, 31 and the corresponding ones of the first upper and lower conductive lines 12a, 12b are electrically connected, respectively).
With respect to claim 12, Cho discloses, Figs.2A-6, the semiconductor device, wherein the first lead of the first plurality of leads (14a) and the second lead of the second plurality of leads (14b) are electrically isolated from one another (see col.5 lines 65-67 and col.6 lines 1-10 wherein for connecting each of the corresponding first and second conductive lines 12a, 12b, 14a, 14b, through-holes are formed in the upper and lower second insulating layers 10b, 10c, so that the first upper and lower conductive lines 12a, 12b are exposed; the through-holes are filled with a conductive metal 42 (such as aluminum, lead, copper or tungsten), which electrically connects the first conductive lines 12a, 12b with the corresponding second conductive lines 14a, 14b, respectively; see col.4 lines 1-40 wherein bonding layer of the insulator 10 is formed of a ceramic or a plastic insulating material).
With respect to claim 13, Cho discloses, Figs.2A-6, the semiconductor device, wherein the non-conductive adhesive (10) is disposed between a portion of the first plurality of leads of the first leadframe (14a) and a portion of the second plurality of leads of the second leadframe (14b) (see Fig.6; see col.5 lines 65-67 and col.6 lines 1-10 wherein for connecting each of the corresponding first and second conductive lines 12a, 12b, 14a, 14b, through-holes are formed in the upper and lower second insulating layers 10b, 10c, so that the first upper and lower conductive lines 12a, 12b are exposed; the through-holes are filled with a conductive metal 42 (such as aluminum, lead, copper or tungsten), which electrically connects the first conductive lines 12a, 12b with the corresponding second conductive lines 14a, 14b, respectively; see col.4 lines 1-40 wherein bonding layer of the insulator 10 is formed of a ceramic or a plastic insulating material).
With respect to claim 14, Cho discloses, Figs.2A-6, the semiconductor device, wherein the non-conductive adhesive (10) is further disposed between a backside of the first die pad (20) of the first leadframe (14a) and a backside of the second die pad (20) of the second leadframe (14b) (see Fig.6; see col.5 lines 65-67 and col.6 lines 1-10 wherein for connecting each of the corresponding first and second conductive lines 12a, 12b, 14a, 14b, through-holes are formed in the upper and lower second insulating layers 10b, 10c, so that the first upper and lower conductive lines 12a, 12b are exposed; the through-holes are filled with a conductive metal 42 (such as aluminum, lead, copper or tungsten), which electrically connects the first conductive lines 12a, 12b with the corresponding second conductive lines 14a, 14b, respectively; see col.4 lines 1-40 wherein bonding layer of the insulator 10 is formed of a ceramic or a plastic insulating material).
With respect to claim 15, Cho discloses, Figs.2A-6, the semiconductor device, wherein the first plurality of leads of the first leadframe (14a) and the second plurality of leads of the second leadframe (14b) are electrically isolated from one another (see col.5 lines 65-67 and col.6 lines 1-10 wherein for connecting each of the corresponding first and second conductive lines 12a, 12b, 14a, 14b, through-holes are formed in the upper and lower second insulating layers 10b, 10c, so that the first upper and lower conductive lines 12a, 12b are exposed; the through-holes are filled with a conductive metal 42 (such as aluminum, lead, copper or tungsten), which electrically connects the first conductive lines 12a, 12b with the corresponding second conductive lines 14a, 14b, respectively; see col.4 lines 1-40 wherein bonding layer of the insulator 10 is formed of a ceramic or a plastic insulating material).
With respect to claim 16, Cho discloses, Figs.2A-6, a method comprising: attaching a first semiconductor die (30) to a first die pad (20) of a first leadframe (14a); attaching a second semiconductor die (31) to a second die pad (20) of a second leadframe (14b); attaching a portion of a first plurality of leads of the first leadframe (14a) to a portion of a second plurality of leads of the second leadframe (14b) by way of a non-conductive adhesive (10), such that leads of the first plurality of leads (14a) are interleaved with leads of the second plurality of leads (14b); and encapsulating with an encapsulant (50) the first (30) and second (31) semiconductor die, portions of the first (14a) and second (14b) leadframes, and the non-conductive adhesive (10) (see col.5 lines 65-67 and col.6 lines 1-10 wherein for connecting each of the corresponding first and second conductive lines 12a, 12b, 14a, 14b, through-holes are formed in the upper and lower second insulating layers 10b, 10c, so that the first upper and lower conductive lines 12a, 12b are exposed; the through-holes are filled with a conductive metal 42 (such as aluminum, lead, copper or tungsten), which electrically connects the first conductive lines 12a, 12b with the corresponding second conductive lines 14a, 14b, respectively; see col.4 lines 1-40 wherein bonding layer of the insulator 10 is formed of a ceramic or a plastic insulating material; see col.6 lines 55-67 wherein epoxy moldings 50 for sealing the upper and lower semiconductor chips 30, 31, the third conductive lines 40 and the first upper and lower conductive lines 12a, 12b).
With respect to claim 17, Cho discloses, Figs.2A-6, the method, further comprising before encapsulating with the encapsulant: attaching a first end of a first bond wire (40) to a first bond pad of the first semiconductor die (30) and a second end of the first bond wire (40) to a first lead of the first plurality of leads (14a); and attaching a first end of a second bond wire (40) to a second bond pad of the second semiconductor die (31) and a second end of the second bond wire (40) to a second lead of the second plurality of leads (14b) (see col.6 lines 40-60 wherein as shown in FIG. 4C, using a third conductive line 40 as a medium, the pads (not shown) of the upper and lower semiconductor chips 30, 31 and the corresponding ones of the first upper and lower conductive lines 12a, 12b are electrically connected, respectively).
With respect to claim 18, Cho discloses, Figs.2A-6, the method, wherein the first lead of the first plurality of leads (14a) and the second lead of the second plurality of leads (14b) are electrically isolated from one another (see col.5 lines 65-67 and col.6 lines 1-10 wherein for connecting each of the corresponding first and second conductive lines 12a, 12b, 14a, 14b, through-holes are formed in the upper and lower second insulating layers 10b, 10c, so that the first upper and lower conductive lines 12a, 12b are exposed; the through-holes are filled with a conductive metal 42 (such as aluminum, lead, copper or tungsten), which electrically connects the first conductive lines 12a, 12b with the corresponding second conductive lines 14a, 14b, respectively; see col.4 lines 1-40 wherein bonding layer of the insulator 10 is formed of a ceramic or a plastic insulating material).
With respect to claim 19, Cho discloses, Figs.2A-6, the method, further comprising attaching a backside of the first die pad (20) of the first leadframe (14a) to a backside of the second die pad (20) of the second leadframe (14b) by way of the non-conductive adhesive (10) (see col.5 lines 65-67 and col.6 lines 1-10 wherein for connecting each of the corresponding first and second conductive lines 12a, 12b, 14a, 14b, through-holes are formed in the upper and lower second insulating layers 10b, 10c, so that the first upper and lower conductive lines 12a, 12b are exposed; the through-holes are filled with a conductive metal 42 (such as aluminum, lead, copper or tungsten), which electrically connects the first conductive lines 12a, 12b with the corresponding second conductive lines 14a, 14b, respectively; see col.4 lines 1-40 wherein bonding layer of the insulator 10 is formed of a ceramic or a plastic insulating material).
Claims 1-4, 6-7, 10-13, 15-18 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al. (US 2019/0172815 A1 hereinafter referred to as “Wang”).
With respect to claim 1, Wang discloses, in Figs.1A-16, a method comprising: attaching a first semiconductor die (110) to a first die pad (106) of a first leadframe (114); attaching a second semiconductor die (108) to a second die pad (112) of a second leadframe (112); attaching the first leadframe (114) to the second leadframe (112) by way of a non-conductive adhesive (120) such that leads of a first plurality of leads of the first leadframe (114) are interleaved/(merge together and bend away outside encapsulant) with leads of a second plurality of leads of the second leadframe (112); and encapsulating with an encapsulant (122) the first (110) and second (108) semiconductor die and portions of the first (114) and second (112) leadframes (see Par.[0015] wherein each leadframe assembly 100, 102 includes a die pad 104, 106 for attaching at least one semiconductor die 108, 110, and leads 112, 114 providing means for external electrical connection to the respective dies 108, 110; each die 108, 110 can be connected to the corresponding leads 112, 114 by wires 116, 118, e.g. through wire bonding or tape automated bonds; the semiconductor dies 108, 110 are attached to the respective die pads 104, 106 by a standard die attach material, and the wire bond connections 116, 118 are formed between the dies 108, 110 and the corresponding leads 112 114 to form the leadframe assemblies 100, 102; see Par.[0016]-[0018] wherein the spacer 120 is electrically insulative for the reasons explained above; preferably, but not necessarily, the spacer 120 is a good thermal conductor; some examples of the spacer material are an adhesive or a polymeric glob, film or paste with thermally conductive and electrically insulative fillers; the spacer 120 may comprises the same or different material than the mold compound 122; see Fig.6 wherein the interleave leads are shown).
With respect to claim 2, Wang discloses, in Figs.1A-16, the method, further comprising before encapsulating with the encapsulant: attaching a first end of a first bond wire (118) to a first bond pad of the first semiconductor die (110) and a second end of the first bond wire (116) to a first lead/(surface electrode) of the first plurality of leads (114); and attaching a first end of a second bond wire (116) to a second bond pad/(surface electrode) of the second semiconductor die (108) and a second end of the second bond wire to a second lead of the second plurality of leads (112) (see step of Figs.10B-10C, Par.[0038]-[0039] wherein bond wires are formed over surface (e.g.; on surface electrode) of dies before the attachment and encapsulation steps; the second dies can be connected to the corresponding groups of second leads 304 by electrical conductors such as wire bonds, metal clips, metal ribbons, etc; see step of Fig.11B, Par.[0043] wherein in FIG. 11B, the stacked arrangement of leadframe assemblies is placed in a standard molding tool 400 and subjected to a common molding process during which part of each first leadframe assembly 216, part of each second leadframe assembly attached to the intact leadframe strip 300, and the spacers 314 are embedded in a single mold compound 402).
With respect to claim 3, Wang discloses, in Figs.1A-16, the method, wherein the first lead of the first plurality of leads (114) and the second lead of the second plurality of leads (112) are electrically isolated from one another (see Fig.4, for example, wherein the leads 112, 114 are isolated from each other by spacer and/or mold; see Par.[0016]-[0018] wherein the spacer 120 is electrically insulative for the reasons explained above; preferably, but not necessarily, the spacer 120 is a good thermal conductor. Some examples of the spacer material are an adhesive or a polymeric glob, film or paste with thermally conductive and electrically insulative fillers; the spacer 120 may comprises the same or different material than the mold compound 122).
With respect to claim 4, Wang discloses, in Figs.1A-16, the method, wherein attaching the first leadframe (114) to the second leadframe (112) by way of the non-conductive adhesive (120) includes attaching a portion of the firstplurality of leads of the first leadframe (114) to a portion of the second plurality of leads of the second leadframe (112) by way of the non-conductive adhesive (120) (see Fig.4, for example, wherein the leads 112, 114 are isolated from each other by spacer and/or mold; see Par.[0016]-[0018] wherein the spacer 120 is electrically insulative for the reasons explained above; preferably, but not necessarily, the spacer 120 is a good thermal conductor. Some examples of the spacer material are an adhesive or a polymeric glob, film or paste with thermally conductive and electrically insulative fillers; the spacer 120 may comprises the same or different material than the mold compound 122).
With respect to claim 6, Wang discloses, in Figs.1A-16, he method of claim 1, wherein the non-conductive adhesive is characterized as a non-conductive die attach film (DAF) (see Fig.4, for example, wherein the leads 112, 114 are isolated from each other by spacer and/or mold; see Par.[0016]-[0018] wherein the spacer 120 is electrically insulative for the reasons explained above; preferably, but not necessarily, the spacer 120 is a good thermal conductor. Some examples of the spacer material are an adhesive or a polymeric glob, film or paste with thermally conductive and electrically insulative fillers; the spacer 120 may comprises the same or different material than the mold compound 122).
With respect to claim 7, Wang discloses, in Figs.1A-16, the method, wherein after encapsulating with the encapsulant (122) a backside of the first die pad (106) of the first leadframe (114) is exposed through the encapsulant (122) (see Figs.8 and steps of Figs.11D-11E, wherein the die pads are exposed after molding process).
With respect to claim 10, Wang discloses, in Figs.1A-16, a semiconductor device comprising: a first leadframe (114) including a first die pad (106) and a first plurality of leads (114); a first semiconductor die (110) attached to the first die pad (106) of the first leadframe (114); a second leadframe (112) including a second die pad (104) and a second plurality of leads (112), the first leadframe (114) attached to the second leadframe (112) by way of a non-conductive adhesive (120) such that leads of the first plurality of leads (114) are interleaved with leads of the second plurality of leads (112); a second semiconductor die (108) attached to the second die pad (106) of the second leadframe (112); and an encapsulant (122) encapsulating the first (110) and second (108) semiconductor die and portions of the first and second leadframes (114, 112) (see Par.[0015] wherein each leadframe assembly 100, 102 includes a die pad 104, 106 for attaching at least one semiconductor die 108, 110, and leads 112, 114 providing means for external electrical connection to the respective dies 108, 110; each die 108, 110 can be connected to the corresponding leads 112, 114 by wires 116, 118, e.g. through wire bonding or tape automated bonds; the semiconductor dies 108, 110 are attached to the respective die pads 104, 106 by a standard die attach material, and the wire bond connections 116, 118 are formed between the dies 108, 110 and the corresponding leads 112 114 to form the leadframe assemblies 100, 102; see Par.[0016]-[0018] wherein the spacer 120 is electrically insulative for the reasons explained above; preferably, but not necessarily, the spacer 120 is a good thermal conductor; some examples of the spacer material are an adhesive or a polymeric glob, film or paste with thermally conductive and electrically insulative fillers; the spacer 120 may comprises the same or different material than the mold compound 122; see Fig.6 wherein the interleave leads are shown).
With respect to claim 11, Wang discloses, in Figs.1A-16, the semiconductor device, further comprising: a first bond wire (118) having a first end attached to a first bond pad of the first semiconductor die (110) and a second end attached to a first lead of the first plurality of leads (114); and a second bond wire (116) having a first end attached to a second bond pad of the second semiconductor die (108) and a second end attached to a second lead of the second plurality of leads (112) (see step of Figs.10B-10C, Par.[0038]-[0039] wherein bond wires are formed over surface (e.g.; on surface electrode) of dies before the attachment and encapsulation steps; the second dies can be connected to the corresponding groups of second leads 304 by electrical conductors such as wire bonds, metal clips, metal ribbons, etc; see step of Fig.11B, Par.[0043] wherein in FIG. 11B, the stacked arrangement of leadframe assemblies is placed in a standard molding tool 400 and subjected to a common molding process during which part of each first leadframe assembly 216, part of each second leadframe assembly attached to the intact leadframe strip 300, and the spacers 314 are embedded in a single mold compound 402).
With respect to claim 12, Wang discloses, in Figs.1A-16, the semiconductor device, wherein the first lead of the first plurality of leads (114) and the second lead of the second plurality of leads (112) are electrically isolated from one another (see Fig.4, for example, wherein the leads 112, 114 are isolated from each other by spacer and/or mold; see Par.[0016]-[0018] wherein the spacer 120 is electrically insulative for the reasons explained above; preferably, but not necessarily, the spacer 120 is a good thermal conductor; some examples of the spacer material are an adhesive or a polymeric glob, film or paste with thermally conductive and electrically insulative fillers; the spacer 120 may comprises the same or different material than the mold compound 122).
With respect to claim 13, Wang discloses, in Figs.1A-16, the semiconductor device, wherein the non-conductive adhesive (120) is disposed between a portion of the first plurality of leads of the first leadframe (114) and a portion of the second plurality of leads of the second leadframe (112) (see Fig.4, for example, wherein the leads 112, 114 are isolated from each other by spacer and/or mold; see Par.[0016]-[0018] wherein the spacer 120 is electrically insulative for the reasons explained above; preferably, but not necessarily, the spacer 120 is a good thermal conductor; some examples of the spacer material are an adhesive or a polymeric glob, film or paste with thermally conductive and electrically insulative fillers; the spacer 120 may comprises the same or different material than the mold compound 122).
With respect to claim 15, Wang discloses, in Figs.1A-16, the semiconductor device, wherein the first plurality of leads of the first leadframe (114) and the second plurality of leads of the second leadframe (112) are electrically isolated from one another (see Fig.4, for example, wherein the leads 112, 114 are isolated from each other by spacer and/or mold; see Par.[0016]-[0018] wherein the spacer 120 is electrically insulative for the reasons explained above; preferably, but not necessarily, the spacer 120 is a good thermal conductor; some examples of the spacer material are an adhesive or a polymeric glob, film or paste with thermally conductive and electrically insulative fillers; the spacer 120 may comprises the same or different material than the mold compound 122).
With respect to claim 16, Wang discloses, in Figs.1A-16, a method comprising: attaching a first semiconductor die (110) to a first die pad (106) of a first leadframe (114); attaching a second semiconductor die (108) to a second die pad (104) of a second leadframe (112); attaching a portion of a first plurality of leads of the first leadframe (114) to a portion of a second plurality of leads of the second leadframe (112) by way of a non-conductive adhesive (120), such that leads of the first plurality of leads (114) are interleaved with leads of the second plurality of leads (112); and encapsulating with an encapsulant (122) the first (110) and second (108) semiconductor die, portions of the first and second leadframes (114, 112), and the non-conductive adhesive (120) (see Par.[0015] wherein each leadframe assembly 100, 102 includes a die pad 104, 106 for attaching at least one semiconductor die 108, 110, and leads 112, 114 providing means for external electrical connection to the respective dies 108, 110; each die 108, 110 can be connected to the corresponding leads 112, 114 by wires 116, 118, e.g. through wire bonding or tape automated bonds; the semiconductor dies 108, 110 are attached to the respective die pads 104, 106 by a standard die attach material, and the wire bond connections 116, 118 are formed between the dies 108, 110 and the corresponding leads 112 114 to form the leadframe assemblies 100, 102; see Par.[0016]-[0018] wherein the spacer 120 is electrically insulative for the reasons explained above; preferably, but not necessarily, the spacer 120 is a good thermal conductor; some examples of the spacer material are an adhesive or a polymeric glob, film or paste with thermally conductive and electrically insulative fillers; the spacer 120 may comprises the same or different material than the mold compound 122; see Fig.6 wherein the interleave leads are shown).
With respect to claim 17, Wang discloses, in Figs.1A-16, the method, further comprising before encapsulating with the encapsulant: attaching a first end of a first bond wire (118) to a first bond pad of the first semiconductor die (110) and a second end of the first bond wire (118) to a first lead of the first plurality of leads (114); and attaching a first end of a second bond wire (116) to a second bond pad of the second semiconductor die (108) and a second end of the second bond wire (116) to a second lead of the second plurality of leads (112) (see step of Figs.10B-10C, Par.[0038]-[0039] wherein bond wires are formed over surface (e.g.; on surface electrode) of dies before the attachment and encapsulation steps; the second dies can be connected to the corresponding groups of second leads 304 by electrical conductors such as wire bonds, metal clips, metal ribbons, etc; see step of Fig.11B, Par.[0043] wherein in FIG. 11B, the stacked arrangement of leadframe assemblies is placed in a standard molding tool 400 and subjected to a common molding process during which part of each first leadframe assembly 216, part of each second leadframe assembly attached to the intact leadframe strip 300, and the spacers 314 are embedded in a single mold compound 402).
With respect to claim 18, Wang discloses, in Figs.1A-16, the method, wherein the first lead of the first plurality of leads (114) and the second lead of the second plurality of leads (112) are electrically isolated from one another (see Fig.4, for example, wherein the leads 112, 114 are isolated from each other by spacer and/or mold; see Par.[0016]-[0018] wherein the spacer 120 is electrically insulative for the reasons explained above; preferably, but not necessarily, the spacer 120 is a good thermal conductor. Some examples of the spacer material are an adhesive or a polymeric glob, film or paste with thermally conductive and electrically insulative fillers; the spacer 120 may comprises the same or different material than the mold compound 122).
With respect to claim 20, Wang discloses, in Figs.1A-16, the method, further comprising exposing a backside of the first die pad of the first leadframe through a first major surface of the encapsulant (see Figs.8 and steps of Figs.11D-11E, wherein the die pads are exposed after molding process).
Claims 1-2, 4-5, 8-11, 13-14, 16-17, 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yoon (US 2009/0051021 A1).
With respect to claim 1, Yoon discloses, in Figs.2-4E, a method comprising: attaching a first semiconductor die (110uc) to a first die pad/(portion of 130u underlying 110uc) of a first leadframe (130u); attaching a second semiconductor die (110lc) to a second die pad/(portion of 130l underlying 110lc) of a second leadframe (130l) (see Par.[0023] wherein a semiconductor chip stack-type package may include a lead frame, semiconductor chip groups I, II, III and IV, wiring boards 130u and 130l, bonding wires 125ua, 125ub, 125uc, 125ud, 125la, 125lb, 125lc and 125ld, and a molded portion 140; see Par.[0025] wherein the second semiconductor chip group II may include a third upper semiconductor chip 110uc and a fourth upper semiconductor chip 110ud sequentially stacked on an upper wiring board 130u, the upper wiring board 130u being interposed between the first semiconductor chip group I and the second semiconductor chip group II; the fourth semiconductor chip group IV may include a third lower semiconductor chip 110lc and a fourth lower semiconductor chip 110ld sequentially stacked on a lower wiring board 130l, the lower wiring board 130l being interposed between the third semiconductor chip group III and the fourth semiconductor chip group IV); attaching the first leadframe (130u) to the second leadframe (130l) by way of a non-conductive adhesive (115ub, 115ua, 115lb, 115la) such that leads of a first plurality of leads/(portions of 130u) of the first leadframe (130u) are interleaved/(merge out in bending shape 120l) with leads of a second plurality of leads/(portions of 130l) of the second leadframe (130l) (see Fig.4D, Par.[0046]-[0047] wherein attaching or bonding step of the package: referring to FIG. 4D, a third semiconductor chip group III may be mounted on a lower surface of the die paddle part 120p, the third semiconductor chip group III including a first lower semiconductor chip 110la and a second lower semiconductor chip 110lb sequentially stacked; an adhesive material layer may be further provided between the third semiconductor chip group III and the die paddle part 120p; the third semiconductor chip group III may be mounted on the lower surface of the die paddle part 120p by means of the adhesive material layer; also, the second lower semiconductor chip 110lb may be stacked on the first lower semiconductor chip 110la by means of an adhesive material layer; see Par.[0041], [0043] wherein a first inter-chip material layer 115ua may be interposed between the first upper semiconductor chip 110ua and the second upper semiconductor chip 110ub; the first inter-chip material layer 115ua may include a non-conductive material; also, the first inter-chip material layer 115ua may have an adhesive characteristic; the first inter-chip material layer 115ua may be disposed to provide space (or height) for forming first semiconductor chip group bonding wires 125ua and 125ub; see Par.[0051] wherein a fourth inter-chip material layer 115lc may be interposed between the third lower semiconductor chip 110lc and the fourth lower semiconductor chip 110ld; the fourth inter-chip material layer 115lc may include a non-conductive material; also, the fourth inter-chip material layer 115lc may have an adhesive characteristic. The fourth inter-chip material layer 115lc may be disposed to provide space (or height) for forming fourth semiconductor chip group bonding wires 125lc and 125ld); and encapsulating with an encapsulant (140) the first (110uc) and second (110lc) semiconductor die and portions of the first (130u) and second (130l) leadframes (see step of Fig.4E, Par.[0054] wherein referring to FIG. 4E, a molded portion 140, which encapsulates the die paddle part 120p, the inner leads of the lead part 120l adjacent to the die paddle part 120p, the semiconductor chip groups I, II, III and IV, wiring boards 130u and 130l, and the bonding wires 125ua, 125ub, 125uc, 135ud, 125la, 125lb, 125lc and 125ld, is formed).
With respect to claim 2, Yoon discloses, in Figs.2-4E, the method, further comprising before encapsulating with the encapsulant: attaching a first end of a first bond wire (125uc) to a first bond pad of the first semiconductor die (110uc) and a second end of the first bond wire (125uc) to a first lead of the first plurality of leads/(portions of 130u); and attaching a first end of a second bond wire (125lc) to a second bond pad of the second semiconductor die (110lc) and a second end of the second bond wire (125lc) to a second lead of the second plurality of leads/(portions of 130l) (see step of Fig.4D, Par.[0031] wherein he second semiconductor chip group bonding wires 125uc and 125ud may electrically connect bonding pads of respective third upper semiconductor chip 110uc and fourth upper semiconductor chip 110ud of the second semiconductor chip group II, with the upper wiring board 130u; the third semiconductor chip group bonding wires 125la and 125lb may electrically connect bonding pads of respective first lower semiconductor chip 110la and second lower semiconductor chip 110lb, with the lead part 120l of the lead frame; the fourth semiconductor chip group bonding wires 125lc and 125ld may electrically connect bonding pads of respective third lower semiconductor chip 110lc and fourth lower semiconductor chip 110ld, with the lower wiring board 130l).
With respect to claim 4, Yoon discloses, in Figs.2-4E, the method, wherein attaching the first leadframe (130u) to the second leadframe (130l) by way of the non-conductive adhesive (115ua, 115ub, 115lb, 115 la) includes attaching a portion of the firstplurality of leads/(portions of 130u) of the first leadframe (130u) to a portion of the second plurality of leads/(portions of 130l) of the second leadframe (130l) by way of the non-conductive adhesive (115ua, 115ub, 115lb, 115 la) (see Par.[0041], [0043] wherein a first inter-chip material layer 115ua may be interposed between the first upper semiconductor chip 110ua and the second upper semiconductor chip 110ub; the first inter-chip material layer 115ua may include a non-conductive material; also, the first inter-chip material layer 115ua may have an adhesive characteristic; the first inter-chip material layer 115ua may be disposed to provide space (or height) for forming first semiconductor chip group bonding wires 125ua and 125ub; see Par.[0051] wherein a fourth inter-chip material layer 115lc may be interposed between the third lower semiconductor chip 110lc and the fourth lower semiconductor chip 110ld; the fourth inter-chip material layer 115lc may include a non-conductive material; also, the fourth inter-chip material layer 115lc may have an adhesive characteristic; the fourth inter-chip material layer 115lc may be disposed to provide space (or height) for forming fourth semiconductor chip group bonding wires 125lc and 125ld).
With respect to claim 5, Yoon discloses, in Figs.2-4E, the method, wherein attaching the first leadframe (130u) to the second leadframe (130l) by way of the non-conductive adhesive (115ua, 115ub) further includes attaching a backside of the first die pad/(portion of 130u underlying 110uc) of the first leadframe (130u) to a backside of the second die pad/(portion of 130l underlying 110lc) of the second leadframe (113l) by way of the non-conductive adhesive (115la, 115lb) (see Par.[0041], [0043] wherein a first inter-chip material layer 115ua may be interposed between the first upper semiconductor chip 110ua and the second upper semiconductor chip 110ub; the first inter-chip material layer 115ua may include a non-conductive material; also, the first inter-chip material layer 115ua may have an adhesive characteristic; the first inter-chip material layer 115ua may be disposed to provide space (or height) for forming first semiconductor chip group bonding wires 125ua and 125ub; see Par.[0051] wherein a fourth inter-chip material layer 115lc may be interposed between the third lower semiconductor chip 110lc and the fourth lower semiconductor chip 110ld; the fourth inter-chip material layer 115lc may include a non-conductive material; also, the fourth inter-chip material layer 115lc may have an adhesive characteristic; the fourth inter-chip material layer 115lc may be disposed to provide space (or height) for forming fourth semiconductor chip group bonding wires 125lc and 125ld).
With respect to claim 6, Yoon discloses, in Figs.2-4E, the method, wherein the non-conductive adhesive (115ua, 115ub, 115la, 115lb) is characterized as a non-conductive die attach film (DAF) (see Par.[0041], [0043] wherein a first inter-chip material layer 115ua may be interposed between the first upper semiconductor chip 110ua and the second upper semiconductor chip 110ub; the first inter-chip material layer 115ua may include a non-conductive material; also, the first inter-chip material layer 115ua may have an adhesive characteristic; the first inter-chip material layer 115ua may be disposed to provide space (or height) for forming first semiconductor chip group bonding wires 125ua and 125ub; see Par.[0051] wherein a fourth inter-chip material layer 115lc may be interposed between the third lower semiconductor chip 110lc and the fourth lower semiconductor chip 110ld; the fourth inter-chip material layer 115lc may include a non-conductive material; also, the fourth inter-chip material layer 115lc may have an adhesive characteristic; the fourth inter-chip material layer 115lc may be disposed to provide space (or height) for forming fourth semiconductor chip group bonding wires 125lc and 125ld).
With respect to claim 8, Yoon discloses, in Figs.2-4E, the method, further comprising before encapsulating with the encapsulant, attaching a third semiconductor die (110ud) to an active side/(electrical connection upper side) of the first semiconductor die (110uc) (see step of Fig.4D, Par.[0044]-[0045] wherein the fourth upper semiconductor chip 110ud may be stacked on the third upper semiconductor chip 110uc by means of an adhesive material layer and the second semiconductor chip group bonding wires 125uc and 125ud may be used to electrically connect bonding pads (not shown) of the third upper semiconductor chip 110uc and the fourth upper semiconductor chip 110ud to the lead part 120l of the lead frame).
With respect to claim 9, Yoon discloses, in Figs.2-4E, the method, further comprising before encapsulating with the encapsulant, attaching a first end of a third bond wire (115ud) to a first bond pad of the third semiconductor die (110ud) and a second end of the third bond wire (115ud) to a third lead of the first plurality of leads/(portions of 130u) (see step of Fig.4D, Par.[0044]-[0045] wherein the fourth upper semiconductor chip 110ud may be stacked on the third upper semiconductor chip 110uc by means of an adhesive material layer and the second semiconductor chip group bonding wires 125uc and 125ud may be used to electrically connect bonding pads (not shown) of the third upper semiconductor chip 110uc and the fourth upper semiconductor chip 110ud to the lead part 120l of the lead frame).
With respect to claim 10, Yoon discloses, in Figs.2-4E, a semiconductor device comprising: a first leadframe (130u) including a first die pad/(portion of 130u underlying 110uc) and a first plurality of leads/(portions of 130u); a first semiconductor die (110uc) attached to the first die pad of the first leadframe (130u); a second leadframe (130l) including a second die pad/(portion 130l underlying 110lc) and a second plurality of leads/(portions of 130l), the first leadframe (130u) attached to the second leadframe (130l) by way of a non-conductive adhesive (115ua, 115ub, 115la, 115lb) such that leads of the first plurality of leads/(portions of 130u) are interleaved/(merge out in bending shape 120l) with leads of the second plurality of leads/(portions of 130l); a second semiconductor die (110lc) attached to the second die pad/(portion of 130l underlying 110lc) of the second leadframe (130l) (see Par.[0023] wherein a semiconductor chip stack-type package may include a lead frame, semiconductor chip groups I, II, III and IV, wiring boards 130u and 130l, bonding wires 125ua, 125ub, 125uc, 125ud, 125la, 125lb, 125lc and 125ld, and a molded portion 140; see Par.[0025] wherein the second semiconductor chip group II may include a third upper semiconductor chip 110uc and a fourth upper semiconductor chip 110ud sequentially stacked on an upper wiring board 130u, the upper wiring board 130u being interposed between the first semiconductor chip group I and the second semiconductor chip group II; the fourth semiconductor chip group IV may include a third lower semiconductor chip 110lc and a fourth lower semiconductor chip 110ld sequentially stacked on a lower wiring board 130l, the lower wiring board 130l being interposed between the third semiconductor chip group III and the fourth semiconductor chip group IV; see Fig.4D, Par.[0046]-[0047] wherein attaching or bonding step of the package: referring to FIG. 4D, a third semiconductor chip group III may be mounted on a lower surface of the die paddle part 120p, the third semiconductor chip group III including a first lower semiconductor chip 110la and a second lower semiconductor chip 110lb sequentially stacked; an adhesive material layer may be further provided between the third semiconductor chip group III and the die paddle part 120p; the third semiconductor chip group III may be mounted on the lower surface of the die paddle part 120p by means of the adhesive material layer; also, the second lower semiconductor chip 110lb may be stacked on the first lower semiconductor chip 110la by means of an adhesive material layer; see Par.[0041], [0043] wherein a first inter-chip material layer 115ua may be interposed between the first upper semiconductor chip 110ua and the second upper semiconductor chip 110ub; the first inter-chip material layer 115ua may include a non-conductive material; also, the first inter-chip material layer 115ua may have an adhesive characteristic; the first inter-chip material layer 115ua may be disposed to provide space (or height) for forming first semiconductor chip group bonding wires 125ua and 125ub; see Par.[0051] wherein a fourth inter-chip material layer 115lc may be interposed between the third lower semiconductor chip 110lc and the fourth lower semiconductor chip 110ld; the fourth inter-chip material layer 115lc may include a non-conductive material; also, the fourth inter-chip material layer 115lc may have an adhesive characteristic; the fourth inter-chip material layer 115lc may be disposed to provide space (or height) for forming fourth semiconductor chip group bonding wires 125lc and 125ld); and an encapsulant (140) encapsulating the first (110uc) and second (110lc) semiconductor die and portions of the first (130u) and second (130l) leadframes (see step of Fig.4E, Par.[0054] wherein referring to FIG. 4E, a molded portion 140, which encapsulates the die paddle part 120p, the inner leads of the lead part 120l adjacent to the die paddle part 120p, the semiconductor chip groups I, II, III and IV, wiring boards 130u and 130l, and the bonding wires 125ua, 125ub, 125uc, 135ud, 125la, 125lb, 125lc and 125ld, is formed).
With respect to claim 11, Yoon discloses, in Figs.2-4E, the semiconductor device, further comprising: a first bond wire (125uc) having a first end attached to a first bond pad of the first semiconductor die (110uc) and a second end attached to a first lead of the first plurality of leads/(portions of 130u); and a second bond wire (125lc) having a first end attached to a second bond pad of the second semiconductor die (110lc) and a second end attached to a second lead of the second plurality of leads/(portions of 130l) (see step of Fig.4D, Par.[0031] wherein he second semiconductor chip group bonding wires 125uc and 125ud may electrically connect bonding pads of respective third upper semiconductor chip 110uc and fourth upper semiconductor chip 110ud of the second semiconductor chip group II, with the upper wiring board 130u; the third semiconductor chip group bonding wires 125la and 125lb may electrically connect bonding pads of respective first lower semiconductor chip 110la and second lower semiconductor chip 110lb, with the lead part 120l of the lead frame; the fourth semiconductor chip group bonding wires 125lc and 125ld may electrically connect bonding pads of respective third lower semiconductor chip 110lc and fourth lower semiconductor chip 110ld, with the lower wiring board 130l).
With respect to claim 13, Yoon discloses, in Figs.2-4E, the semiconductor device, wherein the non-conductive adhesive (115ua, 115ub, 115la, 115lb) is disposed between a portion of the first plurality of leads/(portions of 130u) of the first leadframe (130u) and a portion of the second plurality of leads/(portions of 130l) of the second leadframe (130lc) (see Par.[0041], [0043] wherein a first inter-chip material layer 115ua may be interposed between the first upper semiconductor chip 110ua and the second upper semiconductor chip 110ub; the first inter-chip material layer 115ua may include a non-conductive material; also, the first inter-chip material layer 115ua may have an adhesive characteristic; the first inter-chip material layer 115ua may be disposed to provide space (or height) for forming first semiconductor chip group bonding wires 125ua and 125ub; see Par.[0051] wherein a fourth inter-chip material layer 115lc may be interposed between the third lower semiconductor chip 110lc and the fourth lower semiconductor chip 110ld; the fourth inter-chip material layer 115lc may include a non-conductive material; also, the fourth inter-chip material layer 115lc may have an adhesive characteristic; the fourth inter-chip material layer 115lc may be disposed to provide space (or height) for forming fourth semiconductor chip group bonding wires 125lc and 125ld).
With respect to claim 14, Yoon discloses, in Figs.2-4E, the semiconductor device, wherein the non-conductive adhesive (115ua, 115ub, 115la, 115lb) is further disposed between a backside of the first die pad/(portion of 130u underlying 110uc) of the first leadframe (130u) and a backside of the second die pad/(portion of 130lc underlying 110lc) of the second leadframe (130l) (see Par.[0041], [0043] wherein a first inter-chip material layer 115ua may be interposed between the first upper semiconductor chip 110ua and the second upper semiconductor chip 110ub; the first inter-chip material layer 115ua may include a non-conductive material; also, the first inter-chip material layer 115ua may have an adhesive characteristic; the first inter-chip material layer 115ua may be disposed to provide space (or height) for forming first semiconductor chip group bonding wires 125ua and 125ub; see Par.[0051] wherein a fourth inter-chip material layer 115lc may be interposed between the third lower semiconductor chip 110lc and the fourth lower semiconductor chip 110ld; the fourth inter-chip material layer 115lc may include a non-conductive material; also, the fourth inter-chip material layer 115lc may have an adhesive characteristic; the fourth inter-chip material layer 115lc may be disposed to provide space (or height) for forming fourth semiconductor chip group bonding wires 125lc and 125ld).
With respect to claim 16, Yoon discloses, in Figs.2-4E, a method comprising: attaching a first semiconductor die (110uc) to a first die pad/(portion of 130u underlying 110uc) of a first leadframe (130u); attaching a second semiconductor die (110lc) to a second die pad/(portion of 130l underlying 110lc) of a second leadframe (130l); attaching a portion of a first plurality of leads/(portions of 130u) of the first leadframe (130u) to a portion of a second plurality of leads/(portions of 130l) of the second leadframe (130l) by way of a non-conductive adhesive (115ua, 115ub, 115la, 115lc), such that leads of the first plurality of leads are interleaved/(merge out in bending shape 120l) with leads of the second plurality of leads (see Par.[0023] wherein a semiconductor chip stack-type package may include a lead frame, semiconductor chip groups I, II, III and IV, wiring boards 130u and 130l, bonding wires 125ua, 125ub, 125uc, 125ud, 125la, 125lb, 125lc and 125ld, and a molded portion 140; see Par.[0025] wherein the second semiconductor chip group II may include a third upper semiconductor chip 110uc and a fourth upper semiconductor chip 110ud sequentially stacked on an upper wiring board 130u, the upper wiring board 130u being interposed between the first semiconductor chip group I and the second semiconductor chip group II; the fourth semiconductor chip group IV may include a third lower semiconductor chip 110lc and a fourth lower semiconductor chip 110ld sequentially stacked on a lower wiring board 130l, the lower wiring board 130l being interposed between the third semiconductor chip group III and the fourth semiconductor chip group IV; see Fig.4D, Par.[0046]-[0047] wherein attaching or bonding step of the package: referring to FIG. 4D, a third semiconductor chip group III may be mounted on a lower surface of the die paddle part 120p, the third semiconductor chip group III including a first lower semiconductor chip 110la and a second lower semiconductor chip 110lb sequentially stacked; an adhesive material layer may be further provided between the third semiconductor chip group III and the die paddle part 120p; the third semiconductor chip group III may be mounted on the lower surface of the die paddle part 120p by means of the adhesive material layer; also, the second lower semiconductor chip 110lb may be stacked on the first lower semiconductor chip 110la by means of an adhesive material layer; see Par.[0041], [0043] wherein a first inter-chip material layer 115ua may be interposed between the first upper semiconductor chip 110ua and the second upper semiconductor chip 110ub; the first inter-chip material layer 115ua may include a non-conductive material; also, the first inter-chip material layer 115ua may have an adhesive characteristic; the first inter-chip material layer 115ua may be disposed to provide space (or height) for forming first semiconductor chip group bonding wires 125ua and 125ub; see Par.[0051] wherein a fourth inter-chip material layer 115lc may be interposed between the third lower semiconductor chip 110lc and the fourth lower semiconductor chip 110ld; the fourth inter-chip material layer 115lc may include a non-conductive material; also, the fourth inter-chip material layer 115lc may have an adhesive characteristic; the fourth inter-chip material layer 115lc may be disposed to provide space (or height) for forming fourth semiconductor chip group bonding wires 125lc and 125ld); and encapsulating with an encapsulant (140) the first (110uc) and second semiconductor die (110lc), portions of the first (130u) and second (130l) leadframes, and the non-conductive adhesive (see Par.[0041], [0043] wherein a first inter-chip material layer 115ua may be interposed between the first upper semiconductor chip 110ua and the second upper semiconductor chip 110ub; the first inter-chip material layer 115ua may include a non-conductive material; also, the first inter-chip material layer 115ua may have an adhesive characteristic; the first inter-chip material layer 115ua may be disposed to provide space (or height) for forming first semiconductor chip group bonding wires 125ua and 125ub; see Par.[0051] wherein a fourth inter-chip material layer 115lc may be interposed between the third lower semiconductor chip 110lc and the fourth lower semiconductor chip 110ld; the fourth inter-chip material layer 115lc may include a non-conductive material; also, the fourth inter-chip material layer 115lc may have an adhesive characteristic; the fourth inter-chip material layer 115lc may be disposed to provide space (or height) for forming fourth semiconductor chip group bonding wires 125lc and 125ld).
With respect to claim 17, Yoon discloses, in Figs.2-4E, the method, further comprising before encapsulating with the encapsulant: attaching a first end of a first bond wire (125uc) to a first bond pad of the first semiconductor die (110uc) and a second end of the first bond wire (125uc) to a first lead of the first plurality of leads/(portions of 130u); and attaching a first end of a second bond wire (125lc) to a second bond pad of the second semiconductor die (110lc) and a second end of the second bond wire (125lc) to a second lead of the second plurality of leads/(portions of 130l) (see step of Fig.4E, Par.[0054] wherein referring to FIG. 4E, a molded portion 140, which encapsulates the die paddle part 120p, the inner leads of the lead part 120l adjacent to the die paddle part 120p, the semiconductor chip groups I, II, III and IV, wiring boards 130u and 130l, and the bonding wires 125ua, 125ub, 125uc, 135ud, 125la, 125lb, 125lc and 125ld, is formed).
With respect to claim 19, Yoon discloses, in Figs.2-4E, the method, further comprising attaching a backside of the first die pad of the first leadframe (130u) to a backside of the second die pad of the second leadframe (130l) by way of the non-conductive adhesive (115ua, 115ub, 115la, 115lb) (see Par.[0041], [0043] wherein a first inter-chip material layer 115ua may be interposed between the first upper semiconductor chip 110ua and the second upper semiconductor chip 110ub; the first inter-chip material layer 115ua may include a non-conductive material; also, the first inter-chip material layer 115ua may have an adhesive characteristic; the first inter-chip material layer 115ua may be disposed to provide space (or height) for forming first semiconductor chip group bonding wires 125ua and 125ub; see Par.[0051] wherein a fourth inter-chip material layer 115lc may be interposed between the third lower semiconductor chip 110lc and the fourth lower semiconductor chip 110ld; the fourth inter-chip material layer 115lc may include a non-conductive material; also, the fourth inter-chip material layer 115lc may have an adhesive characteristic; the fourth inter-chip material layer 115lc may be disposed to provide space (or height) for forming fourth semiconductor chip group bonding wires 125lc and 125ld).
Response to Arguments
Applicant’s arguments, see Applicant Arguments/Remarks, filed 01/06/2026, with respect to the rejections of claims 1, 10 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground of non-final rejections is made.
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOULOUCOULAYE INOUSSA whose telephone number is (571)272-0596. The examiner can normally be reached Monday-Friday (10-18).
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/Mouloucoulaye Inoussa/ Primary Examiner, Art Unit 2818