DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 31 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 31, lines 7-8 recite, forming first and second contacts on the first portions of the second semiconductor second layer. This recited language used to define the invention is ambiguous and clarifications and/or correction are/is required to make its meaning clear and precise whereby the metes and bounds of the claimed invention can be ascertained. No new matter may be added. For example, there is insufficient antecedent basis for “the second semiconductor second layer”. Is “the second semiconductor second layer” referring to the previously recited “second semiconductor layer” of claim 31 (please see, lines 3-4) or is “the second semiconductor second layer” referring to a different structure of the semiconductor device of claim 31 which is being fabricated by the method thereof? For purpose of examination, the Examiner is interpreting lines 7-8 of claim 31 as reciting “forming first and second contacts on the first portions of the second semiconductor layer” because of this ambiguity.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 15 is alternatively rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2004/0137761 A1 (Inoue).
Regarding claim 15, Inoue discloses, A semiconductor device, comprising:
a semiconductor structure (FIG. 2(b)) comprising a heterojunction ([0030]) between first (first semiconductor layer (11); FIG. 2(b); [0027]) and second (second semiconductor layer (12A); FIG. 5A; [0028]) semiconductor layers; and
an integrated resistor (dotted rectangle; annotated FIG. 2(b), below) in the semiconductor structure (FIG. 2(b)) wherein the integrated resistor has a sheet resistance of about 300 ohm/square to about 2500 ohm/square ([0030]—400 Ω/sq.; please see, MPEP 2131.03(I)—A Specific Example In The Prior Art Which Is Within A Claimed Range Anticipates The Range).
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Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the Examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 5-7, and 13 are rejected under 35 U.S.C. 103 as being unpatentable based on US 2022/0020873 A1 (Motoyoshi).
Regarding claim 1, Motoyoshi discloses, A semiconductor device, comprising:
a semiconductor structure (FIG. 5(b)) comprising first (first semiconductor layer (102); FIG. 5(b); [0050]) and second (second semiconductor layer (103); FIG. 5(b); [0050]) semiconductor layers having different bandgaps ([0050]);
first (first contact (113); FIG. 5(b); [0070]) and second (second contact (114); FIG. 5(b); [0070]) contacts on first portions (annotated FIG. 5(b), below) of the second semiconductor layer (first (113) and second (114) contacts are on first portions of second semiconductor layer (103)) and free of a gate structure therebetween (annotated FIG. 5(b), below); and
a resistor (resistor (22 and/or 23); FIGs. 5(a) and 5(b); [0069]) comprising a second portion (second portion (103 and 107); annotated FIG. 5(b), below; [0070]) of the second semiconductor layer (103) that electrically connects the first (113) and second (114) contacts ([0070] and [0071]),
wherein the second portion (103 and 107) comprises a second electrical resistance (a second electrical resistance of resistor (22 and/or 23) is an inherent characteristic defined, for example, by Ohm’s law; please see, MPEP 2112; annotated FIG. 5(b), below) and the first portions have a first electrical resistance (a first electrical resistance of first portions of second semiconductor layer (103) is an inherent characteristic defined, for example, by Ohm’s law; please see, MPEP 2112; annotated FIG. 5(b), below).
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But, Applicant may argue that Motoyoshi does not appear to explicitly disclose, wherein the second portion comprises a second electrical resistance that is different than a first electrical resistance of the first portions.
However, it would have been obvious to one of ordinary skill in the art having the teachings of Motoyoshi before him/her that a second electrical resistance of the second portion (103 and 107) of Motoyoshi that is different than a first electrical resistance of the first portions (annotated FIG. 5(b), above) is a result effective variable of resistivity which can be controlled through routine experimentation with a reasonable expectation of success by, for example, selecting the materials of first and second portions thereof, doping of the first and second portions, and/or selecting the dimensions of the first and second portions thereof, such as length and/or cross-sectional area. Please see, MPEP 2144.05(II).
Regarding claim 5, Motoyoshi discloses, The semiconductor device of Claim 1, further comprising:
a passivation layer (passivation layer (106); FIG. 5(b); [0050]) on the semiconductor structure (first semiconductor layer (102) and second semiconductor layer (103)) and in direct contact (FIG. 5(b)) with the second portion (103 and 107) of semiconductor layer (103).
Regarding claim 6, Motoyoshi discloses, The semiconductor device of Claim 1, wherein the resistor (22 and/or 23) extends between non-conductive regions (non-conductive regions (104) and/or (106); FIG. 5(b); [0050]) of the semiconductor structure (FIG. 5(b)).
Regarding claim 7, Motoyoshi discloses, The semiconductor device of Claim 6, wherein the first and second contacts (113 and 114) extend onto the non-conductive regions (104 and/or 106) of the semiconductor structure (FIGs. 5(a) and 5(b)).
Regarding claim 13, Motoyoshi discloses, The semiconductor device of Claim 1, wherein the semiconductor device is a passive device (resistor(s) 22 and/or 23 are passive devices)1 and the semiconductor structure is free of transistors (FIG 5(b)—there are no transistors).
Claims 2-4, 8, and 31 are rejected under 35 U.S.C. 103 as being unpatentable over Motoyoshi, as applied to claim 1, above, in view of US 2017/0338122 A1 (Daulton).
Regarding claim 2, Motoyoshi does not appear to explicitly disclose, wherein the second portion of the second semiconductor layer is recessed in thickness relative to the first portions thereof.
However, in analogous art, Daulton discloses that it is well-known that a semiconductor structure (FIG. 1C) can be predicably formed to include first semiconductor layer (first semiconductor layer (164); FIG. 1C; [0071]) and a second semiconductor layer (second semiconductor layer (162); FIG. 1C; [0071]). Daulton also discloses that it is well-known that second semiconductor layer (162) can be predicably formed to include a second portion (annotated FIG. 1C, below) that is recessed in thickness relative to a first portions thereof (annotated FIG. 1C, below).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Motoyoshi and Daulton before him/her, that it is well-known that the second portion (103 and 107) of the second semiconductor layer (103) of Motoyoshi could be predicably formed to be recessed in thickness relative to a first portions thereof, as taught by Daulton, with no change in the function of second portion (103 and 107) because it would still electrically connect first and second contacts (113 and 114). See, MPEP 2143(A)—Combining Prior Art Elements According to Known Methods to Yield Predicable Results.
Regarding claim 3, Motoyoshi in view of Daulton discloses, The semiconductor device of Claim 1, wherein a first carrier density ([0108] of Daulton—electron density is a carrier density) of a two-dimensional electron gas (2DEG) (two-dimension electron gas (2DEG) (107); FIG. 5(b); [0050], all of Motoyoshi) along respective interfaces between the first portions (annotated FIG. 5(b), above) of the second semiconductor layer (103) and the first semiconductor layer (102) has a second carrier density ([0108] of Daulton—electron density is a carrier density) of the 2DEG (107) along an interface between the second portion (103 and 107) of the second semiconductor layer (103) and the first semiconductor layer (102).
But, Applicant may argue that Motoyoshi in view of Daulton does not appear to explicitly disclose, wherein a first carrier density is higher than a second carrier density.
However, it would have been obvious to one of ordinary skill in the art having the teachings of Motoyoshi and Daulton before him/her that carrier density is a result effective variable which can be controlled through routine experimentation with a reasonable expectation of success by, for example, selecting the materials and/or doping of the two-dimensional electron gas (2DEG) (107) of Motoyoshi in view of Daulton along respective interfaces between the first portions (annotated FIG. 5(b), above) of the second semiconductor layer (103) and the first semiconductor layer (102), as well as or alternatively, the materials and/or doping of along an interface between the second portion (103 and 107) of the second semiconductor layer (103) and the first semiconductor layer (102) of Motoyoshi in view of Daulton, so that the first carrier density is higher than the second carrier density. Please see, MPEP 2144.05(II).
Regarding claim 4, Motoyoshi in view of Daulton discloses, The semiconductor device of Claim 1, further comprising:
ohmic contact elements (113 and 114; [0070] of Motoyoshi) on the second portion (103 and 107) of the second semiconductor layer (103) and electrically coupling the first and second contacts (113 and 114) to the second portion (103 and 107) of the second semiconductor layer (103).
Regarding claim 8, Motoyoshi in view of Daulton discloses that second portion of second semiconductor layer (162) is an AlGaN layer ([0071] of Daulton) and that an AlGaN layer may be recessed in thickness (as recited in claim 2 from which claim 8 depends) from 19 nm (FIG. 13A of Daulton) to 11 nm (FIG. 13B of Daulton). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Motoyoshi and Daulton before him/her, that a thickness of the second portion is greater than about 2 nanometers (nm) because this claimed range overlaps with the range of a recessed thickness from 19 nm 11 nm disclosed by Daulton. See, MPEP 2144.05(I)—"In the case where the claimed ranges ‘overlap or lie inside ranges disclosed by the prior art’ a prima facie case of obviousness exists.”
Regarding claim 31, Motoyoshi discloses, A method of fabricating a semiconductor device, the method comprising:
providing a semiconductor structure (FIG. 5(b)) comprising first (first semiconductor layer (102); FIG. 5(b); [0050]) and second (second semiconductor layer (103); FIG. 5(b); [0050]) semiconductor layers having different bandgaps ([0050]); and
forming first (first contact (113); FIG. 5(b); [0070]) and second (second contact (114); FIG. 5(b); [0070]) contacts on the first portions (annotated FIG. 5(b), above) of the second semiconductor second layer (first (113) and second (114) contacts are on first portions (annotated FIG. 5(b), above) of second semiconductor layer (103))2,
wherein the second portion (103 and 107) of the second semiconductor layer (103) extends between the first and second contacts (113 and 114) and comprises an integrated resistor (integrated resistor (107); FIG. 5(b); [0070]) that electrically connects the first (113) and second contacts (114) ([0071]).
But Motoyoshi does not appear to explicitly disclose, performing a looped recess process to recess a thickness of a second portion of the second semiconductor layer relative to first portions thereof.
However, in analogous art, Daulton discloses that it is well-known that a semiconductor structure (FIG. 1C) can be predicably formed to include first semiconductor layer (first semiconductor layer (164); FIG. 1C; [0071]) and a second semiconductor layer (second semiconductor layer (162); FIG. 1C; [0071]). Daulton also discloses that it is well-known that a looped recess process (looped recess process (160); FIG. 1C; [0070]-[0072]) can be predicably performed to recess a thickness of a second portion (annotated FIG. 1C, above) of second semiconductor layer (162) relative to a first portions thereof (annotated FIG. 1C, above).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Motoyoshi and Daulton before him/her, that it is well-known that a looped recess process can be predicably performed to recess a thickness of a second portion (103 and 107) of the second semiconductor layer (103) of Motoyoshi, relative to a first portions (annotated FIG. 5(b), above) thereof, as taught by Daulton, wherein the second portion (103 and 107) of the second semiconductor layer (103) of Motoyoshi comprises an integrated resistor (107), with no change in the function of the second portion (103 and 107) of the second semiconductor layer (103) because it would still comprise an integrated resistor that electrically connects the first and second contacts (113 and 114). See, MPEP 2143(A), above.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Motoyoshi in view of Daulton, as applied to claim 8, above, and further in view of US 2022/0161556 A1 (Mou).
Regarding claim 9, Motoyoshi in view of Daulton does not appear to explicitly disclose, The semiconductor device of Claim 8, wherein the second portion has one or more lateral dimensions of about 0.25 microns to about 1000 microns.
However, in analogous art, Mou discloses that it is well-known that a semiconductor device (semiconductor device (21); FIG. 2; [0023]) can be predicably formed to have a semiconductor layer portion (semiconductor layer portion (222); FIG. 3; [0023]) that is resistive with a length (which is a lateral dimension) ranging from 5 microns to 30 microns ([0009]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Motoyoshi, Daulton, and Mou before him/her, that the second portion of Motoyoshi in view of Daulton has one or more lateral dimensions of about 0.25 microns to about 1000 microns because this claimed range overlaps with the range of a length ranging from 5 microns to 30 microns for a portion of a semiconductor layer disclosed by Mou. See, MPEP 2144.05(I), above.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Motoyoshi in view of Daulton, as applied to claim 2, above, and further in view of US 2023/0093367 A1 (Baek).
Regarding claim 10, Motoyoshi in view of Daulton discloses, The semiconductor device of Claim 2, wherein the first (102) and second (103) semiconductor layers comprise group III-nitride-based materials ([0070] of Motoyoshi).
Regarding claim 10, Motoyoshi in view of Daulton does not appear to explicitly disclose, wherein the second semiconductor layer comprises an aluminum composition of about 20 to about 35 percent, and the thickness of the second portion is about 5 nanometers (nm) to about 10 nm.
However, in analogous art, Baek discloses, a semiconductor layer (semiconductor layer (403s); FIG. 4; [0168]) that comprises an aluminum composition that may decrease in a thickness direction from 30 atomic % or more to 10 atomic % or less ([0168]). Baek also discloses that semiconductor layer (403s) may have a thickness less than about 30 nm ([0168]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Motoyoshi, Daulton, and Baek before him/her, that the second semiconductor layer (103) of Motoyoshi in view of Daulton comprises an aluminum composition of about 20 to about 35 percent because this claimed range overlaps with the range of 30 atomic % or more to 10 atomic % or less disclosed by Baek. See, MPEP 2144.05(I), above.
It would have also been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Motoyoshi, Daulton, and Baek before him/her, that the second portion of the second semiconductor layer (103) of Motoyoshi in view of Daulton have a thickness of about 5 nanometers (nm) to about 10 nm because this claimed range lies inside the range of less than about 30 nm disclosed by Baek. See, MPEP 2144.05(I), above.
Claims 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Motoyoshi, as applied to claim 1, above, in view of US 2017/0025406 A1 (Liao).
Regarding claim 11, Motoyoshi does not appear to explicitly disclose, The semiconductor device of Claim 1, further comprising:
source and drain contacts and a gate therebetween on an active region of the semiconductor structure, the active region comprising at least one transistor,
wherein the resistor continuously extends from the first contact to the second contact outside of the active region.
However, in analogous art, Liao discloses, that it is well known that a semiconductor device (FIG. 2; [0018]) can be predicably fabricated to include at least one transistor (transistor (T); FIG. 2; [0020]) and a resistor (resistor (R); FIG. 2; [0031]). Liao also discloses that it is well-known that transistor (T) can be predicably fabricated to include a source contact (source contact (130); FIG. 2; [0020]) and a drain contact (drain contact (140); FIG. 2; [0020]) with a gate (gate (150); FIG. 2; [0020]) therebetween (annotated FIG. 2, below) on an active region (active region (120T); FIG. 2; [0020]) of a semiconductor structure (FIG. 2) that includes a portion (portion (126); FIG. 2; [0022]) that electrically connects source and drain contacts (130 and 140), as well as a first contact (first contact (210); FIG. 2; [0031]) and a second contact (second contact (220); FIG. 2; [0031]) of resistor (resistor (R); FIG. 2; [0031]). Liao additionally discloses that it is well-known that resistor (R) can be predicably fabricated to continuously extend from first contact (210) to second contact (220) outside of active region (120T) (annotated FIG. 2, below). Liao further discloses that source contact (130), drain contact (140), first contact (210), and second contact (220) can be manufactured in the same manufacturing process which allows transistor (T) and resistor (R) to be formed without additional processes thereby saving cost and manufacturing time ([0034]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Motoyoshi and Liao before him/her, that it is well-known that the semiconductor device of Motoyoshi can be predicably formed to include source and drain contacts and a gate therebetween on an active region of the semiconductor structure (FIG. 5(b)) of Motoyoshi, as taught by Liao, the active region comprising at least one transistor, as also taught by Liao, wherein the resistor (22 and/or 23) of Motoyoshi continuously extends from the first contact (113) to the second contact (114) of Motoyoshi outside of the active region, as additionally taught by Liao, which allows the resistor of Motoyoshi and the at least one transistor to be formed without additional processes thereby saving cost and manufacturing time, as further taught by Liao.
Regarding claim 12, Motoyoshi in view of Liao discloses, The semiconductor device of Claim 11, wherein the resistor (22 and/or 23) comprises a portion of an impedance matching, harmonic termination, or bias control circuit (bias control circuit (20a); FIG. 4(a); [0066]), all of Motoyoshi) of the at least one transistor (T) outside the active region (120T).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Motoyoshi, as applied to claim 1, above, and further in view of US 3,341,380 (Gentry).
Regarding claim 14, Motoyoshi does not appear to explicitly disclose, The semiconductor device of Claim 1, wherein the resistor has a sheet resistance of about 300 ohm/square to about 2500 ohm/square.
However, in analogous art, Gentry discloses that it is well-known that in a semiconductor device (FIG. 2) a semiconductor layer (semiconductor layer (25); FIG. 2; Col. 6, lines 1-4) can be predicably formed to have a sheet resistance of 1000 ohms or greater (Col. 6, lines 13-14).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Motoyoshi and Gentry before him/her, that the resistor (22 and/or 23) of Motoyoshi has a sheet resistance of about 300 ohm/square to about 2500 ohm/square because this claimed range overlaps with the range of a sheet resistance of 1000 ohms or greater disclosed by Gentry. See, MPEP 2144.05(I), above.
Claims 15, 16, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0375927 A1 (Mao) in view of Gentry.
Regarding claim 15, Mao discloses, A semiconductor device, comprising:
a semiconductor structure (FIG. 5A) comprising a heterojunction ([0044]) between first (first semiconductor layer (14); FIG. 5A; [0039]) and second (second semiconductor layer (16); FIG. 5A; [0039]) semiconductor layers; and
an integrated resistor (integrated resistor (14g); FIG. 5A; dotted rectangle B; [0044]; [0058]; [0071]; [0125]) in the semiconductor structure (FIG. 5A).
But Mao does not appear to explicitly disclose, wherein the integrated resistor has a sheet resistance of about 300 ohm/square to about 2500 ohm/square.
However, in analogous art, Gentry discloses that it is well-known that in a semiconductor device (FIG. 2) a semiconductor layer (semiconductor layer (25); FIG. 2; Col. 6, lines 1-4) can be predicably formed to have a sheet resistance of 1000 ohms or greater (Col. 6, lines 13-14).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Mao and Gentry before him/her, that the integrated resistor (14g) of Mao has a sheet resistance of about 300 ohm/square to about 2500 ohm/square because this claimed range overlaps with the range of a sheet resistance of 1000 ohms or greater disclosed by Gentry. See MPEP 2144.05(I), above.
Regarding claim 16, Mao in view of Gentry discloses, The semiconductor device of Claim 15, further comprising:
first (first contact (32f); FIG. 5A; [0058]) and second (second contact (32g); FIG. 5A; [0058]) contacts on the semiconductor structure (FIG. 5A) and free of a gate structure therebetween (first annotated FIG. 5A, above),
wherein the integrated resistor (14g) comprises a portion (FIG. 5A—dotted rectangle B) of the semiconductor structure (FIG. 5A) that electrically connects ([0058]; [0071]; [0125]) the first and second contacts (32f and 32g).
Regarding claim 22, Mao in view of Gentry discloses, The semiconductor device of Claim 16, further comprising:
a passivation layer (passivation layer (22); FIG. 1; [0045], all of Mao) on the portion (FIG. 5A—dotted rectangle B) of the semiconductor structure (FIG. 5A) and in direct contact with the second semiconductor layer (16) (first annotated FIG. 5A, above).
Claims 17-21 are rejected under 35 U.S.C. 103 as being unpatentable over Mao in view of Gentry, as applied to claim 16, above, in view of Daulton.
Regarding claim 17, Mao in view of Gentry does not appear to explicitly disclose, The semiconductor device of Claim 16, wherein the portion of the semiconductor structure comprises a second portion of the second semiconductor layer that is recessed in thickness relative to a first portion thereof.
However, in analogous art, Daulton discloses that it is well-known that a semiconductor structure (FIG. 1C) can be predicably formed to include first semiconductor layer (first semiconductor layer (164); FIG. 1C; [0071]) and a second semiconductor layer (second semiconductor layer (162); FIG. 1C; [0071]). Daulton also discloses that it is well-known that second semiconductor layer (162) can be predicably formed to include second portion (annotated FIG. 1C, above) that is recessed in thickness relative to a first portion thereof (annotated FIG. 1C, above).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Mao, Gentry, and Daulton before him/her, that it is well-known that the portion (FIG. 5A—dotted rectangle B) of the semiconductor structure (FIG. 5A) of Mao in view of Gentry could be predicably formed to comprise a second portion of the second semiconductor layer (16) that is recessed in thickness relative to a first portion thereof, as taught by Daulton, with no change in the function of portion (FIG. 5A—dotted rectangle B) because it would still electrically connect first and second contacts (32f and 32g). See, MPEP 2143(A), above.
Regarding claim 18, Mao in view of Gentry and Daulton discloses, The semiconductor device of Claim 17, wherein the second portion of the second semiconductor layer (16) extends between non-conductive regions (non-conductive regions (24 and/or 36c); annotated FIG. 1, below); [0047]; [0051], all of Mao) of the semiconductor structure (FIG. 5A).
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Regarding claim 19, Mao in view of Gentry and Daulton discloses, The semiconductor device of Claim 18, wherein the first and second contacts (32f and 32g) extend onto the non-conductive regions (24 and/or 36c; annotated FIG. 1, above) of the semiconductor structure (FIG. 5A) and are electrically coupled to the second portion of the second semiconductor layer (16) ([0058]).
Regarding claim 20, Mao in view of Gentry and Daulton discloses, The semiconductor device of Claim 19, further comprising:
ohmic contact elements (ohmic contact elements (242); FIG. 2D; [0083], all of Mao) on the second portion of the second semiconductor layer (16) and electrically coupling the second portion of the second semiconductor layer (16) to the first and second contacts (32f and 32g).
Regarding claim 21, Mao in view of Gentry and Daulton discloses that second portion of second semiconductor layer (162) is an AlGaN layer ([0071] of Daulton) and that an AlGaN layer may be recessed in thickness (as recited in claim 17 from which claim 21 depends) from 19 nm (FIG. 13A of Daulton) to 11 nm (FIG. 13B of Daulton). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Mao, Gentry, and Daulton before him/her, that a thickness of the second portion is greater than about 2 nanometers (nm) because this claimed range overlaps with the range of a recessed thickness from 19 nm 11 nm disclosed by Daulton. See, MPEP 2144.05(I), above.
Claims 23-25 are rejected under 35 U.S.C. 103 as being unpatentable over Mao in view of Daulton.
Regarding claim 23, Mao discloses, A semiconductor device, comprising:
a semiconductor structure (FIG. 5A) comprising a heterojunction ([0044]) between a channel layer (channel layer (14); FIG. 5A; [0042]) and a barrier layer (barrier layer (16); FIG. 2A; [0043]) thereon;
first (first contact (32f); FIG. 5A; [0058]) and second (second contact (32g); FIG. 5A; [0058]) contacts on the semiconductor structure (FIG. 5A) and free of a gate structure therebetween (first annotated FIG. 5A, below); and
an integrated resistor (integrated resistor (14g); FIG. 5A; dotted rectangle B; [0044]; [0058]; [0071]; [0125]) comprising a second portion (first annotated FIG. 5A, below) of the barrier layer (16) that extends between the first and second contacts (32f and 32g).
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But Mao does not appear to explicitly disclose, the second portion is recessed in thickness relative to a first portion thereof.
However, in analogous art, Daulton discloses that it is well-known that a semiconductor structure (FIG. 1C) can be predicably formed to include first semiconductor layer (first semiconductor layer (164); FIG. 1C; [0071]) and a second semiconductor layer (second semiconductor layer (162); FIG. 1C; [0071]). Daulton also discloses that it is well-known that second semiconductor layer (162) can be predicably formed to include second portion (annotated FIG. 1C, above) that is recessed in thickness relative to a first portion thereof (annotated FIG. 1C, above).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Mao and Daulton before him/her, that it is well-known that the second portion (first annotated FIG. 5A, above) of the barrier layer (16) of Mao could be predicably formed to be recessed in thickness relative to a first portion thereof, as taught by Daulton, with no change in the function of the second portion (first annotated FIG. 5A, above) of the barrier layer (16) because it would still act as a resistor. See, MPEP 2143(A), above.
Regarding claim 24, Mao in view of and Daulton do not appear to explicitly disclose how to solve the problem of fabricating the semiconductor device thereof such that, wherein the first portion of the barrier layer has a first electrical resistance associated therewith, and the second portion of the barrier layer has a second electrical resistance associated therewith that is higher than the first electrical resistance.
However, there are a finite number of predicable solutions regarding a second electrical resistance associated with the second portion of the barrier layer (16) of Mao in view of Daulton relative to a first electrical resistance associated with the first portion of the barrier layer (16)—i.e., the second electrical resistance can be the same, lower than, or higher than the first electrical resistance—and, absent unexpected results, it would, therefore, have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to try each of them with a reasonable expectation of success, one of which is: wherein the first portion of the barrier layer (16) has a first electrical resistance associated therewith, and the second portion of the barrier layer (16) has a second electrical resistance associated therewith that is higher than the first electrical resistance, as recited in claim 24. See, MPEP 2143(E)—“Obvious To Try”—Choosing From A Finite Number Of Identified, Predictable Solutions, With A Reasonable Expectation Of Success.
Regarding claim 25, Mao in view of Daulton discloses that second portion of second semiconductor layer (162) is an AlGaN layer ([0071] of Daulton) and that an AlGaN layer may be recessed in thickness (as recited in claim 23 from which claim 25 depends) from 19 nm (FIG. 13A of Daulton) to 11 nm (FIG. 13B of Daulton). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Mao and Daulton before him/her, that a thickness of the second portion is greater than about 2 nanometers (nm) because this claimed range overlaps with the range of a recessed thickness from 19 nm 11 nm disclosed by Daulton. See, MPEP 2144.05(I), above.
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Mao in view of Daulton, as applied to claim 25, above, and further in view of Mou.
Regarding claim 26, Mao in view of Daulton does not appear to explicitly disclose, The semiconductor device of Claim 25, wherein the second portion has one or more lateral dimensions of about 0.25 microns to about 1000 microns.
However, in analogous art, Mou discloses that it is well-known that a semiconductor device (semiconductor device (21); FIG. 2; [0023]) can be predicably formed to have a semiconductor layer portion (semiconductor layer portion (222); FIG. 3; [0023]) that is resistive with a length (which is a lateral dimension) ranging from 5 microns to 30 microns ([0009]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Mao, Daulton, and Mou before him/her, that the second portion of Mao in view of Daulton has one or more lateral dimensions of about 0.25 microns to about 1000 microns because this claimed range overlaps with the range of a length ranging from 5 microns to 30 microns for a portion of a semiconductor layer disclosed by Mou. See MPEP 2144.05(I), above.
Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over Mao in view of Daulton, as applied to claim 23, above, and further in view of Baek.
Regarding claim 27, Mao in view of Daulton discloses, The semiconductor device of Claim 23, wherein the channel layer (14) and the barrier layer (16) semiconductor layers comprise group III-nitride-based materials ([0042]-[0043] of Mao).
Regarding claim 27, Mao in view of Daulton does not appear to explicitly disclose, wherein the barrier layer comprises an aluminum composition of about 20 to about 35 percent, and the thickness of the second portion is about 5 nanometers (nm) to about 10 nm.
However, in analogous art, Baek discloses, a semiconductor layer (semiconductor layer (403s); FIG. 4; [0168]) that comprises an aluminum composition that may decrease in a thickness direction from 30 atomic % or more to 10 atomic % or less ([0168]). Baek also discloses that semiconductor layer (403s) may have a thickness less than about 30 nm ([0168]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Mao, Daulton, and Baek before him/her, that the barrier layer (16) of Mao in view of Daulton comprises an aluminum composition of about 20 to about 35 percent because this claimed range overlaps with the range of 30 atomic % or more to 10 atomic % or less disclosed by Baek. See, MPEP 2144.05(I), above.
It would have also been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Mau, Daulton, and Baek before him/her, that the second portion (annotated FIG. 5A, above) of Mao in view of Daulton have a thickness of about 5 nanometers (nm) to about 10 nm because this claimed range lies inside the range of less than about 30 nm disclosed by Baek. See MPEP 2144.05(I), above.
Claims 28 and 40 are rejected under 35 U.S.C. 103 as being unpatentable over Mao.
Regarding claim 28, Mao discloses, A semiconductor device, comprising:
a semiconductor structure (FIG. 5A) comprising a heterojunction ([0044]) between a channel layer (channel layer (14); FIG. 5A; [0042]) and a barrier layer (barrier layer (16); FIG. 5A; [0043]) thereon;
first (first contact (32f); FIG. 5A; [0058]) and second (second contact (32g); FIG. 5A; [0058]) contacts on first portions (second annotated FIG. 5A, below) of the barrier layer (16) and free of a gate structure therebetween (second annotated FIG. 5A, below);
a passivation layer (passivation layer (22); FIG. 1; [0045]) directly on a second portion (second annotated FIG. 5A, below) of the barrier layer (16) between the first and second contacts (32f and 32g); and
an integrated resistor (integrated resistor (14g); FIG. 5A; dotted rectangle B; [0044]; [0058]; [0071]; [0125]) that electrically connects ([0058]; [0071]; [0125]) the first and second contacts (32f and 32g) and comprises the second portion (second annotated FIG. 5A, below) of the barrier layer (16) having the passivation layer (22) thereon (second annotated FIG. 5A, below),
wherein the second portion (second annotated FIG. 5A, below) of the barrier layer (16) comprises an electrical resistance (an electrical resistance of the second portion is an inherent characteristic defined, for example, by Ohm’s law; please see, MPEP 2112; second annotated FIG. 5A, below) and the first portions have an electrical resistance (an electrical resistance of the first portions is an inherent characteristic defined, for example, by Ohm’s law; please see, MPEP 2112; second annotated FIG. 5A, below) of the barrier layer (16) having the first and second contacts (32f and 32g) thereon.
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But, Applicant may argue that Mao does not appear to explicitly disclose, wherein the second portion of the barrier layer comprises a different electrical resistance than the first portions of the barrier layer having the first and second contacts.
However, it would have been obvious to one of ordinary skill in the art having the teachings of Mao before him/her that an electrical resistance of the second portion (second annotated FIG. 5A, above) of the barrier layer (16) of Mao is different than an electrical resistance of the first portions (second annotated FIG. 5A, above) of the barrier layer (16) having the first and second contacts (32f and 32g) is a result effective variable of resistivity which can be controlled through routine experimentation with a reasonable expectation of success by, for example, selecting the materials of first and second portions thereof, doping of the first and second portions, and/or selecting the dimensions of the first and second portions thereof, such as length and/or cross-sectional area. Please see, MPEP 2144.05(II).
Regarding claim 40, Mao discloses, A method of fabricating a semiconductor device, the method comprising:
providing a semiconductor structure (FIG. 5A) comprising first (first semiconductor layer (14); FIG. 5A; [0042]) and second (second semiconductor layer (16); FIG. 5A; [0043]) semiconductor layers having a heterojunction ([0044]) therebetween;
forming a passivation layer (passivation layer (22); FIG. 1; [0045]) directly on a second portion (third annotated FIG. 5A, below) of the second semiconductor layer (16); and
forming first (first contact (32f); FIG. 5A; [0058]) and second (second contact (32g); FIG. 5A; [0058]) contacts on first portions of the second semiconductor layer ((16); third annotated FIG. 5A, below),
wherein the second portion (third annotated FIG. 5A, below) of the second semiconductor layer (16) having the passivation layer (22) thereon comprises an integrated resistor (integrated resistor (14g); FIG. 5A; dotted rectangle B; [0044]; [0058]; [0071]; [0125]) that electrically connects ([0058]; [0071]; [0125]) the first and second contacts (32f and 32g) free of a gate electrode therebetween (third annotated FIG. 5A, below),
wherein the second portion (third annotated FIG. 5A, below) comprises an electrical resistance (an electrical resistance of the second portion is an inherent characteristic defined, for example, by Ohm’s law; please see, MPEP 2112; third annotated FIG. 5A, below) and the first portions (third annotated FIG. 5A, below) of the second semiconductor layer (16) have an electrical resistance (an electrical resistance of the first portions is an inherent characteristic defined, for example, by Ohm’s law; please see, MPEP 2112; third annotated FIG. 5A, below).
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But, Applicant may argue that Mao does not appear to explicitly disclose, wherein the second portion comprises a different electrical resistance than the first portions of the second semiconductor layer.
However, it would have been obvious to one of ordinary skill in the art having the teachings of Mao before him/her that an electrical resistance of the second portion (third annotated FIG. 5A, above) of Mao is different than an electrical resistance of the first portions (third annotated FIG. 5A, above) of the second semiconductor layer (16) is a result effective variable of resistivity which can be controlled through routine experimentation with a reasonable expectation of success by, for example, selecting the materials of first and second portions thereof, doping of the first and second portions, and/or selecting the dimensions of the first and second portions thereof, such as length and/or cross-sectional area. Please see, MPEP 2144.05(II).
Claim 30 is rejected under 35 U.S.C. 103 as being unpatentable over Mao, as applied to claim 28, above, in view of Baek and further in view of US 5,825,068 (Yang).
Regarding claim 30, Mao discloses, The semiconductor device of Claim 28, wherein the channel layer (14) and the barrier layer (16) semiconductor layers comprise group III-nitride-based materials ([0042]-[0043]).
Regarding claim 30, Mao does not appear to explicitly disclose, wherein the barrier layer comprises an aluminum composition of about 20 to about 35 percent, and the passivation layer comprises silicon nitride.
However, in analogous art, Baek discloses, a semiconductor layer (semiconductor layer (403s); FIG. 4; [0168]) that comprises an aluminum composition that may decrease in a thickness direction from 30 atomic % or more to 10 atomic % or less ([0168]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Mao and Baek before him/her, that the barrier layer (16) of Mao in view of Daulton comprises an aluminum composition of about 20 to about 35 percent because this claimed range overlaps with the range of 30 atomic % or more to 10 atomic % or less disclosed by Baek. See, MPEP 2144.05(I), above.
But Mao in view of Baek does not appear to explicitly disclose, the passivation layer comprises silicon nitride.
However, in analogous art, Yang discloses that it is well-known that silicon nitride is widely used as a passivation layer in integrated circuits because it is a good barrier to diffusion of moisture (Col. 1, lines 30-32).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Mao, Baek, and Yang before him/her, that the passivation layer (22) of Mao in view of Baek comprises silicon nitride, as taught by Yang, to provide a good barrier to diffusion of moisture, as also taught by Yang.
Response to Amendments and Arguments
Applicant’s amendment of dependent claim 6 and remarks on page ten (10) of the Amendment dated February 9, 2026 (hereinafter the “Reply”) have overcome the objection to dependent claim 6 in the Office Action dated November 10, 2025 (hereinafter the “Office Action”). Applicant’s amendment of independent claims 1, 28, 31, and 40; dependent claims 2-6, and 11; and remarks on pages ten (10)-twenty (20) of the Reply have been reviewed and considered by the Examiner. However, they are not deemed persuasive for at least the following reasons.
For example, regarding amended independent claim 1, page ten (10) of the Reply states: “Claims 1, 5-7, and 13 are rejected as being anticipated by Motoyoshi, while Claim 3 (the recitations of which have been included in Claim 1) is rejected as being unpatentable over Motoyoshi in view of Daulton.” Also regarding amended independent claim 1, page 13 of the Reply states:
Accordingly neither Motoyoshi nor Daulton, alone or in combination, disclose or suggest a second semiconductor layer including "first and second contacts on first portions" and "a second portion...that electrically connects the first and second contacts," where "the second portion comprises a second electrical resistance that is different than a first electrical resistance of the first portions," as recited by Claim 1. Claim 1 and the claims dependent therefrom are patentable for at least these reasons.
The Examiner respectfully notes that this structure and these limitations of independent claim 1, highlighted by Applicant on page 13 of the Reply, as quoted above, where added by Applicant to amended independent claim 1 in the Reply. They were not previously in unamended independent claim 1 that was rejected in the Office Action as being anticipated under 35 U.S.C. 102(a)(1) by Motoyoshi. The Examiner also respectfully notes that some of this above-quoted added structure and added limitations of amended independent claim 1 (e.g., first and second contacts on first portions" and "a second portion...that electrically connects the first and second contacts”) were not part of unamended dependent claim 3 that was rejected in the Office Action under 35 U.S.C. 103 as being unpatentable over Motoyoshi in view of Daulton. For at least the reasons detailed above in this Final Office Action, the Examiner respectfully submits that amended independent claim 1 is unpatentable under 35 U.S.C. 103 based on Motoyoshi.
As another example, regarding amended independent claim 28, page 13 of the Reply states:
Claims 28 and 40 are rejected as being anticipated by Mao, while Claim 29 (the recitations of which have been included in Claims 28 and 40) are rejected as being unpatentable over Mao. See Office Action, Pages 5 and 31. Claim 28, for example, recites a heterojunction device where "the second portion of the barrier layer comprises a different electrical resistance than the first portions of the barrier layer having the first and second contacts thereon."
The Examiner respectfully disagrees at least because amended independent claim 28 does not recite “a heterojunction device where ‘the second portion of the barrier layer comprises a different electrical resistance than the first portions of the barrier layer having the first and second contacts thereon’”, as argued by Applicant. Rather, amended independent claim 28 recites “[a] semiconductor device, comprising: a semiconductor structure comprising a heterojunction between a channel layer and a barrier layer thereon”. The Examiner respectfully notes that the semiconductor device of amended independent claim 28 is not only a heterojunction device; rather, it a semiconductor device that includes a heterojunction, as well as other separately recited structure and limitations. The Examiner also respectfully notes that amended independent claim 28 does not require that the limitation of “wherein the second portion of the barrier layer comprises a different electrical resistance than the first portions of the barrier layer having the first and second contacts” applies to a heterojunction junction device, as asserted by Applicant. Rather, amended independent claim 28 requires that this limitation applies to first portions and a second portion of the barrier layer which may not be part of the recited heterojunction of amended independent claim 28. For example, this limitation could apply to the “integrated resistor” of amended independent claim 28 that “comprises the second portion of the barrier layer” which is a separately recited structure from the “heterojunction”.
As an additional example, regarding amended independent claim 28, pages 14-15 of the Reply assert that the Office Action has failed to establish a prima facie case of obvious of the rejection of dependent claim 29 as being unpatentable over Mao. For example, page 15 of the Reply states:
In the present rejections, the Office Action merely notes that "the electrical resistance of the second portion can be the same, lower than, or higher than the electrical resistance of the first portions" (Office Action, Page 31), but provides no finding of recognized problem or need, let alone that the same, lower, or higher electrical resistance would provide solutions to such a need.
The Examiner respectfully disagrees for at least the following reasons. For example, the Examiner respectfully notes that the recitations of dependent claim 29 have not be added to claim 28, as asserted by Applicant on page 13 of the Reply. Cancelled dependent claim 29 recited: “The semiconductor device of Claim 28, wherein the portion of the barrier layer is a second portion thereof, and the second portion of the barrier layer has a higher electrical resistance associated therewith than that of first portions thereof adjacent the first and second contacts.” Amended independent claim 28 recites, in part, a different limitation of: “wherein the second portion of the barrier layer comprises a different electrical resistance than the first portions of the barrier layer having the first and second contacts thereon” There are also additional added limitations to amended independent claim 28 that are not part of dependent claim 29 (e.g., “first and second contacts on first portions of the barrier layer”). The Examiner respectfully submits that the above-quoted language of page 15 of Applicant’s reply is inapplicable to amended independent claim 28, as asserted by Applicant, because amended independent claim 28 does not include only the recited limitations of dependent claim 29.
As another example, the Examiner respectfully disagrees that the Office Action failed to establish a prima facie case of obvious of the rejection of dependent claim 29 as being unpatentable over Mao because it “provides no finding of recognized problem or need, let alone that the same, lower, or higher electrical resistance would provide solutions to such a need”. The need is that Mao did not appear to explicitly disclose how to solve the problem of fabricating the semiconductor device thereof such that ”the second portion of the barrier layer has a higher electrical resistance associated therewith than that of first portions thereof adjacent to first and second contacts”. The solution to this problem was clearly articulated by paragraph 86 of the Office Action.
As a further example, regarding amended independent claim 40, page 15 of the Reply states:
Accordingly, Mao fails to disclose or suggest at least the above-highlighted recitations of Claim 28, and the Office Action fails to provide the requisite findings to establish prima facie obviousness. Claim 28 and the claims dependent therefrom are thus patentable for at least these reasons. Amended Claim 40 includes similar recitations, and is thus patentable for at least similar reasons.
The Examiner respectfully submits that amended independent claim 40 is not patentable for at least the reasons detailed above in this Final Office Action. The Examiner also respectfully submits that Applicant’s above-quoted arguments regarding amended independent claim 40 are unresponsive and that he is unable, at this time, to respond further to such arguments without a detailed written explanation by Applicant regarding why these “similar recitations” and “at least similar reasons” distinguish amended independent claim 40 over the rejections in either the Office Action or this Final Office Action.
As another further example, regarding independent claim 15, page 16 of the Reply states:
As such, even if Gentry may disclose a diode structure having sheet resistance in the claimed range, Gentry does not disclose or suggest how one of skill in the art might achieve such a sheet resistance in a semiconductor structure "comprising a heterojunction between first and second semiconductor layers," as recited by Claim 15. Nor does Mao contain any disclosure or suggestion of these recitations, as conceded in the Office Action.
The Examiner respectfully disagrees with this argument at least for the following reasons. For example, Gentry was not relied on in the Office Action and is not being relied on in the Final Office Action for disclosing a “a semiconductor structure ‘comprising a heterojunction between first and second semiconductor layers’”, as argued by Applicant. Rather, Mao is being relied on for disclosing this recited structure. As another example, the Examiner respectfully submits that independent claim 15, does not require that the heterojunction have the recited sheet resistance; rather, independent claim 15 recites that “an integrated resistor in the semiconductor structure” (which is a separately recited structure in independent claim 15) has this recited sheet resistance. As an additional example, the Examiner respectfully notes that Applicant acknowledges that Gentry may disclose a diode structure having a sheet resistance in the claimed range. The Examiner respectfully submits that a diode structure is a semiconductor structure and that one of ordinary skill in the art could apply the teaching of Gentry regarding the sheet resistance range of such a semiconductor structure to the recited semiconductor structure of Mao. Therefore, the Examiner respectfully submits that both the Office Action and this Final Office Action have established a prima facie case of obviousness of Independent claim 15 being unpatentable under 35 U.S.C. 103 based on Mao in view of Gentry.
As an additional further example, regarding independent claim 23, page 18 of the Reply states:
Nowhere, however, does Daulton disclose or suggest using its controlled recess operations to recess the barrier layer 162 “between the first and second contacts,” as recited by Claim 23. That is Daulton at best describes forming the recess under first and second source/drain contacts, rather than in portions of the barrier layer 162 that extend between first and second contacts. Nor do the cited portions or Motoyoshi or Mao disclose or suggest these recitations, as conceded by the Office Action.
The Examiner respectfully disagrees with this argument at least for the following reasons. For example, independent claim 23 does not recite the structure and limitations argued by Applicant, as quoted above. To be clear, independent claim 23 recites: “an integrated resistor comprising a second portion of the barrier layer that extends between the first and second contacts and is recessed in thickness relative to a first portion thereof.” The Examiner respectfully submits that independent claim 23 neither requires using “controlled recessed operations to recess the barrier layer 162” nor that the entire barrier layer or entire portions thereof be recessed in thickness “between the first and second contacts”, as argued by Applicant, above. Independent claim 23 only requires that “an integrated resistor” comprises “a second portion of the barrier layer that extends between the first and second contacts” and that the second portion of the barrier layer “is recessed in thickness relative to a first portion thereof.” There is no requirement in independent claim 23 that the entire second portion of the barrier layer only extend between the first and second contacts.
Additionally, the Examiner respectfully submits that Daulton does in fact, disclose use of a reduced thickness of a semiconductor layer to control resistance, as conceded by Applicant on page 18 of the Reply: “However, Daulton describes that the controlled recess operations shown in FIG. 1C may be used to provide consistent contact resistance for source/drain contacts.” The Examiner respectfully submits that it is t is unclear why at least this conceded teaching of Daulton regarding controlling resistance values via reduced thickness of semiconductor layer (162) cannot be applied to a second portion of barrier layer (16) of Mao (which is also a semiconductor layer) by one of ordinary skill in the art to render the recited invention of independent claim 23 obvious under 35 U.S.C. 103 based on Mao in view of Daulton. The Examiner respectfully submits that Applicant’s remarks regarding independent claim 23 appear to be an argument against the Mao and Daulton references individually, rather than what the combined teachings of these prior art references would have suggested to a person of ordinary skill in the art. Please see, MPEP 2145(IV).
As a still further example, regarding amended independent claim 31, page 19 of the Reply states:
Claim 31, as amended, similarly recites operations to "recess a thickness of a second portion of the second semiconductor layer relative to first portions thereof' and "forming first and second contacts on the first portions...wherein the second portion... extends between the first and second contacts and comprises an integrated resistor that electrically connects the first and second contacts," and is thus patentable for at least similar reasons.
The Examiner respectfully submits that amended independent claim 31 is not patentable for at least the reasons detailed above in this Final Office Action and, perhaps, one or more of the reasons discussed above regarding independent claim 23. The Examiner also respectfully submits that Applicant’s above-quoted arguments regarding amended independent claim 31 are unresponsive and that he is unable, at this time, to respond further to such arguments without a detailed written explanation by Applicant regarding why these recitations and “at least similar reasons” distinguish amended independent claim 31 over the rejections in either the Office Action or this Final Office Action.
As still yet another further example, regarding Applicant’s dependent claims, page 20 of the Reply states:
As each of the dependent claims depends from a base claim that is believed to be in condition for allowance, Applicant does not believe that it is necessary to argue the allowability of each of these claims individually. Applicant does not necessarily concur with the interpretation of these claims, or with the bases for rejection set forth in the Office Action. Applicant therefore reserves the right to address the patentability of these claims individually as necessary in the future.
The Examiner respectfully submits that this argument is non-responsive to the several detail rejections of the dependent claims of the Application in both the Office Action and this Final Office Action. The Examiner also respectfully submits that this non-responsive argument neither provides clarity of the written record by clearly articulating for the benefit of the public why “Applicant does not necessarily concur with the interpretation of these claims, or with the bases for rejection [of the dependent claims] set forth in the Office Action” nor does it provide the Examiner with an opportunity to respond to such arguments also for clarity of the written record.
Notwithstanding the above, in an effort to advance prosecution, the Examiner respectfully requests that Applicant please consider initiating a telephone interview with the Examiner to discuss amendments that Applicant would like to propose to overcome the rejection of claims 1-28, 30, 31, and 40 in this Final Office Action prior to submitting a written response thereto. The Examiner would welcome such a conversation and is available at the telephone number indicated below.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to Erik A. Anderson whose telephone number is (703) 756-1217. The Examiner can normally be reached Monday-Friday 8:30 a.m.-4:30 p.m. (Pacific Time Zone).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, William B. Partridge, can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/ERIK A. ANDERSON/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
1 Please see, for example, US 2014/0091311 A1 (Jeon) which discloses that it is well-known to one of ordinary skill in the art before the effective filing date of the claimed invention that semiconductor resistors are passive devices ([0042]).
2 Please see the rejection of amended independent claim 31 under 35 U.S.C. 112(b), above, for how this recited language of amended independent claim 31 is being interpreted for purpose of examination.