Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over Su et al US 20210376076 A1 in view of Cheng et al US 20220052206 A1. Su et al and Cheng et al will be referenced to as Su and Cheng respectively henceforth.
Regarding Claim 1,
Su teaches:
“A semiconductor structure comprising:
a field effect transistor (FET) comprising:
a source / drain (S/D) epitaxy (semiconductor material layers, [0063], FIG. 29A);
and a metal gate (gate electrodes 124, [0074], FIG. 29A: The gate electrodes may include cobalt.); a backside epitaxy in electrical contact with the S/D epitaxy (semiconductor material layers 106B, [0063], FIG. 29A), wherein the backside epitaxy comprises a highly doped epitaxy ([0061],[0063], FIG. 29A, 106B has a higher dopant concentration than 106A. 106 may have a dopant concentration in the range of 1019 cm----3 to 1021 cm-3. Therefore, one of ordinary skill in the art would consider choosing a concentration of 106B to be about 1021 cm-3.); and a backside power distribution network in electrical contact with the backside contact (conductive features 172, [0106], FIG. 29A-C: 172 routes electrical signals and delivers power to the power rail contacts 74 which are in electrical contact with 138.)”
Su doesn’t substantially teach:
“a backside contact in electrical contact with the backside epitaxy; wherein the backside contact is in direct contact with multiple surfaces of the backside epitaxy such that the backside contact wraps around the backside epitaxy;”
However, Cheng teaches:
“a backside contact in electrical contact with the backside epitaxy (Cheng: backside conductive features 378, [0037], [0060-0061], annotated FIG. 21D); wherein the backside contact is in direct contact with multiple surfaces of the backside epitaxy such that the backside contact wraps around the backside epitaxy (Cheng: backside conductive features 378, [0037], [0060-0061], annotated FIG. 21D: source/drain features 260B are formed epitaxially. A portion of 260B is embedded in dielectric layer 376 which is formed at the backside of the device. Therefore, this portion of 260B is a backside epitaxy. 378 is in direct contact and wraps around the backside epitaxy. 378 is in direct contact with multiple sides of the backside epitaxy. The multiple sides of the backside epitaxy includes two curved sides which lie at the ends of a third flat side.”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Su is modifiable in view of Cheng by modifying Su’s frontside and backside contacts in view of Cheng’s teaching.
This is because Cheng teaches that its backside contact and frontside contact geometry provides the benefit of providing more freedom to metal routing in the frontside therefore enhancing the packing density for GAA (gate all around) devices. The invention of Su is a GAA device. One of ordinary skill in the art would recognize that increasing the packaging density of a device is beneficial as higher packaging density leads to greater computationally power.
PNG
media_image1.png
720
1014
media_image1.png
Greyscale
Annotated FIG. 21D #1
Regarding Claim 2,
Su/Cheng teaches:
“The semiconductor structure of claim 1, wherein the semiconductor structure comprises a gate-all-around device (Su: [0011], FIG. 1: The NanoFETs in FIGs. 29A-C may be gate-all-around FETS. The nanoFETS together comprise a gate-all-around device.). ”
Regarding Claim 3,
Su/Cheng teaches:
“The semiconductor structure of claim 2, wherein the gate-all-around device comprises a stacked FET device comprising the FET (Su: FIG. 1: FIG. 1 shows a stack of nanosheet transistors. The nanosheet transistors are FETs.).”
Regarding Claim 5,
Su/Cheng teaches:
“The semiconductor structure of claim 2, wherein the gate-all-around device comprises a forksheet device comprising the FET (Su: [0011], FIG.1, FIGS. 29A-C).”
Regarding Claim 6,
Su/Cheng teaches:
“The semiconductor structure of claim 1, wherein the backside epitaxy comprises a p-type epitaxy (Su: [0061]: 106, and therefore 106b, may be p-type. 106 may be in situ doped during growth.).”
Regarding Claim 7,
Su/Cheng teaches:
“The semiconductor structure of claim 1, wherein the backside epitaxy comprises an n-type epitaxy (Su: [0061]: 106, and therefore 106b, may be n-type. 106 may be in situ doped during growth.)”
Regarding Claim 8,
Su/Cheng teaches:
“The semiconductor structure of claim 1, wherein the highly doped epitaxy comprises a doping concentration greater than 1 x 1021 (Su: [0061]: 106, and therefore 106b, may be doped to a concentration of about 1 x 1021. The word, “about” indicates a doping concentration of more or less 1 x 1021. Therefore, a doping concentration of more than 1 x 1021 is anticipated.).”
Claims 9-11 and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Su/Cheng as applied to claims 1-3 and 5-8 above, and further in view of Block et al US 20200035560 A1. Block et al will be referenced to as Block henceforth.
Regarding Claim 9,
Su/Cheng teaches:
“The semiconductor structure of claim 1,”
Su/Cheng doesn’t substantially teach:
“wherein the backside epitaxy comprises a polygon shape that is lattice-matched .”
However, Block teaches:
“wherein the backside epitaxy comprises a polygon shape that is lattice-matched (Block: epitaxial growth or deposition of p-type or n-type impurity-doped back-side source/drain semiconductor 1640, [0181], FIG. 16C: Epitaxially grown semiconductor materials are necessarily lattice-matched. 1640 is rectangular and therefore a polygon.).”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Su/Cheng is modifiable in view of Block.
This is because Su teaches a S/D epitaxial growth that is lattice matched. Su/Cheng doesn’t substantively teach a S/D epitaxial growth comprising a polygon shape. Block teaches a S/D epitaxial growth that is lattice matched. Block further teaches a S/D epitaxial growth that is lattice matched and which comprises a polygon shape. Because both Su/Cheng and Block have a S/D epitaxial growth that is lattice matched, one of ordinary skill in the art would have deemed it obvious to substitute the S/D epitaxial growth that is lattice matched of Su/Cheng for the S/D epitaxial growth that is lattice matched and which comprises a polygon shape of Block for the predictable result of a S/D epitaxial growth that is lattice matched and therefore has fewer defects compared to a S/D region which is not epitaxially grown.
Regarding Claim 10,
Su/Cheng/Block teaches:
“A semiconductor structure comprising:
a gate-all-around device (Su: [0011], FIG. 1: The nanoFETs in FIGs. 29A-C may be gate-all-around FETS. The nanoFETS together comprise a gate-all-around device.) comprising:
a field effect transistor (FET) (Su: FIG. 1: each nanoFET is a FET.) comprising:
a source / drain (S/D) epitaxy (Su: semiconductor material layers, [0063], FIG. 29A);
and a metal gate (Su: gate electrodes 124, [0074], FIG. 29A: The gate electrodes may include cobalt);
a backside epitaxy in electrical contact with the S/D epitaxy (Su: semiconductor material layers 106B, [0063], FIG. 29), wherein the backside epitaxy comprises a highly doped epitaxy (Su: [0061],[0063], FIG. 29A, 106B has a higher dopant concentration than 106A. 106 may have a dopant concentration in the range of 1019 cm----3 to 1021 cm-3. Therefore, one of ordinary skill in the art would consider choosing a concentration of 106B to be about 1021 cm-3.), wherein the backside epitaxy comprises a polygon shape (Block: epitaxial growth or deposition of p-type or n-type impurity-doped back-side source/drain semiconductor 1640, [0181], FIG. 16C: Epitaxially grown semiconductor materials are necessarily lattice-matched. 1640 is rectangular and therefore a polygon.);
a backside contact in electrical contact with the backside epitaxy (Cheng: backside conductive features 378, [0037], [0060-0061], annotated FIG. 21D), wherein the backside contact is in direct contact with multiple surfaces of the backside epitaxy such that the backside contact wraps around the backside epitaxy (Cheng: backside conductive features 378, [0037], [0060-0061], annotated FIG. 21D: source/drain features 260B are formed epitaxially. A portion of 260B is embedded in dielectric layer 376 which is formed at the backside of the device. Therefore, this portion of 260B is a backside epitaxy. 378 is in direct contact and wraps around the backside epitaxy. 378 is in direct contact with multiple sides of the backside epitaxy. The multiple sides of the backside epitaxy includes two curved sides which lie at the ends of a third flat side.);
and a backside power distribution network in electrical contact with the backside contact (Su: conductive features 172, [0106], FIG. 29A-C: 172 routes electrical signals and delivers power to the power rail contacts 74 which are in electrical contact with 138.).”
Regarding Claim 11,
Su/Cheng/Block teaches:
“The semiconductor structure of claim 10, wherein the gate-all-around device comprises a stacked FET device comprising the FET (Su: FIG. 1: FIG. 1 shows a stack of nanosheet transistors. The nanosheet transistors are FETs.).”
Regarding Claim 13,
Su/Cheng/Block teaches:
“The semiconductor structure of claim 10, wherein the gate-all-around device comprises a forksheet device comprising the FET (Su: [0011], FIG.1, FIGS. 29A-C).”
Regarding Claim 14,
Su/Cheng/Block teaches:
“The semiconductor structure of claim 10, wherein the backside epitaxy comprises a p-type epitaxy (Su: [0061], 106, and therefore 106b, may be p-type. 106 may be in situ doped during growth.).”
Regarding Claim 15,
Su/Cheng/Block teaches:
“The semiconductor structure of claim 10, wherein the backside epitaxy comprises an n-type epitaxy (Su: [0061], 106, and therefore 106b, may be n-type. 106 may be in situ doped during growth.).”
Regarding Claim 16,
Su/Cheng/Block teaches:
“The semiconductor structure of claim 10, wherein the highly doped epitaxy comprises a doping concentration greater than 1 x 1021 (Su: [0061], 106, and therefore 106b, may be doped to a concentration of about 1 x 1021. The word, “about” indicates a doping concentration of more or less 1 x 1021. Therefore, a doping concentration of more than 1 x 1021 is anticipated.).”
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Su/Cheng as applied to claims 1-3 and 5-8 above, and further in view of Anderson et al US 20170244412 A1. Anderson et al will be referenced to as Anderson henceforth.
Regarding Claim 4,
Su/Cheng teaches:
“The semiconductor structure of claim 2,”
Su/Cheng doesn’t substantially teach:
“wherein the gate-all-around device comprises a vertical transport FET device comprising the FET.”
However, Anderson teaches:
“wherein the gate-all-around device comprises a vertical transport FET device comprising the FET (Anderson: [0015], FIG. 1).”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Su/Cheng is modifiable in view of Anderson.
This is because the invention of Su may be used in logic circuits (Su: [0092]).The invention of Anderson may provide improved circuit density for devices containing logic circuits (Anderson: [0007]). Therefore, one of ordinary skill in the art would have recognized the invention of Anderson provides the invention of Su with the improvement of increased circuit density which in turn increases the computational power of a device while maintaining a same footprint.
Claims 12 is rejected under 35 U.S.C. 103 as being unpatentable over Su/Cheng/Block as applied to claims 9-11 and 13-16 above, and further in view of Anderson.
Regarding Claim 12,
Su/Cheng/Block teaches:
“The semiconductor structure of claim 10,”
Su/Cheng/Block doesn’t substantially teach:
“wherein the gate-all-around device comprises a vertical transport FET device comprising the FET.”
However, Anderson teaches:
“wherein the gate-all-around device comprises a vertical transport FET device comprising the FET (Anderson: [0015], FIG. 1).”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Su/Cheng /Block is modifiable in view of Anderson.
This is because the invention of Su may be used in logic circuits (Su: [0092]).The invention of Anderson may provide improved circuit density for devices containing logic circuits (Anderson: [0007]). Therefore, one of ordinary skill in the art would have recognized the invention of Anderson provides the invention of Su with the improvement of increased circuit density which in turn increases the computational power of a device while maintaining a same footprint.
Response to Arguments
Applicant’s amendments to the Claims have overcome the Examiner’s 102(a)(1) and 103 rejections.
Though element 138 of Su is no longer relied upon by the Examiner due to the Applicant’s amendments, the Applicant has asked the Examiner to further clarify how Su’s backside epitaxy is in contact with element 138. To clarify, the Examiner has provided the following annotated figures:
PNG
media_image2.png
660
790
media_image2.png
Greyscale
Annotated FIG. 29A #1
PNG
media_image3.png
828
784
media_image3.png
Greyscale
Annotated FIG. 29C
In annotated FIG. 29A #1, 138 is in direct contact with 106a. 106a is in direct contact with 106B. Because 138 is conductive and 106a and 106b are semiconductive, 138 is in electrical contact with 106b.
In annotated FIG. 29C #1, the Examiner labels 108b which is not labeled by Su. As noted in the interview, the line segment which delineates the location of 106b is missing in the Applicant’s reproduction of FIG. 29C. It is clear to one of ordinary skill in the art that the Examiner’s label of 106b in FIG. 29C is accurate due to the relative location of 106b relative to 138 and 162. Namely that the relative positions have been maintained.
The Applicant also makes arguments relating to a reference named, “Cheng”. Prior to this office action, the Examiner has not made use of a reference named Cheng. Further, Applicant’s claims make no reference to a dielectric bar. For these reasons, the Examiner finds these arguments non-substantive.
Applicant’s other arguments, with respect to the rejections of the claims have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground of rejection is made in view of Cheng.
In the interest of compact prosecution, if the Applicant were to amend an independent claim with the following limitation:
“wherein the backside epitaxy is surrounded by both a first dielectric layer and a second dielectric layer”
Or
“a first dielectric layer, wherein the first dielectric layer surrounds the backside contact; wherein the backside epitaxy does not directly contact the first dielectric layer”
It would overcome the current rejections for the independent claims. The Examiner is available for interview at Applicant’s convenience for discussion of claim amendments.
Conclusion
The prior arts made of record and not relied upon are US 20220122971 A1, US 20210366916 A1, US 20230377985 A, US 20240194567 A1 1 and considered pertinent to applicant's disclosure. This is because these references show a source/drain region wrapped by a contact.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDRE XAVIER RAMIREZ whose telephone number is (571)272-2715. The examiner can normally be reached Monday - Friday 8:30 AM to 6:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ALEXANDRE X RAMIREZ/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
Prosecution Insights