DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Claims 1-20 are pending in the application. No claims have been amended. No claims have been canceled. Claims 4 and 9-20 have been withdrawn per the 3/24/2026 restriction election (see below). No new claims have been added.
Election/Restrictions
Claims 4 and 9-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 3/24/2026.
Applicant’s election of Species A in the reply filed on 3/24/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). There appear to be a few typos in the reply of 3/24/2026, so Examiner is unsure if the statement “with traverse” is also in error, as no arguments were stated.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/20/2023 and 1/7/2026 is being considered by the examiner.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required: Claims 1-3 and 5-8 rely on a nanosheet layer, but the specification fails to define what the nanosheet layer is. While the nanosheet layer is referenced in the specification, there is no element associated with it. It appears as though the nanosheet stack is in reference to solely the doped epitaxial structure, as no nanosheets are defined, and an epitaxial structure is not known in the art as a nanosheet layer in itself. For the purposes of examination, please see annotated Species A of Fig. 1A of the present application for Examiner’s interpretation of “nanosheet layer”, which will be defined to be the epitaxial structures and the channels between them.
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Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the a first nanosheet layer and a second nanosheet layer must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 8 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 8 recites the limitation "the stacked FET" in line 1. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, claim 8 will be interpreted to read “The semiconductor structure of claim 7”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-3 and 5-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong et al. (US 2023/0092061 A1, hereafter Hong) in view of Cheng et al. (US 2018/0102359 A1, hereafter Cheng).
Regarding claim 1, Fig. 10 of Hong teaches a semiconductor structure (140, [0046]) comprising:
a protection diode (see annotated Fig. 10), the protection diode comprising:
a substrate (10, [0021]);
a gate (24_1, [0027]);
a first nanosheet layer (see annotated Figs. 7 (referenced) and 10), comprising a doped n-type epitaxial (26U_1, [0023]) disposed over the substrate (10), wherein the first nanosheet layer is in contact with the gate (24_1);
a second nanosheet layer (see annotated Figs. 7 (referenced) and 10) comprising a doped p-type epitaxial (26L_1, [0023]) disposed over the substrate (10), wherein the second nanosheet layer is in contact with the gate (24_1), and wherein the first nanosheet layer and the second nanosheet layer surround the gate (24) (shown in Fig. 7).
Hong is silent on the doping level of the n-type epitaxial and the p-type epitaxial. However Cheng teaches a similar diode structure with a varying doping level of the epitaxial source/drain structures (114, [0032]) depending on the diode fabrication requirements [0032]. The doping of the epitaxial source/drain structures can be up to 2E21/cm3, which is known in the art to be heavily doped. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the doping of the epitaxial structures of Hong to be heavily doped as taught by Cheng to get the expected result of lower resistance in the diode.
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Regarding claim 2, Hong in view of Cheng teach the semiconductor structure (140, [0046]) of claim 1. In Fig. 10 Hong further teaches the first nanosheet layer (see annotated Figs. 7 (referenced) and 10) is disposed over the second nanosheet layer (see annotated Figs. 7 (referenced) and 10).
Regarding claim 3, Hong in view of Cheng teach the semiconductor structure (140, [0046]) of claim 2. In Fig. 10 Hong further teaches the first nanosheet layer (see annotated Figs. 7 (referenced) and 10)is in contact with the second nanosheet layer (see annotated Figs. 7 (referenced) and 10).
Regarding claim 5, Hong in view of Cheng teach the semiconductor structure (140, [0046]) of claim 1. In Fig. 10 Hong further teaches a first epitaxial contact (32_2, [0025]) in electrical contact with the first nanosheet layer (see annotated Figs. 7 (referenced) and 10).
Regarding claim 6, Hong in view of Cheng teach the semiconductor structure (140, [0046]) of claim 1. In Fig. 10 Hong further teaches a second epitaxial contact (32_1, [0025]) in electrical contact with the second nanosheet layer (see annotated Figs. 7 (referenced) and 10).
Claim(s) 7 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong in view of Cheng as applied to claim 6 above, and further in view of Curatola et al. (US 2024/0079233 A1, hereafter Curatola).
Regarding claim 7, Hong in view of Cheng teach the semiconductor structure (140, [0046]) of claim 6. In Fig. 10, Hong further teaches a stacked field effect transistor (FET) (see annotated Fig. 10.).
Hong in view of Cheng are silent on a metal line in electrical contact with the first epitaxial contact and the stacked FET. However in Fig. 4B, Curatola teaches a contact bridge 408A between contacts creating an electrical connection between a FET and a diode (see annotated Fig. 4B). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Hong in view of Cheng to include the contact bridge of Curatola to act as an electrode contact terminal to allow for current transfer as taught by Curatola [0111].
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Regarding claim 8, Hong in view of Cheng and in further view of Curatola teach the semiconductor structure (140, [0046]) of claim 7. In Fig. 10, Hong further teaches the stacked FET (see annotated Fig. 10) comprises an n-type FET and a p-type FET ([0029-0030] describe the lower semiconductor layer 26L_3 can have the first conductivity (p-type) and the upper semiconductor layer 26U_3 can have the second conductivity type (n-type), thus making the stacked FET comprise n-type FET and a p-type FET).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMMANTHA K SALAZ whose telephone number is (571)272-2484. The examiner can normally be reached Monday - Friday 8:00am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at 571-272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SAMMANTHA K SALAZ/Examiner, Art Unit 2892
/LEX H MALSAWMA/Primary Examiner, Art Unit 2892