DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-3, 5, 7, and 8 have been considered but are moot in view of the new ground of rejection.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 5, 7, and 8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nagao et al. (US PGPub 2016/0379992; hereinafter “Nagao”).
Re claim 1: Nagao teaches (e.g. figs. 1, 2, 3A, 4 and labeled fig. 2 below) a semiconductor device comprising: a semiconductor layer (28) having a first face (upper surface of 28; hereinafter “1F”) and a second face (lower surface of 28; hereinafter “2F”) facing the first face (1F); a first electrode (source pad 6; e.g. paragraph 64) provided on a side of the first face (1F) of the semiconductor layer (28); a second electrode (drain electrode would be provided on shared drain region 28; e.g. paragraph 84) provided on a side of the second face (2F) of the semiconductor layer (28); a gate electrode (gate electrodes 19; e.g. paragraph 70) provided on the side of the first face (1F) of the semiconductor layer (28); an electrode pad (gate pad 4; e.g. paragraph 54) being provided on the side of the first face (1F) of the semiconductor layer (28); a wiring layer (gate finger 5; e.g. paragraph 65) provided on the side of the first face (1F) of the semiconductor layer (28) and electrically connected to the gate electrode (23); a plurality of first polycrystalline silicon layers (gate polysilicon layer 19 and built-in resistance 21 formed from p-type polysilicon; e.g. paragraph 94) provided on the side of the first face (1F) of the semiconductor layer (28), the first polycrystalline silicon layers (21) electrically connected to the electrode pad (4) and the wiring layer (5), each of the first polycrystalline silicon layers (21) extending in a first direction (left-right direction of fig. 2; hereinafter “1D”) parallel to the first face (x-y plane of 1F), the plurality of first polycrystalline silicon layers (21) being arranged (two 21 are disposed on the right side of gate pad 4 as can be seen in fig. 2) in a second direction (up-down direction of fig. 2; hereinafter “2D”) perpendicular to the first direction (1D) and parallel to the first face (1F); and an insulating layer (36) provided between the first polycrystalline silicon layers (21) and the electrode pad (4) and between the first polycrystalline silicon layer (21) and the wiring layer (5), the insulating layer (36) having at least one first opening (opening for pad-side contact 22 within 36 to make contact with 21; hereinafter “1H”) between the electrode pad (4) and each of the first polycrystalline silicon layers (21) and at least one second opening (opening for 23 within 36 to make contact with 21; hereinafter “2H”) between the wiring layer (5) and each of the first polycrystalline silicon layers (21), wherein the electrode pad (4) and each of the first polycrystalline silicon layer (21) are electrically connected via an inside of the at least one first opening (1H), the wiring layer (5) and each of the first polycrystalline silicon layers (21) are electrically connected via an inside of the at least one second opening (2H), a first opening area (area of 1H; hereinafter “1OA”) of the at least one first opening (1H) is larger (in order to decrease the resistance value, the pad-side contact 22 can be made larger; e.g. paragraph 112, therefore opening of 1OA is larger in the x-direction than the opening of 2OA) than a second opening area (area of 2H; hereinafter “2OA”) of the at least one second opening (2H), an area (area of 4 as shown in fig. 1) of the electrode pad (4) is larger than an area (area of 5 as shown in fig. 1) of the wiring layer (5), the wiring layer (5) includes a first portion (portion of 5 labeled “1P”) that is adjacent to the electrode pad (4) extends along the electrode pad (4) in the second direction (2D) and a second portion (portion of 5 labeled “2P”) that is adjacent to the first electrode (6) and extends along the first electrode (6) in the first direction (1D), and the first portion (1P) of the wiring layer (5) and each of the first polycrystalline silicon layers (21) are electrically connected via an inside of the at least one second opening (2H).
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Re claim 2: Nagao teaches the semiconductor device according to claim 1, wherein a length of each of the first polycrystalline silicon layer (21) in the first direction (1D) is 200 µm or more (resistor 21 is a size of 200µm x 200µm or less when viewed planarly; e.g. paragraph 76; therefore it is contemplated that 21 has a dimension of 200µm in the first direction 1D), and a width of the first polycrystalline silicon layer (21) in the second direction (2D) is 50 µm or less (resistor 21 is a size of 200µm x 200µm or less when viewed planarly; e.g. paragraph 76; therefore it is contemplated that 21 has a dimension less than 50µm in the second direction 2D).
Re claim 5: Nagao teaches the semiconductor device according to claim 1, wherein the electrode pad (4) is in contact with each of the first polycrystalline silicon layers (21), and the wiring layer (5) is in contact with each of the first polycrystalline silicon layers (21).
Re claim 7: Nagao teaches the semiconductor device according to claim 1, wherein each of the first polycrystalline silicon layers (21) contains p-type impurities or n-type impurities (gate polysilicon layer 19 and built-in resistance 21 formed from p-type polysilicon; e.g. paragraph 94).
Re claim 8: Nagao teaches the semiconductor device according to claim 1, wherein the semiconductor layer (28) is a silicon carbide layer (SiC; e.g. paragraph 52).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nagao as applied to claim 1 above, and further in view of Okumura (US PGPub 2020/0091339).
Re claim 3: Nagao is silent as to explicitly teaching the semiconductor device according to claim 1, wherein the first opening area (1OA) is twice or more the second opening area (2OA).
Okumura teaches (e.g. fig. 2) the semiconductor device according to claim 1, wherein the first opening area (opening area for 33) is twice or more the second opening area (opening area for 31 which contacts resistor 14).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the more than twice as large an opening area for the pad contact than the gate finger contact as taught by Okumura in the device of Nagao in order to have the predictable result of relying on the resistor to be effective as setting the total impedance, therefore a more accurate impedance can be achieved between the pad and finger.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JESSE Y MIYOSHI whose telephone number is (571)270-1629. The examiner can normally be reached M-F, 8:30AM-5:00PM.
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/JESSE Y MIYOSHI/
Primary Examiner, Art Unit 2898
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