Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/20/2023, 7/19/2024, 12/2/2024, and 8/21/2025 were filed before the mailing date of the Non-final rejection on 2/21/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The formal drawings filed on 6/20/2023 have been approved by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “ PACKAGE MODULE WITH A PLURALITY OF STACKED SUBSTRATES HAVING MULTIPLE POWER CHIPS ”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
Claims 1, 7, 8, 11, 12, and 19 are rejected under 35 U.S.C. 102(a)(2) as being clearly anticipated by Niu et al. (US 11,139,278).
With respect to Claim 1, Niu teaches a positive input electrode 1, a negative input electrode 2, an upper bridge substrate 1, a lower bridge substrate 5, an upper bridge chip 6, a lower bridge chip 8 an output electrode 3, and a signal transmission terminal 10. The upper bridge substrate 1, the upper bridge chip 6, the lower bridge chip 8, 9, and the lower bridge substrate 5 are stacked in sequence. The upper bridge chip 6 (i.e. IGBT) has a collector connected to the upper bridge substrate and an emitter connected to the output electrode. The lower bridge chip 8 (i.e. IGBT) has a collector electrically connected to the output electrode. A sampling terminal 11 at the emitter of the upper bridge chip and a sampling terminal electrically connected at the collector of the upper bridge chip. A control terminal 10 (i.e. one of the terminals) of the upper bridge chip. A sampling terminal electrically connected to an emitter of the lower bridge chip 8. A sampling terminal 11 at the collector of the lower bridge chip. A control terminal 10 of the lower bridge chip are connected to the signal transmission terminal 10, the positive input electrode is connected to the upper bridge substrate, and the negative input electrode 2 is connected to the lower bridge substrate 5 (see col. 3 lines 5-40, col. 4 lines 10-30, col. 9 lines 35-67, col. 11 lines 18-67, and col. 12 lines 1-50; Figs. 7, 14, 15-20).
With respect to Claim 7, Niu teaches the upper bridge chip 6, the output
electrode, and the lower bridge chip 8 are stacked in sequence (see Figs. 7, 14, 15-20).
With respect to Claim 8, Niu teaches a first connection layer, wherein the collector of the upper bridge chip is connected to the upper bridge substrate through the first connection layer (see Figs. 7, 14, 15-20).
With respect to Claim 11, Niu teaches the upper bridge chip 6 and the lower
bridge chip both are arranged in a lateral direction (see Figs. 7, 14, 15-20).
With respect to Claim 12, Niu teaches the upper bridge chip and the lower
bridge chip both are arranged in a longitudinal direction (see Figs. 7, 14, 15-20).
With respect to Claim 19, Niu teaches a sampling terminal 11 at the emitter of
the upper bridge chip 6, a sampling terminal at the collector of the upper bridge chip, and the control terminal of the upper bridge chip. A sampling terminal 11 at the emitter of the lower bridge chip, a sampling terminal at the collector of the lower bridge chip 8, and the control terminal of the lower bridge chip are all connected to the signal transmission terminal through their respective bonding wires (see col. 10 lines 1-30; Figs. 7, 14, 15-20).
Allowable Subject Matter
8. Claims 2-6, 9, 10, and 13-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowance subject matter: none of the prior art of record teaches or suggest the combination an upper bridge buffer block and a third connection layer. The upper bridge chip, the upper bridge buffer block, and the lower bridge chip are stacked, the upper bridge chip is connected to the upper bridge buffer block through the third connection layer. The emitter of the upper bridge chip is connected to the output electrode through the upper bridge buffer block in claim 2.
A thermistor and a thermistor terminal, wherein the thermistor is connected to the thermistor terminal through its bonding wire in claim 9.
The prior art made of record and not relied upon is cited primarily to show the product of the instant invention.
Conclusion
9. Any inquiry concerning the communication or earlier communications from the examiner should be directed to Alonzo Chambliss whose telephone number is (571) 272-1927.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jacob Y. Choi can be reached on (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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AC/February 21, 2026 /Alonzo Chambliss/
Primary Examiner, Art Unit 2897