DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/03/2026 has been entered.
Response to Amendment
The Amendment filed on 04/28/2026 has been entered. Claims 1-20 remain pending in the application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 5, 6, 8-12, 14 and 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Kuriki (Japanese Patent Application Publication Number JP 2019096741 A) hereinafter referenced as Kuriki, in view of Jiang, (United States Patent Application Publication Number, US 2019/0386185 A1) hereinafter referenced as Jiang and in view in of Waragaya et al., (United States Patent Application Publication Number, US 2012/0236582 A1) hereinafter referenced as Waragaya.
Regarding claim 1, Kuriki teaches a semiconductor package, comprising: a package substrate (Fig.3B, element #10) ; a first semiconductor chip and a second semiconductor chip on the package substrate in adjacent, spaced-apart relationship along a horizontal direction (Fig.3B, the two leftmost elements #32); a plurality of bonding wires coupled to the first semiconductor chip (Fig.3B, the leftmost element #32 has two wires); a first molding member on the package substrate and covering the first semiconductor chip and the second semiconductor chip (Fig.1A, element #42), wherein the first molding member comprises a first molding portion arranged above, along a vertical direction extending from the package substrate orthogonal to the horizontal direction, the plurality of bonding wires and on the first semiconductor chip and a second molding portion arranged above, along the vertical direction, the plurality of bonding wires and between the first and second semiconductor chips (Fig.1B, element #42 has a first molding portion above the wires of the first semiconductor chip, the leftmost element #32, and a second portion between the first semiconductor chip and the second semiconductor chip, the second leftmost element #32), and wherein the first molding portion and the second molding portion are arranged at a same height above the package substrate (the two portions above the wires can be selected to be at the same height).
Kuriki does not teach, wherein a ratio per unit volume of a filler material included in the first molding portion is greater than a ratio per unit volume of the filler material included in the second molding portion. Jiang teaches wherein the first molding member (Fig.4J, element #120) comprises a first molding portion arranged above, along a vertical direction extending orthogonal to the horizontal direction, the plurality of bonding wires and on the first semiconductor chip and a second molding portion arranged above, along the vertical direction, the plurality of bonding wires and between the first and second semiconductor chips (Fig.4L, element #120 has a first molding portion above the wires of the first semiconductor chip, element #142 third from the right, and a second portion between the first semiconductor chip and the second semiconductor chip, element #142 on the right side of region #104) and wherein the first molding portion and the second molding portion are arranged at a same height above the package substrate (portions above the wires can be selected to be at the same height) and a ratio per unit volume of a filler material included in the first molding portion is greater than a ratio per unit volume of the filler material included in the second molding portion (Fig.4J, molding material in region #102 has a first filler, which is not present in region #130 between the chips, paragraph [0169] and paragraph [0171], rows 1-5). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Jiang and disclose wherein the first molding member comprises a first molding portion arranged above, along a vertical direction extending from the package substrate orthogonal to the horizontal direction, the plurality of bonding wires and on the first semiconductor chip and a second molding portion arranged above, along the vertical direction, the plurality of bonding wires and between the first and second semiconductor chips, and wherein the first molding portion and the second molding portion are arranged at a same height above the package substrate and a ratio per unit volume of a filler material included in the first molding portion is greater than a ratio per unit volume of the filler material included in the second molding portion. As disclosed by Jiang, the two portions can have different functions and be optimized according to their function (paragraph [0169], rows 1-10).
The combination of Kuriki and Jiang does not disclose a second molding member on the first molding member. Waragaya teaches a second molding member on the first molding member (Fig.2b, element #14 can be made of resin, paragraph [0067], rows 6-8 and in on the first molding member, element #13). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Waragaya and disclose a second molding member on the first molding member. As disclosed by Waragaya, the top surface of the second molding can act as a light emitting surface, improving light emitting efficiency (paragraph [0061]).
Regarding claim 2, the combination of Kuriki, Jiang and Waragaya teaches the semiconductor package of claim 1 as set forth in the obviousness rejection. Jiang further teaches the semiconductor package of claim 1, wherein an average particle size of the filler material included in the first molding portion is greater than an average particle size of the filler material included in the second molding portion (since no filler is present in the second molding portion the limitation is satisfied).
Regarding claim 5, the combination of Kuriki, Jiang and Waragaya teaches the semiconductor package of claim 1 as set forth in the obviousness rejection. Jiang further teaches the semiconductor package of claim 1, wherein the first molding member further comprises a third molding portion on the second semiconductor chip, and wherein a ratio per unit volume of the filler material included in the third molding portion is greater than the ratio per unit volume of the filler material included in the second molding portion (Fig.4J, both the first and second chip are encapsulated in the same molding composition, in same region #102, therefore the same arguments as noted in claim 1 apply).
Regarding claim 6, the combination of Kuriki, Jiang and Waragaya teaches the semiconductor package of claim 1 as set forth in the obviousness rejection. Waragaya further teaches the semiconductor package of claim 1, wherein the second molding member covers an entire upper surface of the first molding member (Fig.2b, element #14, covers the entire upper surface of a first molding member, element #13). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Waragaya and disclose wherein the second molding member covers an entire upper surface of the first molding member. As disclosed by Waragaya, the second molding can increase light emission (paragraph [0061], rows 7-10).
Regarding claim 8, the combination of Kuriki, Jiang and Waragaya teaches the semiconductor package of claim 1 as set forth in the obviousness rejection. Waragaya further teaches the semiconductor package of claim 1, wherein the second molding member comprises a same material as the first molding member (both can comprise silicone resin paragraph [0054], rows 5-8 and, paragraph [0067], rows 7-9). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Waragaya and disclose wherein the second molding member comprises a same material as the first molding member. Using same material simplifies the manufacturing process (same tools can be used for both).
Regarding claim 9, the combination of Kuriki, Jiang and Waragaya teaches the semiconductor package of claim 1 as set forth in the obviousness rejection. Waragaya further teaches the semiconductor package of claim 1, wherein the second molding member comprises a material different from a material of the first molding member (first molding member, element #13, can be silicone resin paragraph [0054], rows 5-8 and the second molding member can be an epoxy resin, paragraph [0067], rows 7-9). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Waragaya and disclose wherein the second molding member comprises a material different from a material of the first molding member. The two molding members may have different functions and each can be optimized separately for its specific purpose.
Regarding claim 10, the combination of Kuriki, Jiang and Waragaya teaches the semiconductor package of claim 1 as set forth in the obviousness rejection. Waragaya further teaches the semiconductor package of claim 1, wherein a thermal conductivity of the second molding member is greater than a thermal conductivity of the first molding member (first molding member, element #13, can be silicone resin paragraph [0054], rows 5-8 and the second molding member can be an epoxy resin, paragraph [0067], rows 7-9. Note that Hatcher (US 2018/0044169 A1) teaches a second molding formed from epoxy resin with a thermal conductivity larger than 2W/m-K, paragraph [0061], rows 7-8 and 17-18, while Tangring (US 2022/0320403 A1) teaches a first molding formed of silicone resin with thermal conductivity less than 0.15W/m-K).
Regarding claim 11, Kuriki teaches a semiconductor package, comprising: a package substrate comprising (Fig.3B, element #10) a first mounting region (Fig.3B, first mounting region is the region of substrate #10 on which the leftmost element #32 is located); and a second mounting region adjacent to the first mounting region and spaced-apart from the first mounting region along a horizontal direction (Fig.3B, second mounting region is the region of substrate #10 on which the second leftmost element #32 is located); a first semiconductor chip mounted on the first mounting region, and a second semiconductor chip mounted on the second mounting region (Fig.3B, the leftmost two element #32); a plurality of bonding wires coupled to the first semiconductor chip (Fig.3B, the leftmost element #32 has two wires); a first molding member on the package substrate covering the first semiconductor chip and the second semiconductor chip (Fig.1A, element #42), wherein the first molding member comprises a first cover portion arranged above, along a vertical direction extending from the package substrate orthogonal to the horizontal direction, the plurality of bonding wires and covering the first semiconductor chip on the first mounting region and a second cover portion arranged above, along the vertical direction, the plurality of bonding wires and between the first and second mounting regions (Fig.1B, element #42 has a first molding portion above the wires of the first semiconductor chip, the leftmost element #32, and a second portion above the wires and between the first semiconductor chip and the second semiconductor chip, the second leftmost element #32), wherein the first cover portion and the second cover portion are arranged adjacent along the horizontal direction (the two portions can be chosen adjacent to one another).
Kuriki does not teach a ratio per unit volume of a filler material included in the first cover portion is greater than a ratio per unit volume of the filler material included in the second cover portion. Jiang teaches wherein first molding member (Fig.4J, element #120) covering the first semiconductor chip and the second semiconductor chip, wherein the first molding member comprises a first cover portion arranged above, along a vertical direction extending from the package substrate orthogonal to the horizontal direction, the plurality of bonding wires and covering the first semiconductor chip and a second cover portion arranged above, along the vertical direction, the plurality of bonding wires and between the first and second semiconductor chips (Fig.4L, element #120 has a first molding portion above the wires of the first semiconductor chip, element #142 third from the right, and a second portion between the first semiconductor chip and the second semiconductor chip, element #142 on the right side of region #104), wherein the first cover portion and the second cover portion are arranged adjacent along the horizontal direction (portions can be selected adjacent to one another) and a ratio per unit volume of a filler material included in the first cover portion is greater than a ratio per unit volume of the filler material included in the second cover portion (Fig.4J, molding material in region #102 has a first filler, which is not present in region #130 between the chips, paragraph [0169] and paragraph [0171], rows 1-5). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Jiang and disclose wherein first molding member covering the first semiconductor chip and the second semiconductor chip, wherein the first molding member comprises a first cover portion arranged above, along a vertical direction extending from the package substrate orthogonal to the horizontal direction, the plurality of bonding wires and covering the first semiconductor chip and a second cover portion arranged above, along the vertical direction, the plurality of bonding wires and between the first and second semiconductor chips, wherein the first cover portion and the second cover portion are arranged adjacent along the horizontal direction (portions can be selected adjacent to one another) and a ratio per unit volume of a filler material included in the first cover portion is greater than a ratio per unit volume of the filler material included in the second cover portion. As disclosed by Jiang, the two portions can have different functions and be optimized according to their function (paragraph [0169], rows 1-10).
The combination of Kuriki and Jiang does not disclose a second molding member on the first molding member. Waragaya teaches a second molding member on the first molding member (Fig.2b, element #14 can be made of resin, paragraph [0067], rows 6-8, and is on the first molding member, element #13). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Waragaya and disclose a second molding member on the first molding member. As disclosed by Waragaya, the top surface of the second molding can act as a light emitting surface, improving the light emitting efficiency of the package (paragraph [0061], rows 7-10).
Regarding claim 12, the combination of Kuriki, Jiang and Waragaya teaches the semiconductor package of claim 11 as set forth in the obviousness rejection. Jiang further teaches the semiconductor package of claim 11, wherein an average particle size of the filler material included in the first molding portion is greater than an average particle size of the filler material included in the second molding portion (since no filler is present in the second molding portion the limitation is satisfied).
Regarding claim 14, the combination of Kuriki, Jiang and Waragaya teaches the semiconductor package of claim 11 as set forth in the obviousness rejection. Waragaya further teaches the semiconductor package of claim 11, wherein the second molding member covers an entire upper surface of the first molding member (Fig.2b, element #14, covers the entire upper surface of a first molding member, element #13). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Waragaya and disclose wherein the second molding member covers an entire upper surface of the first molding member. As disclosed by Waragaya, the second molding can increase the light emission efficiency of the package (paragraph [0061], rows 7-10).
Regarding claim 16, the combination of Kuriki, Jiang and Waragaya teaches the semiconductor package of claim 11 as set forth in the obviousness rejection. Waragaya further teaches the semiconductor package of claim 11, wherein the second molding member comprises a same material as the first molding member (both can comprise silicone resin paragraph [0054], rows 5-8 and, paragraph [0067], rows 7-9). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Waragaya and disclose wherein the second molding member comprises a same material as the first molding member. Using same material simplifies the manufacturing process (same tools can be used).
Regarding claim 17, the combination of Kuriki, Jiang and Waragaya teaches the semiconductor package of claim 11 as set forth in the obviousness rejection. Waragaya further teaches the semiconductor package of claim 11, wherein the second molding member comprises a material different from a material of the first molding member (first molding member, element #13, can be silicone resin paragraph [0054], rows 5-8 and the second molding member can be an epoxy resin, paragraph [0067], rows 7-9). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Waragaya and disclose wherein the second molding member comprises a material different from a material of the first molding member. The two molding members may have different functions and each can be optimized separately for its specific purpose.
Regarding claim 18, the combination of Kuriki, Jiang and Waragaya teaches the semiconductor package of claim 11 as set forth in the obviousness rejection. Waragaya further teaches the semiconductor package of claim 11, wherein a thermal conductivity of the second molding member is greater than a thermal conductivity of the first molding member (first molding member, element #13, can be silicone resin paragraph [0054], rows 5-8, and the second molding member can be an epoxy resin, paragraph [0067], rows 7-9. Note that Hatcher (US 2018/0044169 A1) teaches molding formed from epoxy resin with a thermal conductivity larger than 2W/m-K, paragraph [0061], rows 7-8 and 17-18, while Tangring (US 2022/0320403 A1) teaches molding formed of silicone resin with thermal conductivity less than 0.15W/m-K).
Regarding claim 19, the combination of Kuriki, Jiang and Waragaya teaches the semiconductor package of claim 11 as set forth in the obviousness rejection. Kuriki further teaches the semiconductor package of claim 11, wherein the first molding member comprises an epoxy molding compound (paragraph [0049] of the translation document included with the office action).
Claims 1, 6, 7 , 11, 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Waragaya in view of Okui, (United States Patent Application Publication Number, US 2018/0012872 A1) hereinafter referenced as Okui and in view in of Jiang.
Regarding claim 1, Waragaya teaches a semiconductor package, comprising: a package substrate (Fig.2b, element #10); a first semiconductor chip and a second semiconductor chip on the package substrate in adjacent, spaced-apart relationship along a horizontal direction (Fig.2b, elements #11, labeled in Fig.2a).
Waragaya discloses the first semiconductor chip and a second semiconductor chip are connected to the substrate using solder bumps (Fig.2a, element #12). Waragaya does not disclose a plurality of bonding wires coupled to the first semiconductor chip. Okui teaches a plurality of bonding wires coupled to the first semiconductor chip that electrically connect the chip to a substrate (Fig.18A, wires #119 and #121, connect the chip, #105, to the substrate). Thus, both references Waragaya and Okui teach an electrical connection between the semiconductor chip and a substrate. A person skilled in the art, before the effective filing date of the claimed invention, would have recognized that the solder bumps disclosed by Waragaya could have been replaced for the wires disclosed by Okui, because both serve the same purpose of providing an electrical connection of the semiconductor chip to the substrate. Furthermore, a person skilled in the art would have been able to carry out the substitution. Finally, the substitution achieves the predictable result of providing an electrical connection between the semiconductor chip and the substrate. Wires provide a more flexible connection that can be reworked and replaced easily in case of damage.
Waragaya further teaches a first molding member on the package substrate and covering the first semiconductor chip and the second semiconductor chip (Fig.2b, element #13); and a second molding member on the first molding member (Fig.2b, element #14), wherein the first molding member comprises a first molding portion arranged along a vertical direction extending from the package substrate orthogonal to the horizontal direction, on the first semiconductor chip and a second molding portion arranged, along the vertical direction, and between the first and second semiconductor chips, and wherein the first molding portion and the second molding portion are arranged at a same height above the package substrate (Fig.2b, element #13).
Okui teaches herein the first molding member comprises a first molding portion arranged above, along a vertical direction extending from the package substrate orthogonal to the horizontal direction, the plurality of bonding wires and on the first semiconductor chip and a second molding portion arranged above, along the vertical direction, the plurality of bonding wires and between the first and second semiconductor chips, and wherein the first molding portion and the second molding portion are arranged at a same height above the package substrate (Fig.18A, the first molding member, element #191, has portions that satisfy the limitations. The combination of Waragaya and Okui does not teach a ratio per unit volume of a filler material included in the first molding portion is greater than a ratio per unit volume of the filler material included in the second molding portion. Jiang teaches wherein the first molding member (Fig.4J, element #120) comprises a first molding portion arranged above, along a vertical direction extending orthogonal to the horizontal direction, the plurality of bonding wires and on the first semiconductor chip and a second molding portion arranged above, along the vertical direction, the plurality of bonding wires and between the first and second semiconductor chips (Fig.4L, element #120 has a first molding portion above the wires of the first semiconductor chip, element #142 third from the right, and a second portion between the first semiconductor chip and the second semiconductor chip, element #142 on the right side of region #104) and wherein the first molding portion and the second molding portion are arranged at a same height above the package substrate (portions above the wires can be selected to be at the same height) and a ratio per unit volume of a filler material included in the first molding portion is greater than a ratio per unit volume of the filler material included in the second molding portion (Fig.4J, molding material in region #102 has a first filler, which is not present in region #130 between the chips, paragraph [0169] and paragraph [0171], rows 1-5). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Jiang and disclose wherein the first molding member comprises a first molding portion arranged above, along a vertical direction extending from the package substrate orthogonal to the horizontal direction, the plurality of bonding wires and on the first semiconductor chip and a second molding portion arranged above, along the vertical direction, the plurality of bonding wires and between the first and second semiconductor chips, and wherein the first molding portion and the second molding portion are arranged at a same height above the package substrate and a ratio per unit volume of a filler material included in the first molding portion is greater than a ratio per unit volume of the filler material included in the second molding portion. As disclosed by Jiang, the two portions can have different functions and be optimized according to their function (paragraph [0169], rows 1-10).
Regarding claim 6, the combination of Waragaya, Okui and Jiang teaches the semiconductor package the semiconductor package of claim 1 as set forth in the obviousness rejection. Waragaya further teaches the semiconductor package of claim 1, wherein the second molding member covers an entire upper surface of the first molding member (Fig.2B, element #14 covers the entire top surface of element #13).
Regarding claim 7, the combination of Waragaya, Okui and Jiang teaches the semiconductor package the semiconductor package of claims 1 and 6 as set forth in the obviousness rejection. Waragaya further teaches the semiconductor package of claim 6, wherein a side surface of the first molding member is exposed from the semiconductor package (Fig.2b, the side surface of element #13 are exposed).
Regarding claim 11, Waragaya teaches a semiconductor package, comprising: a package substrate (Fig.2b, element #10) comprising a first mounting region (Fig.2b, region of element #10 where the left side semiconductor chip #11 is mounted) and a second mounting region adjacent to the first mounting region and spaced-apart from the first mounting region along a horizontal direction (Fig.2b, region of element #10 where the right side semiconductor chip #11 is mounted); a first semiconductor chip mounted on the first mounting region (Fig.2b, semiconductor chip #11 located on the left side of the figure), and a second semiconductor chip mounted on the second mounting region (Fig.2b, semiconductor chip #11 located on the right side of the figure).
Waragaya discloses the first semiconductor chip and a second semiconductor chip are connected to the substrate using solder bumps (Fig.2a, element #12). Waragaya does not disclose a plurality of bonding wires coupled to the first semiconductor chip. Okui teaches a plurality of bonding wires coupled to the first semiconductor chip that connect the chip with a substrate (Fig.18A, wires #119 and #121, connect the chip, #105, to the substrate). Thus, both references Waragaya and Okui teach an electrical connection between the semiconductor chip and a substrate. A person skilled in the art, before the effective filing date of the claimed invention, would have recognized that the solder bumps disclosed by Waragaya could have been replaced for the wires disclosed by Okui, because both serve the same purpose of providing an electrical connection of the semiconductor chip to the substrate. Furthermore, a person skilled in the art would have been able to carry out the substitution. Finally, the substitution achieves the predictable result of providing an electrical connection between the semiconductor chip and the substrate. Wires provide a more flexible connection that can be reworked and replaced easily in case of damage.
Waragaya further teaches a first molding member on the package substrate and covering the first semiconductor chip and the second semiconductor chip (Fig.2b, element #13), wherein the first molding member comprises a first molding portion arranged along a vertical direction extending from the package substrate orthogonal to the horizontal direction, on the first semiconductor chip on the first mounting region and a second cover portion arranged along the vertical direction, and between the first and second mounting regions, wherein the first cover portion and the second cover portion are arranged adjacent along the horizontal direction (Fig.2b, element #13 has portions that satisfy the above limitations), and a second molding member on the first molding member (Fig.2b, element #14).
Okui teaches a first molding member on the package substrate covering the first semiconductor chip and the second semiconductor chip, wherein the first molding member comprises a first cover portion arranged above, along a vertical direction extending from the package substrate orthogonal to the horizontal direction, the plurality of bonding wires and covering the first semiconductor chip on the first mounting region and a second cover portion arranged above, along the vertical direction, the plurality of bonding wires and between the first and second mounting regions ,wherein the first cover portion and the second cover portion are arranged adjacent along the horizontal direction (Fig.18A, the first molding member, element #191, has portions that satisfy the limitations). The combination of Waragaya and Okui does not teach a ratio per unit volume of a filler material included in the first molding portion is greater than a ratio per unit volume of the filler material included in the second molding portion. Jiang teaches a first molding member (Fig.4J, element #120) covering the first semiconductor chip and the second semiconductor chip, wherein the first molding member comprises a first cover portion arranged above, along a vertical direction extending from the package substrate orthogonal to the horizontal direction, the plurality of bonding wires and covering the first semiconductor chip and a second cover portion arranged above, along the vertical direction, the plurality of bonding wires and between the first and second semiconductor chips, wherein the first cover portion and the second cover portion are arranged adjacent along the horizontal direction (Fig.4L, element #120 has a first molding portion above the wires of the first semiconductor chip, element #142 third from the right, and a second portion between the first semiconductor chip and the second semiconductor chip, element #142 on the right side of region #104) and a ratio per unit volume of a filler material included in the first cover portion is greater than a ratio per unit volume of the filler material included in the second cover portion (Fig.4J, molding material in region #102 has a first filler, which is not present in region #130 between the chips, paragraph [0169] and paragraph [0171], rows 1-5). ). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Jiang and disclose a first molding member on the package substrate covering the first semiconductor chip and the second semiconductor chip, wherein the first molding member comprises a first cover portion arranged above, along a vertical direction extending from the package substrate orthogonal to the horizontal direction, the plurality of bonding wires and covering the first semiconductor chip and a second cover portion arranged above, along the vertical direction, the plurality of bonding wires and between the first and second semiconductor regions, wherein the first cover portion and the second cover portion are arranged adjacent along the horizontal direction and a ratio per unit volume of a filler material included in the first cover portion is greater than a ratio per unit volume of the filler material included in the second cover portion. As disclosed by Jiang, the two cover portions can have different functions and be optimized according to their function (paragraph [0169], rows 1-10).
Regarding claim 14, the combination of Waragaya, Okui and Jiang teaches the semiconductor package the semiconductor package of claim 11 as set forth in the obviousness rejection. Waragaya further teaches the semiconductor package of claim 11, wherein the second molding member covers an entire upper surface of the first molding member (Fig.2B, element #14 covers the entire top surface of element #13).
Regarding claim 15, the combination of Waragaya, Okui and Jiang teaches the semiconductor package the semiconductor package of claims 11 and 14 as set forth in the obviousness rejection. Waragaya further teaches the semiconductor package of claim 14, wherein a side surface of the first molding member is exposed from the semiconductor package (Fig.2b, the side surface of element #13 are exposed).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Waragaya in view of Okui Jiang and in view of Iida et al., (United States Patent Number, US 7,893,525 B2) hereinafter referenced as Iida.
Regarding claim 20, Waragaya teaches a semiconductor package, comprising: a package substrate (Fig.2b, element #10) comprising a first mounting region (Fig.2b, region of element #10 where the left side semiconductor chip #11 is mounted) and a second mounting region in adjacent, spaced-apart relationship along a horizontal direction (Fig.2b, region of element #10 where the right side semiconductor chip #11 is mounted); a first semiconductor chip mounted on the first mounting region (Fig.2b, semiconductor chip #11 located on the left side of the figure), and a second semiconductor chip mounted on the second mounting region (Fig.2b, semiconductor chip #11 located on the right side of the figure).
Waragaya discloses the first semiconductor chip and a second semiconductor chip are connected to the substrate using solder bumps (Fig.2a, element #12). Waragaya does not disclose a plurality of bonding wires coupled to the first semiconductor chip. Okui teaches a plurality of bonding wires coupled to the first semiconductor chip that connect the chip with a substrate (Fig.18A, wires #119 and #121, connect the chip, #105, to the substrate). Thus, both references Waragaya and Okui teach an electrical connection between the semiconductor chip and a substrate. A person skilled in the art, before the effective filing date of the claimed invention, would have recognized that the solder bumps disclosed by Waragaya could have been replaced for the wires disclosed by Okui, because both serve the same purpose of providing an electrical connection between the semiconductor chip and the substrate. Furthermore, a person skilled in the art would have been able to carry out the substitution. Finally, the substitution achieves the predictable result of providing an electrical connection between the semiconductor chip and the substrate. Wires provide a more flexible connection that can be reworked and replaced easily in case of damage.
Waragaya further teaches a first molding member on the package substrate covering the first semiconductor chip and the second semiconductor chip (Fig.2b, element #13), wherein the first molding member comprises a first cover portion arranged, along a vertical direction extending from the package substrate orthogonal to the horizontal direction, and covering the first semiconductor chip on the first mounting region and a second cover portion arranged, along the vertical direction, and between the first and second mounting regions; wherein the first cover portion and the second cover portion are arranged at a same height above the package substrate (Fig.2b, element #13 has portions that satisfy the above limitations), and a second molding member on the first molding member (Fig.2b, element #14).
Okui teaches a first molding member on the package substrate covering the first semiconductor chip and the second semiconductor chip, wherein the first molding member comprises a first cover portion arranged above, along a vertical direction extending from the package substrate orthogonal to the horizontal direction, the plurality of bonding wires and covering the first semiconductor chip on the first mounting region and a second cover portion arranged above, along the vertical direction, the plurality of bonding wires and between the first and second mounting regions, wherein the first cover portion and the second cover portion are arranged at a same height above the package substrate (Fig.18A, the first molding member, element #191, has portions that satisfy the limitations). The combination of Waragaya and Okui does not teach a ratio per unit volume of a filler material included in the first molding portion is greater than a ratio per unit volume of the filler material included in the second molding portion. Jiang teaches a first molding member (Fig.4J, element #120) covering the first semiconductor chip and the second semiconductor chip, wherein the first molding member comprises a first cover portion arranged above, along a vertical direction extending from the package substrate orthogonal to the horizontal direction, the plurality of bonding wires and covering the first semiconductor chip and a second cover portion arranged above, along the vertical direction, the plurality of bonding wires and between the first and second semiconductor chips, wherein the first cover portion and the second cover portion are arranged at a same height above the package substrate (Fig.4L, element #120 has a first molding portion above the wires of the first semiconductor chip, element #142 third from the right, and a second portion between the first semiconductor chip and the second semiconductor chip, element #142 on the right side of region #104) and a ratio per unit volume of a filler material included in the first cover portion is greater than a ratio per unit volume of the filler material included in the second cover portion (Fig.4J, molding material in region #102 has a first filler, which is not present in region #130 between the chips, paragraph [0169] and paragraph [0171], rows 1-5). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Jiang and disclose teaches a first molding member covering the first semiconductor chip and the second semiconductor chip, wherein the first molding member comprises a first cover portion arranged above, along a vertical direction extending from the package substrate orthogonal to the horizontal direction, the plurality of bonding wires and covering the first semiconductor chip and a second cover portion arranged above, along the vertical direction, the plurality of bonding wires and between the first and second semiconductor chips, wherein the first cover portion and the second cover portion are arranged at a same height above the package substrate and a ratio per unit volume of a filler material included in the first cover portion is greater than a ratio per unit volume of the filler material included in the second cover portion. As disclosed by Jiang, the two cover portions can have different functions and be optimized according to their function (paragraph [0169], rows 1-10).
The combination of Waragaya, Okui and Jiang does not teach wherein a spacing distance between the first and second semiconductor chips is within a range of 0.3 mm to 0.5 mm. Iida teaches a spacing distance between the first and second semiconductor chips is 1 mm (column 14, rows 19-21). Iida also teaches that the stress on the semiconductor chips, for a given molding material and filler concentration, is a function of the distance between the chips, where distances between 0.1 mm and 3 mm were considered (Fig.9 and Fig.29). Iida does not teach wherein a spacing distance between the first and second semiconductor chips is within a range of 0.3 mm to 0.5mm. It would have been obvious to one ordinary skilled in the art, before the effective filling date of the claimed invention, to optimize the spacing distance between the two semiconductor chips through routine experimentation (MPEP 2144.05). The spacing distance between the two chips is a result effective variable because it is important to optimize its value based on the molding material used and the size of the semiconductor chips, to assure the stress on the semiconductor chips is minimized.
Allowable Subject Matter
Claims 3, 4, and 13 are allowed if written in independent form.
The following is a statement of reasons for the indication of allowable subject matter.
Regarding claims 3 and 13 the cited prior art does not teach or fairly suggests, along with other claimed features: “wherein the ratio per unit volume of the filler material included in the first molding portion is within a range of 50% to 70%, and the ratio per unit volume of the filler material included in the second molding portion is 30% to 55%.” Jiang teaches no filler material included in the second molding portion, while the other references do not teach different ration per unit volume of the filler materials.
Regarding claim 4, the cited prior art does not teach or fairly suggests, along with other
claimed features: “wherein the filler material included in the first molding member is within a range of 60wt% to 95wt% of a total weight of the first molding member”. Jiang teaches molding portions with no filler, with no information about the volume of these regions, therefore the content of the filler material cannot be established.
Response to Arguments
Applicant’s arguments filed on 04/28/2026 have been fully considered but they
are not persuasive. Applicant’s arguments with respect to claims 1, 11 and 20 have been considered but are moot because the new ground of rejection does not rely on any reference as applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/CRISTIAN A TIVARUS/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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