DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on 12/23/2025 has been entered. Claims 1-20 remain pending in the application. Applicant’s amendments have overcome each and every 112(b) rejections previously set forth in the Non-Final Office Action mailed on 09/24/2025.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-7, 9, 11, 14, 15, 17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kazama (United States Patent Number, US 7,015,593 B2) hereinafter referenced as Kazama, in view of Jang et al., (United States Patent Application Publication Number, US 2021/0020505 A1) hereinafter referenced as Jang and in view of Hess et al., (United States Patent Number, US 8,318,549 B2) hereinafter referenced as Hess.
Regarding claim 1, Kazama teaches a semiconductor package, comprising: a package substrate (Fig.3C, element #1X); a first semiconductor chip and a second semiconductor chip on the package substrate in adjacent, spaced-apart relationship (Fig.3C, the two chips, elements #3); a first molding member on the package substrate and covering the first semiconductor chip and the second semiconductor chip (Fig.3C, element #5).
Kazama does not teach a second molding member on the first molding member. Jang teaches a second molding member on the first molding member (Fig.2, second molding, element #104, paragraph [0052], rows 1-3 is on the first molding, element #103, paragraph [0050], row 1). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Jang and disclose a second molding member on the first molding member. As disclosed by Jang, the second molding member prevents the inclination of conductive posts that might be embedded in the first molding member (paragraph [0053], rows 9-14).
Kazama further teaches wherein the first molding member comprises a first molding portion on the first semiconductor chip (Fig.3C, portion of molding above the top surface of the first chip, which is the left side chip, element #3) and a second molding portion between the first and second semiconductor chips (Fig.3C, portion of molding between the two chips, elements #3 and at the same height above the substrate as the first portion), and wherein the first molding portion and the second molding portion are arranged at a same height above the package substrate (condition is satisfied by the above choice of the two portions).
The combination of Kazama and Jang does not teach a ratio per unit volume of a filler material included in the first molding portion is greater than a ratio per unit volume of the filler material included in the second molding portion. Hess teaches wherein the first molding member (Fig.2 shows the molding member with the filler material particles), element comprises a first molding portion on the first semiconductor chip (Fig.2, portion of molding above elements #24 and #26 and between wires #46 and #44, corresponding to molding region #62) and a second molding portion between the first and second semiconductor chips (Fig.2 portion of molding located to the right side of elements #26, below the wire #46, corresponding to molding region #50, and at the same height above the substrate as the first portion, this would correspond to a region between the first and second semiconductor chips of Kazama), and wherein the first molding portion and the second molding portion are arranged at a same height above the package substrate (condition is satisfied by the above choice of the two portions), and a ratio per unit volume of a filler material included in the first molding portion is greater than a ratio per unit volume of the filler material included in the second molding portion (Fig.2, first portion corresponds to region #62, which is a medium filler region and second portion corresponds to region #50, which is a low filler region, column 3, rows 30-31). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Hess and disclose a ratio per unit volume of a filler material included in the first molding portion is greater than a ratio per unit volume of the filler material included in the second molding portion. As disclosed by Hess, this is the result of the screening of the filler material by the wires (column 3, rows 22-27).
Regarding claim 4, the combination of Kazama, Jang and Hess teaches the semiconductor package of claim 1 as set forth in the obviousness rejection. Kazama does not each the semiconductor package of claim 1, wherein the filler material included in the first molding member is within a range of 60wt% to 95wt% of a total weight of the first molding member. Jang teaches wherein the filler material included in the first molding member is within a range of 30wt% to 90wt% of a total weight of the first molding member (paragraph [0050], rows 1-4). The claimed range, of 60wt% to 95wt%, overlaps the range disclosed by Jang and therefore a prima facie case of obviousness exists (MPEP 2144.05).
Regarding claim 5, the combination of Kazama, Jang and Hess teaches the semiconductor package of claim 1 as set forth in the obviousness rejection. The combination of Kazama and Jang does not each the semiconductor package of claim 1, wherein the first molding member further comprises a third molding portion on the second semiconductor chip and wherein a ratio per unit volume of the filler material included in the third molding portion is greater than the ratio per unit volume of the filler material included in the second molding portion. Hess teaches wherein the first molding member further comprises a third molding portion on the second semiconductor chip (Fig.2, portion of molding region #56, between element #20 and #24 would exists for both first and second semiconductor chips of Kazama), and wherein a ratio per unit volume of the filler material included in the third molding portion is greater than the ratio per unit volume of the filler material included in the second molding portion (third molding portion corresponds to region #56, which is a high filler region and second molding portion corresponds to region #50, which is a low filler region, column 3, rows 30-31). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Hess and disclose wherein the first molding member further comprises a third molding portion on the second semiconductor chip and wherein a ratio per unit volume of the filler material included in the third molding portion is greater than the ratio per unit volume of the filler material included in the second molding portion. As disclosed by Hess, this is the result of the screening of the filler material by the wires (column 3, rows 22-27).
Regarding claim 6, the combination of Kazama, Jang and Hess teaches the semiconductor package of claim 1 as set forth in the obviousness rejection. Kazama does not teach the semiconductor package of claim 1, wherein the second molding member covers an entire upper surface of the first molding member. Jang teaches wherein the second molding member covers an entire upper surface of the first molding member (Fig.2, element #104 covers the entire top surface of element #103). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Jang and disclose wherein the second molding member covers an entire upper surface of the first molding member. As disclosed by Jang, this provides the package with a flat top surface onto which redistribution layers and/or other semiconductor dies can be easily attached.
Regarding claim 7, the combination of Kazama, Jang and Hess teaches the semiconductor package of claims 1 and 6 as set forth in the obviousness rejection. Kazama further teaches the semiconductor package of claim 6, wherein a side surface of the first molding member is exposed from the semiconductor package (Fig.3C, left side of the first molding member is exposed from the package).
Regarding claim 9, the combination of Kazama, Jang and Hess teaches the semiconductor package of claim 1 as set forth in the obviousness rejection. Kazama does not teach the semiconductor package of claim 1, wherein the second molding member comprises a material different from a material of the first molding member. Jang teaches the semiconductor package of claim 1, wherein the second molding member comprises a material different from a material of the first molding member (first molding member, element #103 may include an epoxy molding compound, paragraph [0049], rows 1-4, and the second molding member, element #104, may include polyimide, paragraph [0052], rows 2-3). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Jang and disclose wherein the second molding member comprises a material different from a material of the first molding member. Using different materials for the first and second molding members allows for the optimization of the thermal conductivities of the two molding members, which can help improve heat dissipation away from the package.
Regarding claim 11, Kazama teaches a semiconductor package, comprising: a package substrate (Fig.3C, element #1X) comprising a first mounting region (Fig.3C, region where the left side element #3 is mounted) and a second mounting region adjacent to the first mounting region and spaced-apart from the first mounting region along a horizontal direction (Fig.3C, region where the right side element #3 is mounted); a first semiconductor chip mounted on the first mounting region (Fig.3C, element #3 located on the left side of the figure), and a second semiconductor chip mounted on the second mounting region (Fig.3C, element #3 located on the right side of the figure); a first molding member on the package substrate covering the first semiconductor chip and the second semiconductor chip (Fig.3C, element #5), wherein the first molding member comprises a first cover portion covering the first semiconductor chip on the first mounting region (Fig.3C portion of molding above the top surface of the first chip, which is the left side chip, element #3) and a second cover portion between the first and second mounting regions (Fig.3C portion of molding between the two chips, elements #3 and at the same height above the substrate as the first portion).
Kazama does not teach a second molding member on the first molding member. Jang teaches a second molding member on the first molding member (Fig.2, second molding, element #104, paragraph [0052], rows 1-3 is on the first molding, element #103, paragraph [0050], row 1). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Jang and disclose a second molding member on the first molding member. As disclosed by Jang, the second molding member prevents the inclination of conductive posts that might be embedded in the first molding member (paragraph [0053], rows 9-14).
Kazama further teaches wherein the first cover portion and the second cover portion are arranged adjacent along the horizontal direction (condition is satisfied by the above choice of the two portions).
The combination of Kazama and Jang does not teach a ratio per unit volume of a filler material included in the first cover portion is greater than a ratio per unit volume of the filler material included in the second cover portion. Hess teaches wherein the first molding member (Fig.2 shows the molding member with the filler material particles), element comprises a first cover portion covering the first semiconductor chip on the first mounting region (Fig.2, portion of molding above elements #24 and #26 and between wires #46 and #44, corresponding to molding region #62) and a second cover portion between the first and second mounting regions (Fig.2 portion of molding located to the right side of elements #26, below the wire #46, corresponding to molding region #50, and at the same height above the substrate and adjacent to the first portion; this would correspond to a region between the first and second mounting regions of Kazama), and wherein the first molding portion and the second molding portion are arranged adjacent along the horizontal direction (condition is satisfied by the above choice of the two portions), and a ratio per unit volume of a filler material included in the first cover portion is greater than a ratio per unit volume of the filler material included in the second cover portion (Fig.2, first portion corresponds to region #62, which is a medium filler region and second portion corresponds to region #50, which is a low filler region, column 3, rows 30-31). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Hess and disclose a ratio per unit volume of a filler material included in the first cover portion is greater than a ratio per unit volume of the filler material included in the second cover portion. As disclosed by Hess, this is the result of the screening of the filler material by the wires (column 3, rows 22-27).
Regarding claim 14, the combination of Kazama, Jang and Hess teaches the semiconductor package of claim 11 as set forth in the obviousness rejection. Kazama does not teach the semiconductor package of claim 11, wherein the second molding member covers an entire upper surface of the first molding member. Jang teaches wherein the second molding member covers an entire upper surface of the first molding member (Fig.2, element #104 covers the entire top surface of element #103). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Jang and disclose wherein the second molding member covers an entire upper surface of the first molding member. As disclosed by Jang, this provides the package with a flat top surface onto which redistribution layers and/or other semiconductor dies can be easily attached.
Regarding claim 15, the combination of Kazama, Jang and Hess teaches the semiconductor package of claims 11 and 14 as set forth in the obviousness rejection. Kazama further teaches the semiconductor package of claim 14, wherein a side surface of the first molding member is exposed from the semiconductor package (Fig.3C, left side of the first molding member is exposed from the package).
Regarding claim 17, the combination of Kazama, Jang and Hess teaches the semiconductor package of claim 11 as set forth in the obviousness rejection. Kazama does not teach the semiconductor package of claim 11, wherein the second molding member comprises a material different from a material of the first molding member. Jang teaches the semiconductor package of claim 11, wherein the second molding member comprises a material different from a material of the first molding member (first molding member, element #103 may include an epoxy molding compound, paragraph [0049], rows 1-4, and the second molding member, element #104, may include polyimide, paragraph [0052], rows 2-3). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Jang and disclose wherein the second molding member comprises a material different from a material of the first molding member. Using different materials for the first and second molding members allows for the optimization of the thermal conductivities of the two molding members, which can help improve heat dissipation away from the package.
Regarding claim 19, the combination of Kazama, Jang and Hess teaches the semiconductor package of claim 11 as set forth in the obviousness rejection. Kazama further teaches the semiconductor package of claim 11, wherein the first molding member comprises a resin (column 1, row 42). Kazama does not teach wherein the first molding member comprises an epoxy molding compound. Jang teaches wherein the first molding member comprises an epoxy molding compound (paragraph [0049], rows 1-4). Thus, both references Kazama and Jang teach a molding member used seal the semiconductor chips. A person skilled in the art, before the effective filing date of the claimed invention, would have recognized that the resin disclosed by Kazama could have been replaced for the epoxy molding compound disclosed by Jang, because both serve the same purpose of providing a molding member that seals the semiconductor chips. Furthermore, a person skilled in the art would have been able to carry out the substitution. Finally, the substitution achieves the predictable result of providing a molding member that seals the semiconductor chips.
Claims 8, 10, 16 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Kazama in view of Jang, Hess and in view of Hatcher et al., (United States Patent Application Publication Number, US 2018/0044169 A1) hereinafter referenced as Hatcher.
Regarding claim 8, the combination of Kazama, Jang and Hess teaches the semiconductor package of claim 1 as set forth in the obviousness rejection. The combination of Kazama, Jang and Hess does not teach the semiconductor the semiconductor package of claim 1, wherein the second molding member comprises a same material as the first molding member. Hatcher teaches wherein a second molding member comprises a same material as a first molding member (Fig.1, second molding member, element #22 comprises a same material as the first molding member, element #20, paragraph [0061], rows 9-10). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Hatcher and disclose wherein the second molding member comprises a same material as the first molding member. Having the molding members comprise of the same material allows the use of the same processing tools and deposition recipes, which can reduce manufacturing costs.
Regarding claim 10, the combination of Kazama, Jang and Hess teaches the semiconductor package of claim 1 as set forth in the obviousness rejection. The combination of Kazama, Jang and Hess does not teach the semiconductor package of claim 1, wherein a thermal conductivity of the second molding member is greater than a thermal conductivity of the first molding member. Hatcher teaches wherein a thermal conductivity of the second molding member is greater than a thermal conductivity of the first molding member (second molding member, element #22 has a greater thermal conductivity as compared to the first molding member, element #20, paragraph [0061], rows 16-19). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Hatcher and disclose wherein a thermal conductivity of the second molding member is greater than a thermal conductivity of the first molding member. The second molding having greater thermal conductivity than the first molding, can help dissipate heat away from the package.
Regarding claim 16, the combination of Kazama, Jang and Hess teaches the semiconductor package of claim 11 as set forth in the obviousness rejection. The combination of Kazama, Jang and Hess does not teach the semiconductor the semiconductor package of claim 11, wherein the second molding member comprises a same material as the first molding member. Hatcher teaches wherein a second molding member comprises a same material as a first molding member (Fig.1, second molding member, element #22 comprises a same material as the first molding member, element #20, paragraph [0061], rows 9-10). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Hatcher and disclose wherein the second molding member comprises a same material as the first molding member. Having the molding members comprise of the same material allows the use of the same processing tools and deposition recipes, which can reduce manufacturing costs.
Regarding claim 18, the combination of Kazama, Jang and Hess teaches the semiconductor package of claim 11 as set forth in the obviousness rejection. The combination of Kazama, Jang and Hess does not teach the semiconductor package of claim 11, wherein a thermal conductivity of the second molding member is greater than a thermal conductivity of the first molding member. Hatcher teaches wherein a thermal conductivity of the second molding member is greater than a thermal conductivity of the first molding member (second molding member, element #22 has a greater thermal conductivity as compared to the first molding member, element #20, paragraph [0061], rows 16-19). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Hatcher and disclose wherein a thermal conductivity of the second molding member is greater than a thermal conductivity of the first molding member. The second molding having greater thermal conductivity than the first molding, can help dissipate heat away from the package.
Claims 3, 13 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kazama in view of Jang, Hess and in view of Iida et al., (United States Patent Number, US 7,893,525 B2) hereinafter referenced as Iida.
Regarding claim 3, the combination of Kazama, Jang and Hess teaches the semiconductor package of claim 1 as set forth in the obviousness rejection. The combination of Kazama, Jang and Hess does not teach the semiconductor package of claim 1, wherein the ratio per unit volume of the filler material included in the first molding portion is within a range of 50% to 70%, and the ratio per unit volume of the filler material included in the second molding portion is 30% to 55%. Iida teaches wherein the ratio per unit volume of the filler material included in the first molding portion (Fig.23B, portion on top of element #10 delimited by the vertical planes coplanar with the left and right side of element #10, and corresponding to top layer #32d) is within a range of 50% to 70% (ratio per unit volume is 67%, column 17, rows 56-57). The claimed range overlaps with the range disclosed by Iida and therefore a prima facie case of obviousness exists (MPEP 2144.05).
The combination of Kazama, Jang and Hess and Iida does not teach the ratio per unit volume of the filler material included in the second molding portion is 30% to 55%. However, Hess teaches the concentration of the filler material in the second portion is less than the concentration of the filler material in the first portion due to wire screening (column 3, rows 22-27). So, if one would inject a molding compound with the filler ratio per unit volume within the range of 50% to 70% (or as disclosed by Iida, a ratio per unit volume is 67%, column 17, rows 56-57), the ratio per unit volume of the filler material in the regions screened by the wires, would be less than 67%, which includes the claimed range of 30% to 55%. Furthermore, a person skilled in the art would recognize that different chips have different densities and distribution of wires and the ratio per unit volume of the filler material in the regions screened by the wires depends on the density and distribution of wires. Therefore, it would have been obvious to someone or ordinary skilled in the art, before the effective filling date of the claimed invention to claim a filler ratio per unit volume, in the second portion, in the range of 30% to 55%. The ratio per unit volume of the filler concentration in the second region is a result of process of molding flow in the regions of the package screened by the wires and a function of the density and distribution of the wires.
Regarding claim 13, the combination of Kazama, Jang and Hess teaches the semiconductor package of claim 11 as set forth in the obviousness rejection. The combination of Kazama, Jang and Hess does not teach the semiconductor package of claim 11, wherein the ratio per unit volume of the filler material included in the first molding portion is within a range of 50% to 70%, and the ratio per unit volume of the filler material included in the second molding portion is 30% to 55%. Iida teaches wherein the ratio per unit volume of the filler material included in the first molding portion (Fig.23B, portion on top of element #10 delimited by the vertical planes coplanar with the left and right side of element #10, and corresponding to top layer #32d) is within a range of 50% to 70% (ratio per unit volume is 67%, column 17, rows 56-57). The claimed range overlaps with the range disclosed by Iida and therefore a prima facie case of obviousness exists (MPEP 2144.05).
The combination of Kazama, Jang and Hess and Iida does not teach the ratio per unit volume of the filler material included in the second molding portion is 30% to 55%. However, Hess teaches the concentration of the filler material in the second portion is less than the concentration of the filler material in the first portion due to wire screening (column 3, rows 22-27). So, if one would inject a molding compound with the filler ratio per unit volume within the range of 50% to 70% (or as disclosed by Iida, a ratio per unit volume is 67%, column 17, rows 56-57), the ratio per unit volume of the filler material in the regions screened by the wires, would be less than 67%, which includes the claimed range of 30% to 55%. Furthermore, a person skilled in the art would recognize that different chips have different densities and distribution of wires and the ratio per unit volume of the filler material in the regions screened by the wires depends on the density and distribution of wires. Therefore, it would have been obvious to someone or ordinary skilled in the art, before the effective filling date of the claimed invention, to claim a filler ratio per unit volume, in the second portion, in the range of 30% to 55%. The ratio per unit volume of the filler concentration in the second region is a result of process of molding flow in the regions of the package screened by the wires and a function of the density and distribution of the wires.
Regarding claim 20, Kazama teaches a semiconductor package, comprising: a package substrate (Fig.3C, element #1X) comprising a first mounting region (Fig.3C, region where the left side element #3 is mounted) and a second mounting region in adjacent, spaced-apart relationship (Fig.3C, region where the right side element #3 is mounted); a first semiconductor chip mounted on the first mounting region (Fig.3C, element #3 located on the left side of the figure), and a second semiconductor chip mounted on the second mounting region (Fig.3C, element #3 located on the right side of the figure); a first molding member on the package substrate covering the first semiconductor chip and the second semiconductor chip (Fig.3C, element #5), wherein the first molding member comprises a first cover portion covering the first semiconductor chip on the first mounting region (Fig.3C, portion of molding above the top surface of the first chip, which is the left side chip, element #3) and a second cover portion between the first and second mounting regions(Fig.3C, portion of molding between the two chips, elements #3 and at the same height above the substrate as the first portion).
Kazama does not teach a second molding member on the first molding member. Jang teaches a second molding member on the first molding member (Fig.2, second molding, element #104, paragraph [0052], rows 1-3 is on the first molding, element #103, paragraph [0050], row 1). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Jang and disclose a second molding member on the first molding member. As disclosed by Jang, the second molding member prevents the inclination of conductive posts that might be embedded in the first molding member (paragraph [0053], rows 9-14).
Kazama further teaches wherein the first cover portion and the second cover portion are arranged at a same height above the package substrate (condition is satisfied by the above choice of the two portions).
The combination of Kazama and Jang does not teach a ratio per unit volume of a filler material included in the first cover portion is greater than a ratio per unit volume of the filler material included in the second cover portion. Hess teaches wherein the first molding member (Fig.2 shows the molding member with the filler material particles), comprises a first cover portion covering the first semiconductor chip on the first mounting region (Fig.2, portion of molding above elements #24 and #26 and between wires #46 and #44, corresponding to molding region #62) and a second cover portion between the first and second mounting regions (Fig.2 portion of molding located to the right side of elements #26, below the wire #46, corresponding to molding region #50, and at the same height above the substrate as the first portion; this would correspond to a region between the first and second mounting regions of Kazama), and wherein the first molding portion and the second molding portion are arranged adjacent along the horizontal direction (condition is satisfied by the above choice of the two portions), and a ratio per unit volume of a filler material included in the first cover portion is greater than a ratio per unit volume of the filler material included in the second cover portion (Fig.2, first portion corresponds to region #62, which is a medium filler region and second portion corresponds to region #50, which is a low filler region, column 3, rows 30-31). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Hess and disclose a ratio per unit volume of a filler material included in the first cover portion is greater than a ratio per unit volume of the filler material included in the second cover portion. As disclosed by Hess, this is the result of the screening of the filler material by the wires (column 3, rows 22-27).
The combination of Kazama, Jang and Hess does not teach wherein a spacing distance between the first and second semiconductor chips is within a range of 0.3 mm to 0.5 mm. Iida teaches a spacing distance between the first and second semiconductor chips is 1mm (column 14, rows 19-21). Iida also teaches that the stress on the semiconductor chips, for a given molding material and filler concentration, is a function of the distance between the chips, where distances between 0.1mm and 3mm were considered (Fig.9 and Fig.29). Iida does not teach wherein a spacing distance between the first and second semiconductor chips is within a range of 0.3 mm to 0.5mm. It would have been obvious to one ordinary skilled in the art, before the effective filling date of the claimed invention, to optimize the spacing distance between the two semiconductor chips through routine experimentation (MPEP 2144.05). The spacing distance between the two chips is a result effective variable because it is important to optimize its value based on the molding material used and the size of the semiconductor chips, to assure the stress on the semiconductor chips is minimized.
Claims 1, 2, 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Sakano et al., (United States Patent Application Publication Number, US 2003/0080341 A1) hereinafter referenced as Sakano, in view of Waragaya et al., (United States Patent Application Publication Number, US 2012/0236582 A1) hereinafter referenced as Waragaya.
Regarding claim 1, Sakano teaches a semiconductor package, comprising: a package substrate (Fig.5; element #2) a first semiconductor chip and a second semiconductor chip on the package substrate in adjacent, spaced-apart relationship (Fig.5, the leftmost two elements #5); a first molding member on the package substrate and covering the first semiconductor chip and the second semiconductor chip (Fig.5, element #8).
Sakano does not teach a second molding member on the first molding member. Waragaya teaches a second molding member on the first molding member (Fig.1, element #14 can be made of epoxy resin, paragraph [0067], rows 6-8). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Waragaya and disclose a second molding member on the first molding member. As disclosed by Waragaya, the top surface of the second molding can act as a light emitting surface, improving light emitting efficiency (paragraph [0061]).
Sakano further teaches wherein the first molding member comprises a first molding portion on the first semiconductor chip (Fig.5, first portion is the portion of element #8 located between the wires of the leftmost element #5 and containing the large particles shown in the figure) and a second molding portion between the first and second semiconductor chips (Fig.5, second portion is the portion to the right side of the right side wire of the leftmost element #5, located as the same heigh) and wherein the first molding portion and the second molding portion are arranged at a same height above the package substrate (the condition is satisfied based on the above choice of the portions) and a ratio per unit volume of a filler material included in the first molding portion is greater than a ratio per unit volume of the filler material included in the second molding portion (Fig.1, the large size particles account 90 vol % and are precipitated near the chip, while the small size particles are dispersed in the surrounding area, paragraph [0103], rows 1-5, paragraph [106], rows 16-26).
Regarding claim 2, the combination of Sakano and Waragaya teaches the semiconductor package of claim 1, as set forth in the obviousness rejection. Sakano further teaches the semiconductor package of claim 1, wherein an average particle size of the filler material included in the first molding portion is greater than an average particle size of the filler material included in the second molding portion (the first portion include the larger particles, element #81 and the second portions include the smaller particles, element #82).
Regarding claim 11, Sakano teaches a semiconductor package, comprising: a package substrate (Fig.5; element #2) comprising a first mounting region a relationship (Fig.5, region of the substrate on which the leftmost chip, element #5 is mounted); and a second mounting region adjacent to the first mounting region and spaced-apart from the first mounting region along a horizontal direction (Fig.5, region of the substrate on which the second from the left chip, element #5 is mounted); a first semiconductor chip mounted on the first mounting region (Fig.5, leftmost element #5), and a second semiconductor chip mounted on the second mounting region (Fig.5, second from the left element #5); a first molding member on the package substrate covering the first semiconductor chip and the second semiconductor chip (Fig.5, element #8), wherein the first molding member comprises a first cover portion covering the first semiconductor chip on the first mounting region (Fig.5, first portion is the portion of element #8 located between the wires of the leftmost element #5 and containing the large particles shown in the figure) and a second cover portion between the first and second mounting regions (Fig.5, second portion is the portion to the right side of the right side wire of the leftmost element #5, located as the same heigh).
Sakano does not teach a second molding member on the first molding member. Waragaya teaches a second molding member on the first molding member (Fig.1, element #14 can be made of epoxy resin, paragraph [0067], rows 6-8). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Waragaya and disclose a second molding member on the first molding member. As disclosed by Waragaya, the top surface of the second molding can act as a light emitting surface, improving light emitting efficiency (paragraph [0061]).
Sakano further teaches wherein the first cover portion and the second cover portion are arranged adjacent along the horizontal direction (condition is satisfied based on the above choice of the two portions) and a ratio per unit volume of a filler material included in the first cover portion is greater than a ratio per unit volume of the filler material included in the second cover portion (Fig.1, the large size particles account 90 vol % and are precipitated near the chip, while the small size particles are dispersed in the surrounding area, paragraph [0103], rows 1-5, paragraph [106], rows 16-26).
Regarding claim 12, the combination of Sakano and Waragaya teaches the semiconductor package of claim 11, as set forth in the obviousness rejection. Sakano further teaches the semiconductor package of claim 11, wherein an average particle size of the filler material included in the first molding portion is greater than an average particle size of the filler material included in the second molding portion (the first portion include the larger particles, element #81 and the second portions include the smaller particles, element #82).
Response to Arguments
Applicant’s arguments filed on 12/13/2025 have been fully considered but they
are not persuasive. Applicant’s arguments with respect to claims 1, 11 and 21 have been considered but are moot because the new ground of rejection does not rely on any reference as applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CRISTIAN A TIVARUS whose telephone number is (703)756-4688. The examiner can normally be reached Monday- Friday 8:00 AM -5:00 PM EST.
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/CRISTIAN A TIVARUS/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899