DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7, 9-13, and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. US 2017/0358518 in view of Lu et al. US 2019/0129023.
Re claim 1, Wu teaches an apparatus comprising:
a die (112, fig1, [14]);
integrated circuitry within the die (chip in 112, fig1, [14]);
a mold (104, fig1, [19]) that at least partially surrounds the die (112, fig1, [14]), wherein the mold has a first dielectric constant (dielectric constant of 104, fig1, [19]); and
a dielectric material (120b as PI, 120d as PI, fig1, [21]) on the mold, wherein the dielectric material has a second dielectric constant (PI with dielectric constant lower than 2.11, teaching reference Ha et al. US 2025/0066285, [28]).
Wu does not explicitly show wherein a first value of the second dielectric constant is smaller than a second value of the first dielectric constant.
Lu teaches using a molding compound with dielectric constant ranging between 3.3 and 3.4 (30, fig4, [28]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Wu and Lu to use a molding compound with dielectric constant ranging between 3.3 and 3.4. The motivation to do so is to achieve low moisture permeability and low thermal coefficient of expansion to avoid exposure of the encapsulated chip to moisture and mechanical stress (Lu, [28]).
Re claim 2, Wu modified above teaches the apparatus of claim 1, wherein at least a portion of the dielectric material (Wu, 120b as PI, 120d as PI, fig1, [21]) is above the integrated circuitry (chip in 112, fig1, [14]), and wherein the dielectric material reduces a capacitance of the apparatus (The language constitutes functional language and while features of an apparatus may be recited either structurally or functionally, claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997). As best can be determined by the Examiner from the specification of the present application, the structure which performs the function "reduces a capacitance of the apparatus” is simply the existence of “a low dielectric constant PI material” (see Paragraphs 48 and 88 of the published present application's specification), a structure which is clearly present in the device of Wu et al. as modified by Lu et al.. Therefore, it appears the structure of Wu fig1 as modified by Lu is capable of performing the function required by the claim language.).
Re claim 3, Wu modified above teaches the apparatus of claim 1, wherein the mold includes one or more cavities (Wu, cavity of 120a in 104, fig1, [19]), and wherein the one or more cavities are at least partially filled with the dielectric material (Wu, 120b as PI, 120d as PI, fig1, [21]).
Re claim 4, Wu modified above teaches the apparatus of claim 1, wherein a portion of the dielectric material is directly physically coupled with the die (Wu, 120b as PI in contact with 112, fig1, [19, 21]).
Re claim 5, Wu modified above teaches the apparatus of claim 1, wherein the dielectric material is a layer parallel to a surface of the die (Wu, part of 120b as PI, 120d as PI located above 104, fig1, [19, 21]).
Re claim 6, Wu modified above teaches the apparatus of claim 5, wherein the dielectric material (Wu, 120b as PI, 120d as PI, fig1, [21]) extends to at least one side of the die (Wu, 112, fig1, [14]), wherein the at least one side of the die is perpendicular to the surface of the die (Wu, side surface of 112 perpendicular to 112b, fig1).
Re claim 7, Wu modified above teaches the apparatus of claim 1, wherein the dielectric material includes a selected one or more of: a modified poly imide (PI) resin (Wu, 120b as PI, 120d as PI, fig1, [21]), a liquid crystal polymer (LCP) resin, a covalent organic framework film (COF), a polytetrafluoroethylene (PTFE) polymer, or air.
Re claim 9, Wu modified above teaches the apparatus of claim 1, wherein a surface of the die (Wu, 112a, fig1, [15]) includes one or more electrical contacts (Wu, 114, fig1, [16]) that are electrically coupled with the integrated circuitry (chip in 112, fig1, [14]).
Re claim 10, Wu teaches a package (fig1) comprising:
a die that includes integrated circuitry (112, fig1, [14]);
a first set of electrical connections (114, fig1, [16]) at a first side of the die (112a, fig1, [16]), wherein the first set of electrical connections is coupled with the integrated circuitry (fig1);
a redistribution layer (132, fig1, [23]) on the first side of the die (112a, fig1, [16]), wherein a first side of the redistribution layer (side of 132 facing 112, fig1, [23]) is electrically coupled (134, 118, fig1, [28]) with at least one of the first set of electrical connections (114, 118, fig1, [18]) at the first side of the die;
a second set of electrical connections (130, 134, fig1, [27, 28]) on a second side of the redistribution layer (side of 132 facing 126, fig1, [23, 24]) opposite the first side of the redistribution layer, wherein the second set of electrical connections (130, 134, fig1, [27, 28]) are electrically coupled with the first set of electrical connections (114,118, fig1, [18]);
a mold compound (104, fig1, [19]) surrounding at least a portion of the die, wherein the mold compound is in direct physical contact with at least a portion of a second side of the die (112b, fig1, [15]) opposite the first side of the die (112a, fig1, [16]); and
a dielectric material (120b as PI, 120d as PI, fig1, [21]) coupled with the mold compound (104, fig1, [19]), wherein at least a portion of the mold compound (104, fig1, [19]) is between the dielectric material (120b as PI, 120d as PI, fig1, [21]) and the die (112, fig1, [14]), wherein the mold compound has a first dielectric constant of a first value (dielectric constant of 104, fig1, [19]), wherein the dielectric material has a second dielectric constant (120b as PI, 120d as PI, fig1, [21]) of a second value (PI with dielectric constant lower than 2.11, teaching reference Ha et al. US 2025/0066285, [28]).
Wu does not explicitly show wherein the first value is greater than the second value.
Lu teaches using a molding compound with dielectric constant ranging between 3.3 and 3.4 (30, fig4, [28]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Wu and Lu to use a molding compound with dielectric constant ranging between 3.3 and 3.4. The motivation to do so is to achieve low moisture permeability and low thermal coefficient of expansion to avoid exposure of the encapsulated chip to moisture and mechanical stress (Lu, [28]).
Re claim 11, Wu modified above teaches the package of claim 10, wherein the first value is greater than or equal to 3 (Lu, 30 dielectric constant ranging between 3.3 and 3.4, fig4, [28]), and wherein the second value is less than or equal to 3 (PI with dielectric constant lower than 2.11, teaching reference Ha et al. US 2025/0066285, [28]).
Re claim 12, Wu modified above teaches the package of claim 10, wherein the mold compound includes one or more cavities (Wu, cavity of 120a in 104 and cavity in 104 holding 108, fig1, [13, 19]), wherein the one or more cavities are at least partially filled with the dielectric material (Wu, 120b as PI, 120d as PI, fig1, [21]), and wherein at least one of the one or more cavities are proximate to the integrated circuitry (fig1).
Re claim 13, Wu modified above teaches the package of claim 12, wherein the one or more cavities (Wu, cavity of 120a in 104, fig1, [19]) are surrounded by the mold compound (Wu, 104, fig1, [19]).
Re claim 17, Wu modified above teaches the package of claim 10, wherein the first set of electrical connections or the second set of electrical connections include solder balls (118b, 134b, fig1, [18, 28]).
Re claim 18, Wu teaches a method comprising:
providing a die (112, fig1, [14]),
wherein the die has a first side (112a, fig1, [16]) and a second side (112b, fig1, [16]) opposite the first side,
wherein the die includes integrated circuitry (chip in 112, fig1, [14]), and wherein the first side of the die (112a, fig1, [16]) includes one or more electrical connections (114, 118, fig1, [18]);
forming a mold (104, fig1, [19]) at least partially around the die, wherein the mold is physically coupled with at least a portion of the second side of the die (112b, fig1, [16]); and
forming a dielectric material (120b as PI, 120d as PI, fig1, [21]) on the mold, wherein at least a portion of the mold is between the dielectric material and the die (fig1),
wherein the mold has a first dielectric constant with a first value (dielectric constant of 104, fig1, [19]),
wherein the dielectric material (120b as PI, 120d as PI, fig1, [21]) has a second dielectric constant with a second value (PI with dielectric constant lower than 2.11, teaching reference Ha et al. US 2025/0066285, [28]).
Wu does not explicitly show wherein the first value is larger than the second value.
Lu teaches using a molding compound with dielectric constant ranging between 3.3 and 3.4 (30, fig4, [28]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Wu and Lu to use a molding compound with dielectric constant ranging between 3.3 and 3.4. The motivation to do so is to achieve low moisture permeability and low thermal coefficient of expansion to avoid exposure of the encapsulated chip to moisture and mechanical stress (Lu, [28]).
Re claim 19, Wu modified above teaches the method of claim 18, wherein forming the mold further comprises forming the mold that includes one or more cavities within the mold (Wu, cavity of 120a in 104 and cavity in 104 holding 108, fig1, [13, 19]), and wherein forming the dielectric material (Wu, 120b as PI, 120d as PI, fig1, [21]) on the mold further comprises forming the dielectric material in at least a portion of the one or more cavities (fig1).
Re claim 20, Wu modified above teaches the method of claim 18, wherein the dielectric material includes a selected one or more of: a modified poly imide (PI) resin (Wu, 120b as PI, 120d as PI, fig1, [21]), a liquid crystal polymer (LCP) resin, a covalent organic framework film (COF), a polytetrafluoroethylene (PTFE) polymer, or air.
Claim(s) 8 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. US 2017/0358518 in view of Lu et al. US 2019/0129023 and Karhade et al. US 2020/0273768.
Re claim 8, Wu does not explicitly show the apparatus of claim 1, wherein a thickness of the dielectric material ranges from 10 micrometers to 10 millimeters, and a thickness of the mold ranges from 10 micrometers to 10 millimeters.
Karhade teaches a thickness of IC die of 100-250 µm (T2, fig2A, [25]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Wu and Lu to adjust the thickness of the molding compound and the dielectric material according to the thickness of the IC die. The motivation to do so is to achieve low moisture permeability and low thermal coefficient of expansion to avoid exposure of the encapsulated chip to moisture and mechanical stress (Lu, [28]) according to the function of the IC die (Karhade, [25]).
Re claim 15, Wu modified above teaches the package of claim 10, wherein the dielectric material includes a selected one or more of: a modified poly imide (PI) resin (Wu, 120b as PI, 120d as PI, fig1, [21]), a liquid crystal polymer (LCP) resin, a covalent organic framework film (COF), a polytetrafluoroethylene (PTFE) polymer, or air,
Wu does not explicitly show wherein a thickness of the dielectric material ranges from 10 micrometers to 10 millimeters, and a thickness of the mold compound ranges from 10 micrometers to 10 millimeters.
Karhade teaches a thickness of IC die of 100-250 µm (T2, fig2A, [25]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Wu and Lu to adjust the thickness of the molding compound and the dielectric material according to the thickness of the IC die. The motivation to do so is to achieve low moisture permeability and low thermal coefficient of expansion to avoid exposure of the encapsulated chip to moisture and mechanical stress (Lu, [28]) according to the function of the IC die (Karhade, [25]).
Claim(s) 14 is rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. US 2017/0358518 in view of Lu et al. US 2019/0129023 and Matsuda et al. US 6380681.
Re claim 14, Wu modified above teaches the package of claim 12, wherein the one or more cavities (Wu, cavity in 104 holding 108, fig1, [13, 19])
Wu does not explicitly show thermally conductive paste in the cavity.
Matsuda teaches bumps formed with thermally conductive paste (25, fig3A, col4 line 20-35).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Wu modified above and Matsuda to use thermally conductive paste as the material of 118 and 134. The motivation to do so is to achieve stable electrical contact with low temperature process with small size (Matsuda, col4 line 20-25).
Claim(s) 16 is rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. US 2017/0358518 in view of Lu et al. US 2019/0129023 and Seidemann et al. US 2018/0204831.
Re claim 16, Wu does not explicitly show the package of claim 10, wherein the die includes electrostatic discharge protection structures.
Seidemann teaches the die (1110, fig12, [57]) includes electrostatic discharge protection structures (ESD 1140, fig12, [57]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Wu modified above and Seidemann to add an ESD structure in Wu 112. The motivation to do so is to inhibit ESD damage (Seidemann, [2]).
Conclusion
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/XIAOMING LIU/Examiner, Art Unit 2812
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